1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx  | FileCheck %s --check-prefixes=CHECK,AVX
4
5define { i64, i64 } @PR46189(double %0, double %1, double %2, double %3, double %4) {
6; SSE-LABEL: PR46189:
7; SSE:       # %bb.0:
8; SSE-NEXT:    movapd %xmm0, %xmm5
9; SSE-NEXT:    subsd %xmm2, %xmm5
10; SSE-NEXT:    addsd %xmm2, %xmm0
11; SSE-NEXT:    unpcklpd {{.*#+}} xmm5 = xmm5[0],xmm0[0]
12; SSE-NEXT:    unpcklpd {{.*#+}} xmm3 = xmm3[0,0]
13; SSE-NEXT:    divpd %xmm3, %xmm5
14; SSE-NEXT:    cvttpd2dq %xmm5, %xmm0
15; SSE-NEXT:    movapd %xmm1, %xmm3
16; SSE-NEXT:    subsd %xmm2, %xmm3
17; SSE-NEXT:    addsd %xmm2, %xmm1
18; SSE-NEXT:    unpcklpd {{.*#+}} xmm3 = xmm3[0],xmm1[0]
19; SSE-NEXT:    unpcklpd {{.*#+}} xmm4 = xmm4[0,0]
20; SSE-NEXT:    divpd %xmm4, %xmm3
21; SSE-NEXT:    cvttpd2dq %xmm3, %xmm1
22; SSE-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
23; SSE-NEXT:    movq %xmm0, %rax
24; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
25; SSE-NEXT:    movq %xmm0, %rdx
26; SSE-NEXT:    retq
27;
28; AVX-LABEL: PR46189:
29; AVX:       # %bb.0:
30; AVX-NEXT:    vsubsd %xmm2, %xmm0, %xmm5
31; AVX-NEXT:    vaddsd %xmm2, %xmm0, %xmm0
32; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm5[0],xmm0[0]
33; AVX-NEXT:    vmovddup {{.*#+}} xmm3 = xmm3[0,0]
34; AVX-NEXT:    vdivpd %xmm3, %xmm0, %xmm0
35; AVX-NEXT:    vcvttpd2dq %xmm0, %xmm0
36; AVX-NEXT:    vsubsd %xmm2, %xmm1, %xmm3
37; AVX-NEXT:    vaddsd %xmm2, %xmm1, %xmm1
38; AVX-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm3[0],xmm1[0]
39; AVX-NEXT:    vmovddup {{.*#+}} xmm2 = xmm4[0,0]
40; AVX-NEXT:    vdivpd %xmm2, %xmm1, %xmm1
41; AVX-NEXT:    vcvttpd2dq %xmm1, %xmm1
42; AVX-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
43; AVX-NEXT:    vmovq %xmm0, %rax
44; AVX-NEXT:    vpextrq $1, %xmm0, %rdx
45; AVX-NEXT:    retq
46  %6 = insertelement <2 x double> undef, double %0, i32 0
47  %7 = shufflevector <2 x double> %6, <2 x double> undef, <2 x i32> zeroinitializer
48  %8 = insertelement <2 x double> undef, double %2, i32 0
49  %9 = shufflevector <2 x double> %8, <2 x double> undef, <2 x i32> zeroinitializer
50  %10 = fsub <2 x double> %7, %9
51  %11 = fadd <2 x double> %7, %9
52  %12 = shufflevector <2 x double> %10, <2 x double> %11, <2 x i32> <i32 0, i32 3>
53  %13 = insertelement <2 x double> undef, double %3, i32 0
54  %14 = shufflevector <2 x double> %13, <2 x double> undef, <2 x i32> zeroinitializer
55  %15 = fdiv <2 x double> %12, %14
56  %16 = fptosi <2 x double> %15 to <2 x i32>
57  %17 = insertelement <2 x double> undef, double %1, i32 0
58  %18 = shufflevector <2 x double> %17, <2 x double> undef, <2 x i32> zeroinitializer
59  %19 = fsub <2 x double> %18, %9
60  %20 = fadd <2 x double> %18, %9
61  %21 = shufflevector <2 x double> %19, <2 x double> %20, <2 x i32> <i32 0, i32 3>
62  %22 = insertelement <2 x double> undef, double %4, i32 0
63  %23 = shufflevector <2 x double> %22, <2 x double> undef, <2 x i32> zeroinitializer
64  %24 = fdiv <2 x double> %21, %23
65  %25 = fptosi <2 x double> %24 to <2 x i32>
66  %26 = zext <2 x i32> %25 to <2 x i64>
67  %27 = shl nuw <2 x i64> %26, <i64 32, i64 32>
68  %28 = zext <2 x i32> %16 to <2 x i64>
69  %29 = or <2 x i64> %27, %28
70  %30 = extractelement <2 x i64> %29, i32 0
71  %31 = insertvalue { i64, i64 } undef, i64 %30, 0
72  %32 = extractelement <2 x i64> %29, i32 1
73  %33 = insertvalue { i64, i64 } %31, i64 %32, 1
74  ret { i64, i64 } %33
75}
76
77