1 // Copyright 2015, ARM Limited
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
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13 // used to endorse or promote products derived from this software without
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15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 #ifndef VIXL_A64_CONSTANTS_A64_H_
28 #define VIXL_A64_CONSTANTS_A64_H_
29
30 #include <stdint.h>
31
32 #include "jit/arm64/vixl/Globals-vixl.h"
33
34 namespace vixl {
35
36 // Supervisor Call (svc) specific support.
37 //
38 // The SVC instruction encodes an optional 16-bit immediate value.
39 // The simulator understands the codes below.
40 enum SVCSimulatorCodes {
41 kCallRtRedirected = 0x10, // Transition to x86_64 C code.
42 kMarkStackPointer = 0x11, // Push the current SP on a special Simulator stack.
43 kCheckStackPointer = 0x12 // Pop from the special Simulator stack and compare to SP.
44 };
45
46 const unsigned kNumberOfRegisters = 32;
47 const unsigned kNumberOfVRegisters = 32;
48 const unsigned kNumberOfFPRegisters = kNumberOfVRegisters;
49 // Callee saved registers are x21-x30(lr).
50 const int kNumberOfCalleeSavedRegisters = 10;
51 const int kFirstCalleeSavedRegisterIndex = 21;
52 // Callee saved FP registers are d8-d15. Note that the high parts of v8-v15 are
53 // still caller-saved.
54 const int kNumberOfCalleeSavedFPRegisters = 8;
55 const int kFirstCalleeSavedFPRegisterIndex = 8;
56
57 #define REGISTER_CODE_LIST(R) \
58 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
59 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
60 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
61 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
62
63 #define INSTRUCTION_FIELDS_LIST(V_) \
64 /* Register fields */ \
65 V_(Rd, 4, 0, Bits) /* Destination register. */ \
66 V_(Rn, 9, 5, Bits) /* First source register. */ \
67 V_(Rm, 20, 16, Bits) /* Second source register. */ \
68 V_(Ra, 14, 10, Bits) /* Third source register. */ \
69 V_(Rt, 4, 0, Bits) /* Load/store register. */ \
70 V_(Rt2, 14, 10, Bits) /* Load/store second register. */ \
71 V_(Rs, 20, 16, Bits) /* Exclusive access status. */ \
72 \
73 /* Common bits */ \
74 V_(SixtyFourBits, 31, 31, Bits) \
75 V_(FlagsUpdate, 29, 29, Bits) \
76 \
77 /* PC relative addressing */ \
78 V_(ImmPCRelHi, 23, 5, SignedBits) \
79 V_(ImmPCRelLo, 30, 29, Bits) \
80 \
81 /* Add/subtract/logical shift register */ \
82 V_(ShiftDP, 23, 22, Bits) \
83 V_(ImmDPShift, 15, 10, Bits) \
84 \
85 /* Add/subtract immediate */ \
86 V_(ImmAddSub, 21, 10, Bits) \
87 V_(ShiftAddSub, 23, 22, Bits) \
88 \
89 /* Add/substract extend */ \
90 V_(ImmExtendShift, 12, 10, Bits) \
91 V_(ExtendMode, 15, 13, Bits) \
92 \
93 /* Move wide */ \
94 V_(ImmMoveWide, 20, 5, Bits) \
95 V_(ShiftMoveWide, 22, 21, Bits) \
96 \
97 /* Logical immediate, bitfield and extract */ \
98 V_(BitN, 22, 22, Bits) \
99 V_(ImmRotate, 21, 16, Bits) \
100 V_(ImmSetBits, 15, 10, Bits) \
101 V_(ImmR, 21, 16, Bits) \
102 V_(ImmS, 15, 10, Bits) \
103 \
104 /* Test and branch immediate */ \
105 V_(ImmTestBranch, 18, 5, SignedBits) \
106 V_(ImmTestBranchBit40, 23, 19, Bits) \
107 V_(ImmTestBranchBit5, 31, 31, Bits) \
108 \
109 /* Conditionals */ \
110 V_(Condition, 15, 12, Bits) \
111 V_(ConditionBranch, 3, 0, Bits) \
112 V_(Nzcv, 3, 0, Bits) \
113 V_(ImmCondCmp, 20, 16, Bits) \
114 V_(ImmCondBranch, 23, 5, SignedBits) \
115 \
116 /* Floating point */ \
117 V_(FPType, 23, 22, Bits) \
118 V_(ImmFP, 20, 13, Bits) \
119 V_(FPScale, 15, 10, Bits) \
120 \
121 /* Load Store */ \
122 V_(ImmLS, 20, 12, SignedBits) \
123 V_(ImmLSUnsigned, 21, 10, Bits) \
124 V_(ImmLSPair, 21, 15, SignedBits) \
125 V_(ImmShiftLS, 12, 12, Bits) \
126 V_(LSOpc, 23, 22, Bits) \
127 V_(LSVector, 26, 26, Bits) \
128 V_(LSSize, 31, 30, Bits) \
129 V_(ImmPrefetchOperation, 4, 0, Bits) \
130 V_(PrefetchHint, 4, 3, Bits) \
131 V_(PrefetchTarget, 2, 1, Bits) \
132 V_(PrefetchStream, 0, 0, Bits) \
133 \
134 /* Other immediates */ \
135 V_(ImmUncondBranch, 25, 0, SignedBits) \
136 V_(ImmCmpBranch, 23, 5, SignedBits) \
137 V_(ImmLLiteral, 23, 5, SignedBits) \
138 V_(ImmException, 20, 5, Bits) \
139 V_(ImmHint, 11, 5, Bits) \
140 V_(ImmBarrierDomain, 11, 10, Bits) \
141 V_(ImmBarrierType, 9, 8, Bits) \
142 \
143 /* System (MRS, MSR, SYS) */ \
144 V_(ImmSystemRegister, 19, 5, Bits) \
145 V_(SysO0, 19, 19, Bits) \
146 V_(SysOp, 18, 5, Bits) \
147 V_(SysOp1, 18, 16, Bits) \
148 V_(SysOp2, 7, 5, Bits) \
149 V_(CRn, 15, 12, Bits) \
150 V_(CRm, 11, 8, Bits) \
151 \
152 /* Load-/store-exclusive */ \
153 V_(LdStXLoad, 22, 22, Bits) \
154 V_(LdStXNotExclusive, 23, 23, Bits) \
155 V_(LdStXAcquireRelease, 15, 15, Bits) \
156 V_(LdStXSizeLog2, 31, 30, Bits) \
157 V_(LdStXPair, 21, 21, Bits) \
158 \
159 /* NEON generic fields */ \
160 V_(NEONQ, 30, 30, Bits) \
161 V_(NEONSize, 23, 22, Bits) \
162 V_(NEONLSSize, 11, 10, Bits) \
163 V_(NEONS, 12, 12, Bits) \
164 V_(NEONL, 21, 21, Bits) \
165 V_(NEONM, 20, 20, Bits) \
166 V_(NEONH, 11, 11, Bits) \
167 V_(ImmNEONExt, 14, 11, Bits) \
168 V_(ImmNEON5, 20, 16, Bits) \
169 V_(ImmNEON4, 14, 11, Bits) \
170 \
171 /* NEON Modified Immediate fields */ \
172 V_(ImmNEONabc, 18, 16, Bits) \
173 V_(ImmNEONdefgh, 9, 5, Bits) \
174 V_(NEONModImmOp, 29, 29, Bits) \
175 V_(NEONCmode, 15, 12, Bits) \
176 \
177 /* NEON Shift Immediate fields */ \
178 V_(ImmNEONImmhImmb, 22, 16, Bits) \
179 V_(ImmNEONImmh, 22, 19, Bits) \
180 V_(ImmNEONImmb, 18, 16, Bits)
181
182 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
183 /* NZCV */ \
184 V_(Flags, 31, 28, Bits) \
185 V_(N, 31, 31, Bits) \
186 V_(Z, 30, 30, Bits) \
187 V_(C, 29, 29, Bits) \
188 V_(V, 28, 28, Bits) \
189 M_(NZCV, Flags_mask) \
190 /* FPCR */ \
191 V_(AHP, 26, 26, Bits) \
192 V_(DN, 25, 25, Bits) \
193 V_(FZ, 24, 24, Bits) \
194 V_(RMode, 23, 22, Bits) \
195 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
196
197 // Fields offsets.
198 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \
199 const int Name##_offset = LowBit; \
200 const int Name##_width = HighBit - LowBit + 1; \
201 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
202 #define NOTHING(A, B)
203 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS)
204 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING)
205 #undef NOTHING
206 #undef DECLARE_FIELDS_BITS
207
208 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed
209 // from ImmPCRelLo and ImmPCRelHi.
210 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;
211
212 // Condition codes.
213 enum Condition {
214 eq = 0, // Z set Equal.
215 ne = 1, // Z clear Not equal.
216 cs = 2, // C set Carry set.
217 cc = 3, // C clear Carry clear.
218 mi = 4, // N set Negative.
219 pl = 5, // N clear Positive or zero.
220 vs = 6, // V set Overflow.
221 vc = 7, // V clear No overflow.
222 hi = 8, // C set, Z clear Unsigned higher.
223 ls = 9, // C clear or Z set Unsigned lower or same.
224 ge = 10, // N == V Greater or equal.
225 lt = 11, // N != V Less than.
226 gt = 12, // Z clear, N == V Greater than.
227 le = 13, // Z set or N != V Less then or equal
228 al = 14, // Always.
229 nv = 15, // Behaves as always/al.
230
231 // Aliases.
232 hs = cs, // C set Unsigned higher or same.
233 lo = cc, // C clear Unsigned lower.
234
235 // Mozilla expanded aliases.
236 Equal = 0, Zero = 0,
237 NotEqual = 1, NonZero = 1,
238 AboveOrEqual = 2, CarrySet = 2,
239 Below = 3, CarryClear = 3,
240 Signed = 4,
241 NotSigned = 5,
242 Overflow = 6,
243 NoOverflow = 7,
244 Above = 8,
245 BelowOrEqual = 9,
246 GreaterThanOrEqual_ = 10,
247 LessThan_ = 11,
248 GreaterThan_ = 12,
249 LessThanOrEqual_ = 13,
250 Always = 14,
251 Never = 15
252 };
253
InvertCondition(Condition cond)254 inline Condition InvertCondition(Condition cond) {
255 // Conditions al and nv behave identically, as "always true". They can't be
256 // inverted, because there is no "always false" condition.
257 VIXL_ASSERT((cond != al) && (cond != nv));
258 return static_cast<Condition>(cond ^ 1);
259 }
260
261 enum FPTrapFlags {
262 EnableTrap = 1,
263 DisableTrap = 0
264 };
265
266 enum FlagsUpdate {
267 SetFlags = 1,
268 LeaveFlags = 0
269 };
270
271 enum StatusFlags {
272 NoFlag = 0,
273
274 // Derive the flag combinations from the system register bit descriptions.
275 NFlag = N_mask,
276 ZFlag = Z_mask,
277 CFlag = C_mask,
278 VFlag = V_mask,
279 NZFlag = NFlag | ZFlag,
280 NCFlag = NFlag | CFlag,
281 NVFlag = NFlag | VFlag,
282 ZCFlag = ZFlag | CFlag,
283 ZVFlag = ZFlag | VFlag,
284 CVFlag = CFlag | VFlag,
285 NZCFlag = NFlag | ZFlag | CFlag,
286 NZVFlag = NFlag | ZFlag | VFlag,
287 NCVFlag = NFlag | CFlag | VFlag,
288 ZCVFlag = ZFlag | CFlag | VFlag,
289 NZCVFlag = NFlag | ZFlag | CFlag | VFlag,
290
291 // Floating-point comparison results.
292 FPEqualFlag = ZCFlag,
293 FPLessThanFlag = NFlag,
294 FPGreaterThanFlag = CFlag,
295 FPUnorderedFlag = CVFlag
296 };
297
298 enum Shift {
299 NO_SHIFT = -1,
300 LSL = 0x0,
301 LSR = 0x1,
302 ASR = 0x2,
303 ROR = 0x3,
304 MSL = 0x4
305 };
306
307 enum Extend {
308 NO_EXTEND = -1,
309 UXTB = 0,
310 UXTH = 1,
311 UXTW = 2,
312 UXTX = 3,
313 SXTB = 4,
314 SXTH = 5,
315 SXTW = 6,
316 SXTX = 7
317 };
318
319 enum SystemHint {
320 NOP = 0,
321 YIELD = 1,
322 WFE = 2,
323 WFI = 3,
324 SEV = 4,
325 SEVL = 5,
326 ESB = 16,
327 CSDB = 20,
328 BTI = 32,
329 BTI_c = 34,
330 BTI_j = 36,
331 BTI_jc = 38
332 };
333
334 enum BranchTargetIdentifier {
335 EmitBTI_none = NOP,
336 EmitBTI = BTI,
337 EmitBTI_c = BTI_c,
338 EmitBTI_j = BTI_j,
339 EmitBTI_jc = BTI_jc,
340
341 // These correspond to the values of the CRm:op2 fields in the equivalent HINT
342 // instruction.
343 EmitPACIASP = 25,
344 EmitPACIBSP = 27
345 };
346
347 enum BarrierDomain {
348 OuterShareable = 0,
349 NonShareable = 1,
350 InnerShareable = 2,
351 FullSystem = 3
352 };
353
354 enum BarrierType {
355 BarrierOther = 0,
356 BarrierReads = 1,
357 BarrierWrites = 2,
358 BarrierAll = 3
359 };
360
361 enum PrefetchOperation {
362 PLDL1KEEP = 0x00,
363 PLDL1STRM = 0x01,
364 PLDL2KEEP = 0x02,
365 PLDL2STRM = 0x03,
366 PLDL3KEEP = 0x04,
367 PLDL3STRM = 0x05,
368
369 PLIL1KEEP = 0x08,
370 PLIL1STRM = 0x09,
371 PLIL2KEEP = 0x0a,
372 PLIL2STRM = 0x0b,
373 PLIL3KEEP = 0x0c,
374 PLIL3STRM = 0x0d,
375
376 PSTL1KEEP = 0x10,
377 PSTL1STRM = 0x11,
378 PSTL2KEEP = 0x12,
379 PSTL2STRM = 0x13,
380 PSTL3KEEP = 0x14,
381 PSTL3STRM = 0x15
382 };
383
384 enum BType {
385 // Set when executing any instruction on a guarded page, except those cases
386 // listed below.
387 DefaultBType = 0,
388
389 // Set when an indirect branch is taken from an unguarded page to a guarded
390 // page, or from a guarded page to ip0 or ip1 (x16 or x17), eg "br ip0".
391 BranchFromUnguardedOrToIP = 1,
392
393 // Set when an indirect branch and link (call) is taken, eg. "blr x0".
394 BranchAndLink = 2,
395
396 // Set when an indirect branch is taken from a guarded page to a register
397 // that is not ip0 or ip1 (x16 or x17), eg, "br x0".
398 BranchFromGuardedNotToIP = 3
399 };
400
401 template<int op0, int op1, int crn, int crm, int op2>
402 class SystemRegisterEncoder {
403 public:
404 static const uint32_t value =
405 ((op0 << SysO0_offset) |
406 (op1 << SysOp1_offset) |
407 (crn << CRn_offset) |
408 (crm << CRm_offset) |
409 (op2 << SysOp2_offset)) >> ImmSystemRegister_offset;
410 };
411
412 // System/special register names.
413 // This information is not encoded as one field but as the concatenation of
414 // multiple fields (Op0, Op1, Crn, Crm, Op2).
415 enum SystemRegister {
416 NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value,
417 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value,
418 RNDR = SystemRegisterEncoder<3, 3, 2, 4, 0>::value, // Random number.
419 RNDRRS = SystemRegisterEncoder<3, 3, 2, 4, 1>::value // Reseeded random number.
420 };
421
422 template<int op1, int crn, int crm, int op2>
423 class CacheOpEncoder {
424 public:
425 static const uint32_t value =
426 ((op1 << SysOp1_offset) |
427 (crn << CRn_offset) |
428 (crm << CRm_offset) |
429 (op2 << SysOp2_offset)) >> SysOp_offset;
430 };
431
432 enum InstructionCacheOp {
433 IVAU = CacheOpEncoder<3, 7, 5, 1>::value
434 };
435
436 enum DataCacheOp {
437 CVAC = CacheOpEncoder<3, 7, 10, 1>::value,
438 CVAU = CacheOpEncoder<3, 7, 11, 1>::value,
439 CVAP = CacheOpEncoder<3, 7, 12, 1>::value,
440 CVADP = CacheOpEncoder<3, 7, 13, 1>::value,
441 CIVAC = CacheOpEncoder<3, 7, 14, 1>::value,
442 ZVA = CacheOpEncoder<3, 7, 4, 1>::value
443 };
444
445 // Instruction enumerations.
446 //
447 // These are the masks that define a class of instructions, and the list of
448 // instructions within each class. Each enumeration has a Fixed, FMask and
449 // Mask value.
450 //
451 // Fixed: The fixed bits in this instruction class.
452 // FMask: The mask used to extract the fixed bits in the class.
453 // Mask: The mask used to identify the instructions within a class.
454 //
455 // The enumerations can be used like this:
456 //
457 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
458 // switch(instr->Mask(PCRelAddressingMask)) {
459 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
460 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
461 // default: printf("Unknown instruction\n");
462 // }
463
464
465 // Generic fields.
466 enum GenericInstrField {
467 SixtyFourBits = 0x80000000,
468 ThirtyTwoBits = 0x00000000,
469
470 FPTypeMask = 0x00C00000,
471 FP16 = 0x00C00000,
472 FP32 = 0x00000000,
473 FP64 = 0x00400000
474 };
475
476 enum NEONFormatField {
477 NEONFormatFieldMask = 0x40C00000,
478 NEON_Q = 0x40000000,
479 NEON_8B = 0x00000000,
480 NEON_16B = NEON_8B | NEON_Q,
481 NEON_4H = 0x00400000,
482 NEON_8H = NEON_4H | NEON_Q,
483 NEON_2S = 0x00800000,
484 NEON_4S = NEON_2S | NEON_Q,
485 NEON_1D = 0x00C00000,
486 NEON_2D = 0x00C00000 | NEON_Q
487 };
488
489 enum NEONFPFormatField {
490 NEONFPFormatFieldMask = 0x40400000,
491 NEON_FP_4H = FP16,
492 NEON_FP_2S = FP32,
493 NEON_FP_8H = FP16 | NEON_Q,
494 NEON_FP_4S = FP32 | NEON_Q,
495 NEON_FP_2D = FP64 | NEON_Q
496 };
497
498 enum NEONLSFormatField {
499 NEONLSFormatFieldMask = 0x40000C00,
500 LS_NEON_8B = 0x00000000,
501 LS_NEON_16B = LS_NEON_8B | NEON_Q,
502 LS_NEON_4H = 0x00000400,
503 LS_NEON_8H = LS_NEON_4H | NEON_Q,
504 LS_NEON_2S = 0x00000800,
505 LS_NEON_4S = LS_NEON_2S | NEON_Q,
506 LS_NEON_1D = 0x00000C00,
507 LS_NEON_2D = LS_NEON_1D | NEON_Q
508 };
509
510 enum NEONScalarFormatField {
511 NEONScalarFormatFieldMask = 0x00C00000,
512 NEONScalar = 0x10000000,
513 NEON_B = 0x00000000,
514 NEON_H = 0x00400000,
515 NEON_S = 0x00800000,
516 NEON_D = 0x00C00000
517 };
518
519 // PC relative addressing.
520 enum PCRelAddressingOp {
521 PCRelAddressingFixed = 0x10000000,
522 PCRelAddressingFMask = 0x1F000000,
523 PCRelAddressingMask = 0x9F000000,
524 ADR = PCRelAddressingFixed | 0x00000000,
525 ADRP = PCRelAddressingFixed | 0x80000000
526 };
527
528 // Add/sub (immediate, shifted and extended.)
529 const int kSFOffset = 31;
530 enum AddSubOp {
531 AddSubOpMask = 0x60000000,
532 AddSubSetFlagsBit = 0x20000000,
533 ADD = 0x00000000,
534 ADDS = ADD | AddSubSetFlagsBit,
535 SUB = 0x40000000,
536 SUBS = SUB | AddSubSetFlagsBit
537 };
538
539 #define ADD_SUB_OP_LIST(V) \
540 V(ADD), \
541 V(ADDS), \
542 V(SUB), \
543 V(SUBS)
544
545 enum AddSubImmediateOp {
546 AddSubImmediateFixed = 0x11000000,
547 AddSubImmediateFMask = 0x1F000000,
548 AddSubImmediateMask = 0xFF000000,
549 #define ADD_SUB_IMMEDIATE(A) \
550 A##_w_imm = AddSubImmediateFixed | A, \
551 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
552 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE)
553 #undef ADD_SUB_IMMEDIATE
554 };
555
556 enum AddSubShiftedOp {
557 AddSubShiftedFixed = 0x0B000000,
558 AddSubShiftedFMask = 0x1F200000,
559 AddSubShiftedMask = 0xFF200000,
560 #define ADD_SUB_SHIFTED(A) \
561 A##_w_shift = AddSubShiftedFixed | A, \
562 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits
563 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED)
564 #undef ADD_SUB_SHIFTED
565 };
566
567 enum AddSubExtendedOp {
568 AddSubExtendedFixed = 0x0B200000,
569 AddSubExtendedFMask = 0x1F200000,
570 AddSubExtendedMask = 0xFFE00000,
571 #define ADD_SUB_EXTENDED(A) \
572 A##_w_ext = AddSubExtendedFixed | A, \
573 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits
574 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED)
575 #undef ADD_SUB_EXTENDED
576 };
577
578 // Add/sub with carry.
579 enum AddSubWithCarryOp {
580 AddSubWithCarryFixed = 0x1A000000,
581 AddSubWithCarryFMask = 0x1FE00000,
582 AddSubWithCarryMask = 0xFFE0FC00,
583 ADC_w = AddSubWithCarryFixed | ADD,
584 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits,
585 ADC = ADC_w,
586 ADCS_w = AddSubWithCarryFixed | ADDS,
587 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
588 SBC_w = AddSubWithCarryFixed | SUB,
589 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits,
590 SBC = SBC_w,
591 SBCS_w = AddSubWithCarryFixed | SUBS,
592 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits
593 };
594
595 // Rotate right into flags.
596 enum RotateRightIntoFlagsOp {
597 RotateRightIntoFlagsFixed = 0x1A000400,
598 RotateRightIntoFlagsFMask = 0x1FE07C00,
599 RotateRightIntoFlagsMask = 0xFFE07C10,
600 RMIF = RotateRightIntoFlagsFixed | 0xA0000000
601 };
602
603 // Evaluate into flags.
604 enum EvaluateIntoFlagsOp {
605 EvaluateIntoFlagsFixed = 0x1A000800,
606 EvaluateIntoFlagsFMask = 0x1FE03C00,
607 EvaluateIntoFlagsMask = 0xFFE07C1F,
608 SETF8 = EvaluateIntoFlagsFixed | 0x2000000D,
609 SETF16 = EvaluateIntoFlagsFixed | 0x2000400D
610 };
611
612 // Logical (immediate and shifted register).
613 enum LogicalOp {
614 LogicalOpMask = 0x60200000,
615 NOT = 0x00200000,
616 AND = 0x00000000,
617 BIC = AND | NOT,
618 ORR = 0x20000000,
619 ORN = ORR | NOT,
620 EOR = 0x40000000,
621 EON = EOR | NOT,
622 ANDS = 0x60000000,
623 BICS = ANDS | NOT
624 };
625
626 // Logical immediate.
627 enum LogicalImmediateOp {
628 LogicalImmediateFixed = 0x12000000,
629 LogicalImmediateFMask = 0x1F800000,
630 LogicalImmediateMask = 0xFF800000,
631 AND_w_imm = LogicalImmediateFixed | AND,
632 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits,
633 ORR_w_imm = LogicalImmediateFixed | ORR,
634 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
635 EOR_w_imm = LogicalImmediateFixed | EOR,
636 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits,
637 ANDS_w_imm = LogicalImmediateFixed | ANDS,
638 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
639 };
640
641 // Logical shifted register.
642 enum LogicalShiftedOp {
643 LogicalShiftedFixed = 0x0A000000,
644 LogicalShiftedFMask = 0x1F000000,
645 LogicalShiftedMask = 0xFF200000,
646 AND_w = LogicalShiftedFixed | AND,
647 AND_x = LogicalShiftedFixed | AND | SixtyFourBits,
648 AND_shift = AND_w,
649 BIC_w = LogicalShiftedFixed | BIC,
650 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits,
651 BIC_shift = BIC_w,
652 ORR_w = LogicalShiftedFixed | ORR,
653 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
654 ORR_shift = ORR_w,
655 ORN_w = LogicalShiftedFixed | ORN,
656 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
657 ORN_shift = ORN_w,
658 EOR_w = LogicalShiftedFixed | EOR,
659 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits,
660 EOR_shift = EOR_w,
661 EON_w = LogicalShiftedFixed | EON,
662 EON_x = LogicalShiftedFixed | EON | SixtyFourBits,
663 EON_shift = EON_w,
664 ANDS_w = LogicalShiftedFixed | ANDS,
665 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
666 ANDS_shift = ANDS_w,
667 BICS_w = LogicalShiftedFixed | BICS,
668 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
669 BICS_shift = BICS_w
670 };
671
672 // Move wide immediate.
673 enum MoveWideImmediateOp {
674 MoveWideImmediateFixed = 0x12800000,
675 MoveWideImmediateFMask = 0x1F800000,
676 MoveWideImmediateMask = 0xFF800000,
677 MOVN = 0x00000000,
678 MOVZ = 0x40000000,
679 MOVK = 0x60000000,
680 MOVN_w = MoveWideImmediateFixed | MOVN,
681 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
682 MOVZ_w = MoveWideImmediateFixed | MOVZ,
683 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
684 MOVK_w = MoveWideImmediateFixed | MOVK,
685 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits
686 };
687
688 // Bitfield.
689 const int kBitfieldNOffset = 22;
690 enum BitfieldOp {
691 BitfieldFixed = 0x13000000,
692 BitfieldFMask = 0x1F800000,
693 BitfieldMask = 0xFF800000,
694 SBFM_w = BitfieldFixed | 0x00000000,
695 SBFM_x = BitfieldFixed | 0x80000000,
696 SBFM = SBFM_w,
697 BFM_w = BitfieldFixed | 0x20000000,
698 BFM_x = BitfieldFixed | 0xA0000000,
699 BFM = BFM_w,
700 UBFM_w = BitfieldFixed | 0x40000000,
701 UBFM_x = BitfieldFixed | 0xC0000000,
702 UBFM = UBFM_w
703 // Bitfield N field.
704 };
705
706 // Extract.
707 enum ExtractOp {
708 ExtractFixed = 0x13800000,
709 ExtractFMask = 0x1F800000,
710 ExtractMask = 0xFFA00000,
711 EXTR_w = ExtractFixed | 0x00000000,
712 EXTR_x = ExtractFixed | 0x80000000,
713 EXTR = EXTR_w
714 };
715
716 // Unconditional branch.
717 enum UnconditionalBranchOp {
718 UnconditionalBranchFixed = 0x14000000,
719 UnconditionalBranchFMask = 0x7C000000,
720 UnconditionalBranchMask = 0xFC000000,
721 B = UnconditionalBranchFixed | 0x00000000,
722 BL = UnconditionalBranchFixed | 0x80000000
723 };
724
725 // Unconditional branch to register.
726 enum UnconditionalBranchToRegisterOp {
727 UnconditionalBranchToRegisterFixed = 0xD6000000,
728 UnconditionalBranchToRegisterFMask = 0xFE000000,
729 UnconditionalBranchToRegisterMask = 0xFFFFFC00,
730 BR = UnconditionalBranchToRegisterFixed | 0x001F0000,
731 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
732 RET = UnconditionalBranchToRegisterFixed | 0x005F0000,
733
734 BRAAZ = UnconditionalBranchToRegisterFixed | 0x001F0800,
735 BRABZ = UnconditionalBranchToRegisterFixed | 0x001F0C00,
736 BLRAAZ = UnconditionalBranchToRegisterFixed | 0x003F0800,
737 BLRABZ = UnconditionalBranchToRegisterFixed | 0x003F0C00,
738 RETAA = UnconditionalBranchToRegisterFixed | 0x005F0800,
739 RETAB = UnconditionalBranchToRegisterFixed | 0x005F0C00,
740 BRAA = UnconditionalBranchToRegisterFixed | 0x011F0800,
741 BRAB = UnconditionalBranchToRegisterFixed | 0x011F0C00,
742 BLRAA = UnconditionalBranchToRegisterFixed | 0x013F0800,
743 BLRAB = UnconditionalBranchToRegisterFixed | 0x013F0C00
744 };
745
746 // Compare and branch.
747 enum CompareBranchOp {
748 CompareBranchFixed = 0x34000000,
749 CompareBranchFMask = 0x7E000000,
750 CompareBranchMask = 0xFF000000,
751 CBZ_w = CompareBranchFixed | 0x00000000,
752 CBZ_x = CompareBranchFixed | 0x80000000,
753 CBZ = CBZ_w,
754 CBNZ_w = CompareBranchFixed | 0x01000000,
755 CBNZ_x = CompareBranchFixed | 0x81000000,
756 CBNZ = CBNZ_w
757 };
758
759 // Test and branch.
760 enum TestBranchOp {
761 TestBranchFixed = 0x36000000,
762 TestBranchFMask = 0x7E000000,
763 TestBranchMask = 0x7F000000,
764 TBZ = TestBranchFixed | 0x00000000,
765 TBNZ = TestBranchFixed | 0x01000000
766 };
767
768 // Conditional branch.
769 enum ConditionalBranchOp {
770 ConditionalBranchFixed = 0x54000000,
771 ConditionalBranchFMask = 0xFE000000,
772 ConditionalBranchMask = 0xFF000010,
773 B_cond = ConditionalBranchFixed | 0x00000000
774 };
775
776 // System.
777 // System instruction encoding is complicated because some instructions use op
778 // and CR fields to encode parameters. To handle this cleanly, the system
779 // instructions are split into more than one enum.
780
781 enum SystemOp {
782 SystemFixed = 0xD5000000,
783 SystemFMask = 0xFFC00000
784 };
785
786 enum SystemSysRegOp {
787 SystemSysRegFixed = 0xD5100000,
788 SystemSysRegFMask = 0xFFD00000,
789 SystemSysRegMask = 0xFFF00000,
790 MRS = SystemSysRegFixed | 0x00200000,
791 MSR = SystemSysRegFixed | 0x00000000
792 };
793
794 enum SystemPStateOp {
795 SystemPStateFixed = 0xD5004000,
796 SystemPStateFMask = 0xFFF8F000,
797 SystemPStateMask = 0xFFFFF0FF,
798 CFINV = SystemPStateFixed | 0x0000001F,
799 XAFLAG = SystemPStateFixed | 0x0000003F,
800 AXFLAG = SystemPStateFixed | 0x0000005F
801 };
802
803 enum SystemHintOp {
804 SystemHintFixed = 0xD503201F,
805 SystemHintFMask = 0xFFFFF01F,
806 SystemHintMask = 0xFFFFF01F,
807 HINT = SystemHintFixed | 0x00000000
808 };
809
810 enum SystemSysOp {
811 SystemSysFixed = 0xD5080000,
812 SystemSysFMask = 0xFFF80000,
813 SystemSysMask = 0xFFF80000,
814 SYS = SystemSysFixed | 0x00000000
815 };
816
817 // Exception.
818 enum ExceptionOp {
819 ExceptionFixed = 0xD4000000,
820 ExceptionFMask = 0xFF000000,
821 ExceptionMask = 0xFFE0001F,
822 HLT = ExceptionFixed | 0x00400000,
823 BRK = ExceptionFixed | 0x00200000,
824 SVC = ExceptionFixed | 0x00000001,
825 HVC = ExceptionFixed | 0x00000002,
826 SMC = ExceptionFixed | 0x00000003,
827 DCPS1 = ExceptionFixed | 0x00A00001,
828 DCPS2 = ExceptionFixed | 0x00A00002,
829 DCPS3 = ExceptionFixed | 0x00A00003
830 };
831
832 enum MemBarrierOp {
833 MemBarrierFixed = 0xD503309F,
834 MemBarrierFMask = 0xFFFFF09F,
835 MemBarrierMask = 0xFFFFF0FF,
836 DSB = MemBarrierFixed | 0x00000000,
837 DMB = MemBarrierFixed | 0x00000020,
838 ISB = MemBarrierFixed | 0x00000040
839 };
840
841 enum SystemExclusiveMonitorOp {
842 SystemExclusiveMonitorFixed = 0xD503305F,
843 SystemExclusiveMonitorFMask = 0xFFFFF0FF,
844 SystemExclusiveMonitorMask = 0xFFFFF0FF,
845 CLREX = SystemExclusiveMonitorFixed
846 };
847
848 enum SystemPAuthOp {
849 SystemPAuthFixed = 0xD503211F,
850 SystemPAuthFMask = 0xFFFFFD1F,
851 SystemPAuthMask = 0xFFFFFFFF,
852 PACIA1716 = SystemPAuthFixed | 0x00000100,
853 PACIB1716 = SystemPAuthFixed | 0x00000140,
854 AUTIA1716 = SystemPAuthFixed | 0x00000180,
855 AUTIB1716 = SystemPAuthFixed | 0x000001C0,
856 PACIAZ = SystemPAuthFixed | 0x00000300,
857 PACIASP = SystemPAuthFixed | 0x00000320,
858 PACIBZ = SystemPAuthFixed | 0x00000340,
859 PACIBSP = SystemPAuthFixed | 0x00000360,
860 AUTIAZ = SystemPAuthFixed | 0x00000380,
861 AUTIASP = SystemPAuthFixed | 0x000003A0,
862 AUTIBZ = SystemPAuthFixed | 0x000003C0,
863 AUTIBSP = SystemPAuthFixed | 0x000003E0,
864
865 // XPACLRI has the same fixed mask as System Hints and needs to be handled
866 // differently.
867 XPACLRI = 0xD50320FF
868 };
869
870 // Any load or store.
871 enum LoadStoreAnyOp {
872 LoadStoreAnyFMask = 0x0a000000,
873 LoadStoreAnyFixed = 0x08000000
874 };
875
876 // Any load pair or store pair.
877 enum LoadStorePairAnyOp {
878 LoadStorePairAnyFMask = 0x3a000000,
879 LoadStorePairAnyFixed = 0x28000000
880 };
881
882 #define LOAD_STORE_PAIR_OP_LIST(V) \
883 V(STP, w, 0x00000000), \
884 V(LDP, w, 0x00400000), \
885 V(LDPSW, x, 0x40400000), \
886 V(STP, x, 0x80000000), \
887 V(LDP, x, 0x80400000), \
888 V(STP, s, 0x04000000), \
889 V(LDP, s, 0x04400000), \
890 V(STP, d, 0x44000000), \
891 V(LDP, d, 0x44400000), \
892 V(STP, q, 0x84000000), \
893 V(LDP, q, 0x84400000)
894
895 // Load/store pair (post, pre and offset.)
896 enum LoadStorePairOp {
897 LoadStorePairMask = 0xC4400000,
898 LoadStorePairLBit = 1 << 22,
899 #define LOAD_STORE_PAIR(A, B, C) \
900 A##_##B = C
901 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR)
902 #undef LOAD_STORE_PAIR
903 };
904
905 enum LoadStorePairPostIndexOp {
906 LoadStorePairPostIndexFixed = 0x28800000,
907 LoadStorePairPostIndexFMask = 0x3B800000,
908 LoadStorePairPostIndexMask = 0xFFC00000,
909 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \
910 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
911 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX)
912 #undef LOAD_STORE_PAIR_POST_INDEX
913 };
914
915 enum LoadStorePairPreIndexOp {
916 LoadStorePairPreIndexFixed = 0x29800000,
917 LoadStorePairPreIndexFMask = 0x3B800000,
918 LoadStorePairPreIndexMask = 0xFFC00000,
919 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \
920 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
921 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX)
922 #undef LOAD_STORE_PAIR_PRE_INDEX
923 };
924
925 enum LoadStorePairOffsetOp {
926 LoadStorePairOffsetFixed = 0x29000000,
927 LoadStorePairOffsetFMask = 0x3B800000,
928 LoadStorePairOffsetMask = 0xFFC00000,
929 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \
930 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
931 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET)
932 #undef LOAD_STORE_PAIR_OFFSET
933 };
934
935 enum LoadStorePairNonTemporalOp {
936 LoadStorePairNonTemporalFixed = 0x28000000,
937 LoadStorePairNonTemporalFMask = 0x3B800000,
938 LoadStorePairNonTemporalMask = 0xFFC00000,
939 LoadStorePairNonTemporalLBit = 1 << 22,
940 STNP_w = LoadStorePairNonTemporalFixed | STP_w,
941 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w,
942 STNP_x = LoadStorePairNonTemporalFixed | STP_x,
943 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x,
944 STNP_s = LoadStorePairNonTemporalFixed | STP_s,
945 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s,
946 STNP_d = LoadStorePairNonTemporalFixed | STP_d,
947 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d,
948 STNP_q = LoadStorePairNonTemporalFixed | STP_q,
949 LDNP_q = LoadStorePairNonTemporalFixed | LDP_q
950 };
951
952 // Load with pointer authentication.
953 enum LoadStorePACOp {
954 LoadStorePACFixed = 0xF8200400,
955 LoadStorePACFMask = 0xFF200400,
956 LoadStorePACMask = 0xFFA00C00,
957 LoadStorePACPreBit = 0x00000800,
958 LDRAA = LoadStorePACFixed | 0x00000000,
959 LDRAA_pre = LoadStorePACPreBit | LDRAA,
960 LDRAB = LoadStorePACFixed | 0x00800000,
961 LDRAB_pre = LoadStorePACPreBit | LDRAB
962 };
963
964 // Load literal.
965 enum LoadLiteralOp {
966 LoadLiteralFixed = 0x18000000,
967 LoadLiteralFMask = 0x3B000000,
968 LoadLiteralMask = 0xFF000000,
969 LDR_w_lit = LoadLiteralFixed | 0x00000000,
970 LDR_x_lit = LoadLiteralFixed | 0x40000000,
971 LDRSW_x_lit = LoadLiteralFixed | 0x80000000,
972 PRFM_lit = LoadLiteralFixed | 0xC0000000,
973 LDR_s_lit = LoadLiteralFixed | 0x04000000,
974 LDR_d_lit = LoadLiteralFixed | 0x44000000,
975 LDR_q_lit = LoadLiteralFixed | 0x84000000
976 };
977
978 #define LOAD_STORE_OP_LIST(V) \
979 V(ST, RB, w, 0x00000000), \
980 V(ST, RH, w, 0x40000000), \
981 V(ST, R, w, 0x80000000), \
982 V(ST, R, x, 0xC0000000), \
983 V(LD, RB, w, 0x00400000), \
984 V(LD, RH, w, 0x40400000), \
985 V(LD, R, w, 0x80400000), \
986 V(LD, R, x, 0xC0400000), \
987 V(LD, RSB, x, 0x00800000), \
988 V(LD, RSH, x, 0x40800000), \
989 V(LD, RSW, x, 0x80800000), \
990 V(LD, RSB, w, 0x00C00000), \
991 V(LD, RSH, w, 0x40C00000), \
992 V(ST, R, b, 0x04000000), \
993 V(ST, R, h, 0x44000000), \
994 V(ST, R, s, 0x84000000), \
995 V(ST, R, d, 0xC4000000), \
996 V(ST, R, q, 0x04800000), \
997 V(LD, R, b, 0x04400000), \
998 V(LD, R, h, 0x44400000), \
999 V(LD, R, s, 0x84400000), \
1000 V(LD, R, d, 0xC4400000), \
1001 V(LD, R, q, 0x04C00000)
1002
1003 // Load/store (post, pre, offset and unsigned.)
1004 enum LoadStoreOp {
1005 LoadStoreMask = 0xC4C00000,
1006 LoadStoreVMask = 0x04000000,
1007 #define LOAD_STORE(A, B, C, D) \
1008 A##B##_##C = D
1009 LOAD_STORE_OP_LIST(LOAD_STORE),
1010 #undef LOAD_STORE
1011 PRFM = 0xC0800000
1012 };
1013
1014 // Load/store unscaled offset.
1015 enum LoadStoreUnscaledOffsetOp {
1016 LoadStoreUnscaledOffsetFixed = 0x38000000,
1017 LoadStoreUnscaledOffsetFMask = 0x3B200C00,
1018 LoadStoreUnscaledOffsetMask = 0xFFE00C00,
1019 PRFUM = LoadStoreUnscaledOffsetFixed | PRFM,
1020 #define LOAD_STORE_UNSCALED(A, B, C, D) \
1021 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
1022 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED)
1023 #undef LOAD_STORE_UNSCALED
1024 };
1025
1026 // Load/store post index.
1027 enum LoadStorePostIndex {
1028 LoadStorePostIndexFixed = 0x38000400,
1029 LoadStorePostIndexFMask = 0x3B200C00,
1030 LoadStorePostIndexMask = 0xFFE00C00,
1031 #define LOAD_STORE_POST_INDEX(A, B, C, D) \
1032 A##B##_##C##_post = LoadStorePostIndexFixed | D
1033 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX)
1034 #undef LOAD_STORE_POST_INDEX
1035 };
1036
1037 // Load/store pre index.
1038 enum LoadStorePreIndex {
1039 LoadStorePreIndexFixed = 0x38000C00,
1040 LoadStorePreIndexFMask = 0x3B200C00,
1041 LoadStorePreIndexMask = 0xFFE00C00,
1042 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \
1043 A##B##_##C##_pre = LoadStorePreIndexFixed | D
1044 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX)
1045 #undef LOAD_STORE_PRE_INDEX
1046 };
1047
1048 // Load/store unsigned offset.
1049 enum LoadStoreUnsignedOffset {
1050 LoadStoreUnsignedOffsetFixed = 0x39000000,
1051 LoadStoreUnsignedOffsetFMask = 0x3B000000,
1052 LoadStoreUnsignedOffsetMask = 0xFFC00000,
1053 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM,
1054 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \
1055 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
1056 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET)
1057 #undef LOAD_STORE_UNSIGNED_OFFSET
1058 };
1059
1060 // Load/store register offset.
1061 enum LoadStoreRegisterOffset {
1062 LoadStoreRegisterOffsetFixed = 0x38200800,
1063 LoadStoreRegisterOffsetFMask = 0x3B200C00,
1064 LoadStoreRegisterOffsetMask = 0xFFE00C00,
1065 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM,
1066 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
1067 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
1068 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET)
1069 #undef LOAD_STORE_REGISTER_OFFSET
1070 };
1071
1072 enum LoadStoreExclusive {
1073 LoadStoreExclusiveFixed = 0x08000000,
1074 LoadStoreExclusiveFMask = 0x3F000000,
1075 LoadStoreExclusiveMask = 0xFFE08000,
1076 STXRB_w = LoadStoreExclusiveFixed | 0x00000000,
1077 STXRH_w = LoadStoreExclusiveFixed | 0x40000000,
1078 STXR_w = LoadStoreExclusiveFixed | 0x80000000,
1079 STXR_x = LoadStoreExclusiveFixed | 0xC0000000,
1080 LDXRB_w = LoadStoreExclusiveFixed | 0x00400000,
1081 LDXRH_w = LoadStoreExclusiveFixed | 0x40400000,
1082 LDXR_w = LoadStoreExclusiveFixed | 0x80400000,
1083 LDXR_x = LoadStoreExclusiveFixed | 0xC0400000,
1084 STXP_w = LoadStoreExclusiveFixed | 0x80200000,
1085 STXP_x = LoadStoreExclusiveFixed | 0xC0200000,
1086 LDXP_w = LoadStoreExclusiveFixed | 0x80600000,
1087 LDXP_x = LoadStoreExclusiveFixed | 0xC0600000,
1088 STLXRB_w = LoadStoreExclusiveFixed | 0x00008000,
1089 STLXRH_w = LoadStoreExclusiveFixed | 0x40008000,
1090 STLXR_w = LoadStoreExclusiveFixed | 0x80008000,
1091 STLXR_x = LoadStoreExclusiveFixed | 0xC0008000,
1092 LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000,
1093 LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000,
1094 LDAXR_w = LoadStoreExclusiveFixed | 0x80408000,
1095 LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000,
1096 STLXP_w = LoadStoreExclusiveFixed | 0x80208000,
1097 STLXP_x = LoadStoreExclusiveFixed | 0xC0208000,
1098 LDAXP_w = LoadStoreExclusiveFixed | 0x80608000,
1099 LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000,
1100 STLRB_w = LoadStoreExclusiveFixed | 0x00808000,
1101 STLRH_w = LoadStoreExclusiveFixed | 0x40808000,
1102 STLR_w = LoadStoreExclusiveFixed | 0x80808000,
1103 STLR_x = LoadStoreExclusiveFixed | 0xC0808000,
1104 LDARB_w = LoadStoreExclusiveFixed | 0x00C08000,
1105 LDARH_w = LoadStoreExclusiveFixed | 0x40C08000,
1106 LDAR_w = LoadStoreExclusiveFixed | 0x80C08000,
1107 LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000,
1108
1109 // v8.1 Load/store LORegion ops
1110 STLLRB = LoadStoreExclusiveFixed | 0x00800000,
1111 LDLARB = LoadStoreExclusiveFixed | 0x00C00000,
1112 STLLRH = LoadStoreExclusiveFixed | 0x40800000,
1113 LDLARH = LoadStoreExclusiveFixed | 0x40C00000,
1114 STLLR_w = LoadStoreExclusiveFixed | 0x80800000,
1115 LDLAR_w = LoadStoreExclusiveFixed | 0x80C00000,
1116 STLLR_x = LoadStoreExclusiveFixed | 0xC0800000,
1117 LDLAR_x = LoadStoreExclusiveFixed | 0xC0C00000,
1118
1119 // v8.1 Load/store exclusive ops
1120 LSEBit_l = 0x00400000,
1121 LSEBit_o0 = 0x00008000,
1122 LSEBit_sz = 0x40000000,
1123 CASFixed = LoadStoreExclusiveFixed | 0x80A00000,
1124 CASBFixed = LoadStoreExclusiveFixed | 0x00A00000,
1125 CASHFixed = LoadStoreExclusiveFixed | 0x40A00000,
1126 CASPFixed = LoadStoreExclusiveFixed | 0x00200000,
1127 CAS_w = CASFixed,
1128 CAS_x = CASFixed | LSEBit_sz,
1129 CASA_w = CASFixed | LSEBit_l,
1130 CASA_x = CASFixed | LSEBit_l | LSEBit_sz,
1131 CASL_w = CASFixed | LSEBit_o0,
1132 CASL_x = CASFixed | LSEBit_o0 | LSEBit_sz,
1133 CASAL_w = CASFixed | LSEBit_l | LSEBit_o0,
1134 CASAL_x = CASFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz,
1135 CASB = CASBFixed,
1136 CASAB = CASBFixed | LSEBit_l,
1137 CASLB = CASBFixed | LSEBit_o0,
1138 CASALB = CASBFixed | LSEBit_l | LSEBit_o0,
1139 CASH = CASHFixed,
1140 CASAH = CASHFixed | LSEBit_l,
1141 CASLH = CASHFixed | LSEBit_o0,
1142 CASALH = CASHFixed | LSEBit_l | LSEBit_o0,
1143 CASP_w = CASPFixed,
1144 CASP_x = CASPFixed | LSEBit_sz,
1145 CASPA_w = CASPFixed | LSEBit_l,
1146 CASPA_x = CASPFixed | LSEBit_l | LSEBit_sz,
1147 CASPL_w = CASPFixed | LSEBit_o0,
1148 CASPL_x = CASPFixed | LSEBit_o0 | LSEBit_sz,
1149 CASPAL_w = CASPFixed | LSEBit_l | LSEBit_o0,
1150 CASPAL_x = CASPFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz
1151 };
1152
1153 // Load/store RCpc unscaled offset.
1154 enum LoadStoreRCpcUnscaledOffsetOp {
1155 LoadStoreRCpcUnscaledOffsetFixed = 0x19000000,
1156 LoadStoreRCpcUnscaledOffsetFMask = 0x3F200C00,
1157 LoadStoreRCpcUnscaledOffsetMask = 0xFFE00C00,
1158 STLURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00000000,
1159 LDAPURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00400000,
1160 LDAPURSB_x = LoadStoreRCpcUnscaledOffsetFixed | 0x00800000,
1161 LDAPURSB_w = LoadStoreRCpcUnscaledOffsetFixed | 0x00C00000,
1162 STLURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40000000,
1163 LDAPURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40400000,
1164 LDAPURSH_x = LoadStoreRCpcUnscaledOffsetFixed | 0x40800000,
1165 LDAPURSH_w = LoadStoreRCpcUnscaledOffsetFixed | 0x40C00000,
1166 STLUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80000000,
1167 LDAPUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80400000,
1168 LDAPURSW = LoadStoreRCpcUnscaledOffsetFixed | 0x80800000,
1169 STLUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0000000,
1170 LDAPUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0400000
1171 };
1172
1173 #define ATOMIC_MEMORY_SIMPLE_OPC_LIST(V) \
1174 V(LDADD, 0x00000000), \
1175 V(LDCLR, 0x00001000), \
1176 V(LDEOR, 0x00002000), \
1177 V(LDSET, 0x00003000), \
1178 V(LDSMAX, 0x00004000), \
1179 V(LDSMIN, 0x00005000), \
1180 V(LDUMAX, 0x00006000), \
1181 V(LDUMIN, 0x00007000)
1182
1183 // Atomic memory.
1184 enum AtomicMemoryOp {
1185 AtomicMemoryFixed = 0x38200000,
1186 AtomicMemoryFMask = 0x3B200C00,
1187 AtomicMemoryMask = 0xFFE0FC00,
1188 SWPB = AtomicMemoryFixed | 0x00008000,
1189 SWPAB = AtomicMemoryFixed | 0x00808000,
1190 SWPLB = AtomicMemoryFixed | 0x00408000,
1191 SWPALB = AtomicMemoryFixed | 0x00C08000,
1192 SWPH = AtomicMemoryFixed | 0x40008000,
1193 SWPAH = AtomicMemoryFixed | 0x40808000,
1194 SWPLH = AtomicMemoryFixed | 0x40408000,
1195 SWPALH = AtomicMemoryFixed | 0x40C08000,
1196 SWP_w = AtomicMemoryFixed | 0x80008000,
1197 SWPA_w = AtomicMemoryFixed | 0x80808000,
1198 SWPL_w = AtomicMemoryFixed | 0x80408000,
1199 SWPAL_w = AtomicMemoryFixed | 0x80C08000,
1200 SWP_x = AtomicMemoryFixed | 0xC0008000,
1201 SWPA_x = AtomicMemoryFixed | 0xC0808000,
1202 SWPL_x = AtomicMemoryFixed | 0xC0408000,
1203 SWPAL_x = AtomicMemoryFixed | 0xC0C08000,
1204 LDAPRB = AtomicMemoryFixed | 0x0080C000,
1205 LDAPRH = AtomicMemoryFixed | 0x4080C000,
1206 LDAPR_w = AtomicMemoryFixed | 0x8080C000,
1207 LDAPR_x = AtomicMemoryFixed | 0xC080C000,
1208
1209 AtomicMemorySimpleFMask = 0x3B208C00,
1210 AtomicMemorySimpleOpMask = 0x00007000,
1211 #define ATOMIC_MEMORY_SIMPLE(N, OP) \
1212 N##Op = OP, \
1213 N##B = AtomicMemoryFixed | OP, \
1214 N##AB = AtomicMemoryFixed | OP | 0x00800000, \
1215 N##LB = AtomicMemoryFixed | OP | 0x00400000, \
1216 N##ALB = AtomicMemoryFixed | OP | 0x00C00000, \
1217 N##H = AtomicMemoryFixed | OP | 0x40000000, \
1218 N##AH = AtomicMemoryFixed | OP | 0x40800000, \
1219 N##LH = AtomicMemoryFixed | OP | 0x40400000, \
1220 N##ALH = AtomicMemoryFixed | OP | 0x40C00000, \
1221 N##_w = AtomicMemoryFixed | OP | 0x80000000, \
1222 N##A_w = AtomicMemoryFixed | OP | 0x80800000, \
1223 N##L_w = AtomicMemoryFixed | OP | 0x80400000, \
1224 N##AL_w = AtomicMemoryFixed | OP | 0x80C00000, \
1225 N##_x = AtomicMemoryFixed | OP | 0xC0000000, \
1226 N##A_x = AtomicMemoryFixed | OP | 0xC0800000, \
1227 N##L_x = AtomicMemoryFixed | OP | 0xC0400000, \
1228 N##AL_x = AtomicMemoryFixed | OP | 0xC0C00000
1229
1230 ATOMIC_MEMORY_SIMPLE_OPC_LIST(ATOMIC_MEMORY_SIMPLE)
1231 #undef ATOMIC_MEMORY_SIMPLE
1232 };
1233
1234 // Conditional compare.
1235 enum ConditionalCompareOp {
1236 ConditionalCompareMask = 0x60000000,
1237 CCMN = 0x20000000,
1238 CCMP = 0x60000000
1239 };
1240
1241 // Conditional compare register.
1242 enum ConditionalCompareRegisterOp {
1243 ConditionalCompareRegisterFixed = 0x1A400000,
1244 ConditionalCompareRegisterFMask = 0x1FE00800,
1245 ConditionalCompareRegisterMask = 0xFFE00C10,
1246 CCMN_w = ConditionalCompareRegisterFixed | CCMN,
1247 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN,
1248 CCMP_w = ConditionalCompareRegisterFixed | CCMP,
1249 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP
1250 };
1251
1252 // Conditional compare immediate.
1253 enum ConditionalCompareImmediateOp {
1254 ConditionalCompareImmediateFixed = 0x1A400800,
1255 ConditionalCompareImmediateFMask = 0x1FE00800,
1256 ConditionalCompareImmediateMask = 0xFFE00C10,
1257 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN,
1258 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN,
1259 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP,
1260 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP
1261 };
1262
1263 // Conditional select.
1264 enum ConditionalSelectOp {
1265 ConditionalSelectFixed = 0x1A800000,
1266 ConditionalSelectFMask = 0x1FE00000,
1267 ConditionalSelectMask = 0xFFE00C00,
1268 CSEL_w = ConditionalSelectFixed | 0x00000000,
1269 CSEL_x = ConditionalSelectFixed | 0x80000000,
1270 CSEL = CSEL_w,
1271 CSINC_w = ConditionalSelectFixed | 0x00000400,
1272 CSINC_x = ConditionalSelectFixed | 0x80000400,
1273 CSINC = CSINC_w,
1274 CSINV_w = ConditionalSelectFixed | 0x40000000,
1275 CSINV_x = ConditionalSelectFixed | 0xC0000000,
1276 CSINV = CSINV_w,
1277 CSNEG_w = ConditionalSelectFixed | 0x40000400,
1278 CSNEG_x = ConditionalSelectFixed | 0xC0000400,
1279 CSNEG = CSNEG_w
1280 };
1281
1282 // Data processing 1 source.
1283 enum DataProcessing1SourceOp {
1284 DataProcessing1SourceFixed = 0x5AC00000,
1285 DataProcessing1SourceFMask = 0x5FE00000,
1286 DataProcessing1SourceMask = 0xFFFFFC00,
1287 RBIT = DataProcessing1SourceFixed | 0x00000000,
1288 RBIT_w = RBIT,
1289 RBIT_x = RBIT | SixtyFourBits,
1290 REV16 = DataProcessing1SourceFixed | 0x00000400,
1291 REV16_w = REV16,
1292 REV16_x = REV16 | SixtyFourBits,
1293 REV = DataProcessing1SourceFixed | 0x00000800,
1294 REV_w = REV,
1295 REV32_x = REV | SixtyFourBits,
1296 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00,
1297 CLZ = DataProcessing1SourceFixed | 0x00001000,
1298 CLZ_w = CLZ,
1299 CLZ_x = CLZ | SixtyFourBits,
1300 CLS = DataProcessing1SourceFixed | 0x00001400,
1301 CLS_w = CLS,
1302 CLS_x = CLS | SixtyFourBits,
1303
1304 // Pointer authentication instructions in Armv8.3.
1305 PACIA = DataProcessing1SourceFixed | 0x80010000,
1306 PACIB = DataProcessing1SourceFixed | 0x80010400,
1307 PACDA = DataProcessing1SourceFixed | 0x80010800,
1308 PACDB = DataProcessing1SourceFixed | 0x80010C00,
1309 AUTIA = DataProcessing1SourceFixed | 0x80011000,
1310 AUTIB = DataProcessing1SourceFixed | 0x80011400,
1311 AUTDA = DataProcessing1SourceFixed | 0x80011800,
1312 AUTDB = DataProcessing1SourceFixed | 0x80011C00,
1313 PACIZA = DataProcessing1SourceFixed | 0x80012000,
1314 PACIZB = DataProcessing1SourceFixed | 0x80012400,
1315 PACDZA = DataProcessing1SourceFixed | 0x80012800,
1316 PACDZB = DataProcessing1SourceFixed | 0x80012C00,
1317 AUTIZA = DataProcessing1SourceFixed | 0x80013000,
1318 AUTIZB = DataProcessing1SourceFixed | 0x80013400,
1319 AUTDZA = DataProcessing1SourceFixed | 0x80013800,
1320 AUTDZB = DataProcessing1SourceFixed | 0x80013C00,
1321 XPACI = DataProcessing1SourceFixed | 0x80014000,
1322 XPACD = DataProcessing1SourceFixed | 0x80014400
1323 };
1324
1325 // Data processing 2 source.
1326 enum DataProcessing2SourceOp {
1327 DataProcessing2SourceFixed = 0x1AC00000,
1328 DataProcessing2SourceFMask = 0x5FE00000,
1329 DataProcessing2SourceMask = 0xFFE0FC00,
1330 UDIV_w = DataProcessing2SourceFixed | 0x00000800,
1331 UDIV_x = DataProcessing2SourceFixed | 0x80000800,
1332 UDIV = UDIV_w,
1333 SDIV_w = DataProcessing2SourceFixed | 0x00000C00,
1334 SDIV_x = DataProcessing2SourceFixed | 0x80000C00,
1335 SDIV = SDIV_w,
1336 LSLV_w = DataProcessing2SourceFixed | 0x00002000,
1337 LSLV_x = DataProcessing2SourceFixed | 0x80002000,
1338 LSLV = LSLV_w,
1339 LSRV_w = DataProcessing2SourceFixed | 0x00002400,
1340 LSRV_x = DataProcessing2SourceFixed | 0x80002400,
1341 LSRV = LSRV_w,
1342 ASRV_w = DataProcessing2SourceFixed | 0x00002800,
1343 ASRV_x = DataProcessing2SourceFixed | 0x80002800,
1344 ASRV = ASRV_w,
1345 RORV_w = DataProcessing2SourceFixed | 0x00002C00,
1346 RORV_x = DataProcessing2SourceFixed | 0x80002C00,
1347 RORV = RORV_w,
1348 PACGA = DataProcessing2SourceFixed | SixtyFourBits | 0x00003000,
1349 CRC32B = DataProcessing2SourceFixed | 0x00004000,
1350 CRC32H = DataProcessing2SourceFixed | 0x00004400,
1351 CRC32W = DataProcessing2SourceFixed | 0x00004800,
1352 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00,
1353 CRC32CB = DataProcessing2SourceFixed | 0x00005000,
1354 CRC32CH = DataProcessing2SourceFixed | 0x00005400,
1355 CRC32CW = DataProcessing2SourceFixed | 0x00005800,
1356 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00
1357 };
1358
1359 // Data processing 3 source.
1360 enum DataProcessing3SourceOp {
1361 DataProcessing3SourceFixed = 0x1B000000,
1362 DataProcessing3SourceFMask = 0x1F000000,
1363 DataProcessing3SourceMask = 0xFFE08000,
1364 MADD_w = DataProcessing3SourceFixed | 0x00000000,
1365 MADD_x = DataProcessing3SourceFixed | 0x80000000,
1366 MADD = MADD_w,
1367 MSUB_w = DataProcessing3SourceFixed | 0x00008000,
1368 MSUB_x = DataProcessing3SourceFixed | 0x80008000,
1369 MSUB = MSUB_w,
1370 SMADDL_x = DataProcessing3SourceFixed | 0x80200000,
1371 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000,
1372 SMULH_x = DataProcessing3SourceFixed | 0x80400000,
1373 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000,
1374 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000,
1375 UMULH_x = DataProcessing3SourceFixed | 0x80C00000
1376 };
1377
1378 // Floating point compare.
1379 enum FPCompareOp {
1380 FPCompareFixed = 0x1E202000,
1381 FPCompareFMask = 0x5F203C00,
1382 FPCompareMask = 0xFFE0FC1F,
1383 FCMP_h = FPCompareFixed | FP16 | 0x00000000,
1384 FCMP_s = FPCompareFixed | 0x00000000,
1385 FCMP_d = FPCompareFixed | FP64 | 0x00000000,
1386 FCMP = FCMP_s,
1387 FCMP_h_zero = FPCompareFixed | FP16 | 0x00000008,
1388 FCMP_s_zero = FPCompareFixed | 0x00000008,
1389 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
1390 FCMP_zero = FCMP_s_zero,
1391 FCMPE_h = FPCompareFixed | FP16 | 0x00000010,
1392 FCMPE_s = FPCompareFixed | 0x00000010,
1393 FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
1394 FCMPE = FCMPE_s,
1395 FCMPE_h_zero = FPCompareFixed | FP16 | 0x00000018,
1396 FCMPE_s_zero = FPCompareFixed | 0x00000018,
1397 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018,
1398 FCMPE_zero = FCMPE_s_zero
1399 };
1400
1401 // Floating point conditional compare.
1402 enum FPConditionalCompareOp {
1403 FPConditionalCompareFixed = 0x1E200400,
1404 FPConditionalCompareFMask = 0x5F200C00,
1405 FPConditionalCompareMask = 0xFFE00C10,
1406 FCCMP_h = FPConditionalCompareFixed | FP16 | 0x00000000,
1407 FCCMP_s = FPConditionalCompareFixed | 0x00000000,
1408 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1409 FCCMP = FCCMP_s,
1410 FCCMPE_h = FPConditionalCompareFixed | FP16 | 0x00000010,
1411 FCCMPE_s = FPConditionalCompareFixed | 0x00000010,
1412 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1413 FCCMPE = FCCMPE_s
1414 };
1415
1416 // Floating point conditional select.
1417 enum FPConditionalSelectOp {
1418 FPConditionalSelectFixed = 0x1E200C00,
1419 FPConditionalSelectFMask = 0x5F200C00,
1420 FPConditionalSelectMask = 0xFFE00C00,
1421 FCSEL_h = FPConditionalSelectFixed | FP16 | 0x00000000,
1422 FCSEL_s = FPConditionalSelectFixed | 0x00000000,
1423 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1424 FCSEL = FCSEL_s
1425 };
1426
1427 // Floating point immediate.
1428 enum FPImmediateOp {
1429 FPImmediateFixed = 0x1E201000,
1430 FPImmediateFMask = 0x5F201C00,
1431 FPImmediateMask = 0xFFE01C00,
1432 FMOV_h_imm = FPImmediateFixed | FP16 | 0x00000000,
1433 FMOV_s_imm = FPImmediateFixed | 0x00000000,
1434 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
1435 };
1436
1437 // Floating point data processing 1 source.
1438 enum FPDataProcessing1SourceOp {
1439 FPDataProcessing1SourceFixed = 0x1E204000,
1440 FPDataProcessing1SourceFMask = 0x5F207C00,
1441 FPDataProcessing1SourceMask = 0xFFFFFC00,
1442 FMOV_h = FPDataProcessing1SourceFixed | FP16 | 0x00000000,
1443 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000,
1444 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
1445 FMOV = FMOV_s,
1446 FABS_h = FPDataProcessing1SourceFixed | FP16 | 0x00008000,
1447 FABS_s = FPDataProcessing1SourceFixed | 0x00008000,
1448 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
1449 FABS = FABS_s,
1450 FNEG_h = FPDataProcessing1SourceFixed | FP16 | 0x00010000,
1451 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000,
1452 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000,
1453 FNEG = FNEG_s,
1454 FSQRT_h = FPDataProcessing1SourceFixed | FP16 | 0x00018000,
1455 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000,
1456 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000,
1457 FSQRT = FSQRT_s,
1458 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000,
1459 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000,
1460 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000,
1461 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000,
1462 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000,
1463 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000,
1464 FRINT32X_s = FPDataProcessing1SourceFixed | 0x00088000,
1465 FRINT32X_d = FPDataProcessing1SourceFixed | FP64 | 0x00088000,
1466 FRINT32X = FRINT32X_s,
1467 FRINT32Z_s = FPDataProcessing1SourceFixed | 0x00080000,
1468 FRINT32Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00080000,
1469 FRINT32Z = FRINT32Z_s,
1470 FRINT64X_s = FPDataProcessing1SourceFixed | 0x00098000,
1471 FRINT64X_d = FPDataProcessing1SourceFixed | FP64 | 0x00098000,
1472 FRINT64X = FRINT64X_s,
1473 FRINT64Z_s = FPDataProcessing1SourceFixed | 0x00090000,
1474 FRINT64Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00090000,
1475 FRINT64Z = FRINT64Z_s,
1476 FRINTN_h = FPDataProcessing1SourceFixed | FP16 | 0x00040000,
1477 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000,
1478 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000,
1479 FRINTN = FRINTN_s,
1480 FRINTP_h = FPDataProcessing1SourceFixed | FP16 | 0x00048000,
1481 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
1482 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
1483 FRINTP = FRINTP_s,
1484 FRINTM_h = FPDataProcessing1SourceFixed | FP16 | 0x00050000,
1485 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
1486 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
1487 FRINTM = FRINTM_s,
1488 FRINTZ_h = FPDataProcessing1SourceFixed | FP16 | 0x00058000,
1489 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
1490 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
1491 FRINTZ = FRINTZ_s,
1492 FRINTA_h = FPDataProcessing1SourceFixed | FP16 | 0x00060000,
1493 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
1494 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
1495 FRINTA = FRINTA_s,
1496 FRINTX_h = FPDataProcessing1SourceFixed | FP16 | 0x00070000,
1497 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
1498 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
1499 FRINTX = FRINTX_s,
1500 FRINTI_h = FPDataProcessing1SourceFixed | FP16 | 0x00078000,
1501 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
1502 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
1503 FRINTI = FRINTI_s
1504 };
1505
1506 // Floating point data processing 2 source.
1507 enum FPDataProcessing2SourceOp {
1508 FPDataProcessing2SourceFixed = 0x1E200800,
1509 FPDataProcessing2SourceFMask = 0x5F200C00,
1510 FPDataProcessing2SourceMask = 0xFFE0FC00,
1511 FMUL = FPDataProcessing2SourceFixed | 0x00000000,
1512 FMUL_h = FMUL | FP16,
1513 FMUL_s = FMUL,
1514 FMUL_d = FMUL | FP64,
1515 FDIV = FPDataProcessing2SourceFixed | 0x00001000,
1516 FDIV_h = FDIV | FP16,
1517 FDIV_s = FDIV,
1518 FDIV_d = FDIV | FP64,
1519 FADD = FPDataProcessing2SourceFixed | 0x00002000,
1520 FADD_h = FADD | FP16,
1521 FADD_s = FADD,
1522 FADD_d = FADD | FP64,
1523 FSUB = FPDataProcessing2SourceFixed | 0x00003000,
1524 FSUB_h = FSUB | FP16,
1525 FSUB_s = FSUB,
1526 FSUB_d = FSUB | FP64,
1527 FMAX = FPDataProcessing2SourceFixed | 0x00004000,
1528 FMAX_h = FMAX | FP16,
1529 FMAX_s = FMAX,
1530 FMAX_d = FMAX | FP64,
1531 FMIN = FPDataProcessing2SourceFixed | 0x00005000,
1532 FMIN_h = FMIN | FP16,
1533 FMIN_s = FMIN,
1534 FMIN_d = FMIN | FP64,
1535 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000,
1536 FMAXNM_h = FMAXNM | FP16,
1537 FMAXNM_s = FMAXNM,
1538 FMAXNM_d = FMAXNM | FP64,
1539 FMINNM = FPDataProcessing2SourceFixed | 0x00007000,
1540 FMINNM_h = FMINNM | FP16,
1541 FMINNM_s = FMINNM,
1542 FMINNM_d = FMINNM | FP64,
1543 FNMUL = FPDataProcessing2SourceFixed | 0x00008000,
1544 FNMUL_h = FNMUL | FP16,
1545 FNMUL_s = FNMUL,
1546 FNMUL_d = FNMUL | FP64
1547 };
1548
1549 // Floating point data processing 3 source.
1550 enum FPDataProcessing3SourceOp {
1551 FPDataProcessing3SourceFixed = 0x1F000000,
1552 FPDataProcessing3SourceFMask = 0x5F000000,
1553 FPDataProcessing3SourceMask = 0xFFE08000,
1554 FMADD_h = FPDataProcessing3SourceFixed | 0x00C00000,
1555 FMSUB_h = FPDataProcessing3SourceFixed | 0x00C08000,
1556 FNMADD_h = FPDataProcessing3SourceFixed | 0x00E00000,
1557 FNMSUB_h = FPDataProcessing3SourceFixed | 0x00E08000,
1558 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000,
1559 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000,
1560 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000,
1561 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000,
1562 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000,
1563 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000,
1564 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000,
1565 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000
1566 };
1567
1568 // Conversion between floating point and integer.
1569 enum FPIntegerConvertOp {
1570 FPIntegerConvertFixed = 0x1E200000,
1571 FPIntegerConvertFMask = 0x5F20FC00,
1572 FPIntegerConvertMask = 0xFFFFFC00,
1573 FCVTNS = FPIntegerConvertFixed | 0x00000000,
1574 FCVTNS_wh = FCVTNS | FP16,
1575 FCVTNS_xh = FCVTNS | SixtyFourBits | FP16,
1576 FCVTNS_ws = FCVTNS,
1577 FCVTNS_xs = FCVTNS | SixtyFourBits,
1578 FCVTNS_wd = FCVTNS | FP64,
1579 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
1580 FCVTNU = FPIntegerConvertFixed | 0x00010000,
1581 FCVTNU_wh = FCVTNU | FP16,
1582 FCVTNU_xh = FCVTNU | SixtyFourBits | FP16,
1583 FCVTNU_ws = FCVTNU,
1584 FCVTNU_xs = FCVTNU | SixtyFourBits,
1585 FCVTNU_wd = FCVTNU | FP64,
1586 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64,
1587 FCVTPS = FPIntegerConvertFixed | 0x00080000,
1588 FCVTPS_wh = FCVTPS | FP16,
1589 FCVTPS_xh = FCVTPS | SixtyFourBits | FP16,
1590 FCVTPS_ws = FCVTPS,
1591 FCVTPS_xs = FCVTPS | SixtyFourBits,
1592 FCVTPS_wd = FCVTPS | FP64,
1593 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64,
1594 FCVTPU = FPIntegerConvertFixed | 0x00090000,
1595 FCVTPU_wh = FCVTPU | FP16,
1596 FCVTPU_xh = FCVTPU | SixtyFourBits | FP16,
1597 FCVTPU_ws = FCVTPU,
1598 FCVTPU_xs = FCVTPU | SixtyFourBits,
1599 FCVTPU_wd = FCVTPU | FP64,
1600 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64,
1601 FCVTMS = FPIntegerConvertFixed | 0x00100000,
1602 FCVTMS_wh = FCVTMS | FP16,
1603 FCVTMS_xh = FCVTMS | SixtyFourBits | FP16,
1604 FCVTMS_ws = FCVTMS,
1605 FCVTMS_xs = FCVTMS | SixtyFourBits,
1606 FCVTMS_wd = FCVTMS | FP64,
1607 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
1608 FCVTMU = FPIntegerConvertFixed | 0x00110000,
1609 FCVTMU_wh = FCVTMU | FP16,
1610 FCVTMU_xh = FCVTMU | SixtyFourBits | FP16,
1611 FCVTMU_ws = FCVTMU,
1612 FCVTMU_xs = FCVTMU | SixtyFourBits,
1613 FCVTMU_wd = FCVTMU | FP64,
1614 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64,
1615 FCVTZS = FPIntegerConvertFixed | 0x00180000,
1616 FCVTZS_wh = FCVTZS | FP16,
1617 FCVTZS_xh = FCVTZS | SixtyFourBits | FP16,
1618 FCVTZS_ws = FCVTZS,
1619 FCVTZS_xs = FCVTZS | SixtyFourBits,
1620 FCVTZS_wd = FCVTZS | FP64,
1621 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
1622 FCVTZU = FPIntegerConvertFixed | 0x00190000,
1623 FCVTZU_wh = FCVTZU | FP16,
1624 FCVTZU_xh = FCVTZU | SixtyFourBits | FP16,
1625 FCVTZU_ws = FCVTZU,
1626 FCVTZU_xs = FCVTZU | SixtyFourBits,
1627 FCVTZU_wd = FCVTZU | FP64,
1628 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
1629 SCVTF = FPIntegerConvertFixed | 0x00020000,
1630 SCVTF_hw = SCVTF | FP16,
1631 SCVTF_hx = SCVTF | SixtyFourBits | FP16,
1632 SCVTF_sw = SCVTF,
1633 SCVTF_sx = SCVTF | SixtyFourBits,
1634 SCVTF_dw = SCVTF | FP64,
1635 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
1636 UCVTF = FPIntegerConvertFixed | 0x00030000,
1637 UCVTF_hw = UCVTF | FP16,
1638 UCVTF_hx = UCVTF | SixtyFourBits | FP16,
1639 UCVTF_sw = UCVTF,
1640 UCVTF_sx = UCVTF | SixtyFourBits,
1641 UCVTF_dw = UCVTF | FP64,
1642 UCVTF_dx = UCVTF | SixtyFourBits | FP64,
1643 FCVTAS = FPIntegerConvertFixed | 0x00040000,
1644 FCVTAS_wh = FCVTAS | FP16,
1645 FCVTAS_xh = FCVTAS | SixtyFourBits | FP16,
1646 FCVTAS_ws = FCVTAS,
1647 FCVTAS_xs = FCVTAS | SixtyFourBits,
1648 FCVTAS_wd = FCVTAS | FP64,
1649 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64,
1650 FCVTAU = FPIntegerConvertFixed | 0x00050000,
1651 FCVTAU_wh = FCVTAU | FP16,
1652 FCVTAU_xh = FCVTAU | SixtyFourBits | FP16,
1653 FCVTAU_ws = FCVTAU,
1654 FCVTAU_xs = FCVTAU | SixtyFourBits,
1655 FCVTAU_wd = FCVTAU | FP64,
1656 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64,
1657 FMOV_wh = FPIntegerConvertFixed | 0x00060000 | FP16,
1658 FMOV_hw = FPIntegerConvertFixed | 0x00070000 | FP16,
1659 FMOV_xh = FMOV_wh | SixtyFourBits,
1660 FMOV_hx = FMOV_hw | SixtyFourBits,
1661 FMOV_ws = FPIntegerConvertFixed | 0x00060000,
1662 FMOV_sw = FPIntegerConvertFixed | 0x00070000,
1663 FMOV_xd = FMOV_ws | SixtyFourBits | FP64,
1664 FMOV_dx = FMOV_sw | SixtyFourBits | FP64,
1665 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000,
1666 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000,
1667 FJCVTZS = FPIntegerConvertFixed | FP64 | 0x001E0000
1668 };
1669
1670 // Conversion between fixed point and floating point.
1671 enum FPFixedPointConvertOp {
1672 FPFixedPointConvertFixed = 0x1E000000,
1673 FPFixedPointConvertFMask = 0x5F200000,
1674 FPFixedPointConvertMask = 0xFFFF0000,
1675 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000,
1676 FCVTZS_wh_fixed = FCVTZS_fixed | FP16,
1677 FCVTZS_xh_fixed = FCVTZS_fixed | SixtyFourBits | FP16,
1678 FCVTZS_ws_fixed = FCVTZS_fixed,
1679 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits,
1680 FCVTZS_wd_fixed = FCVTZS_fixed | FP64,
1681 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
1682 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000,
1683 FCVTZU_wh_fixed = FCVTZU_fixed | FP16,
1684 FCVTZU_xh_fixed = FCVTZU_fixed | SixtyFourBits | FP16,
1685 FCVTZU_ws_fixed = FCVTZU_fixed,
1686 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits,
1687 FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
1688 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64,
1689 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000,
1690 SCVTF_hw_fixed = SCVTF_fixed | FP16,
1691 SCVTF_hx_fixed = SCVTF_fixed | SixtyFourBits | FP16,
1692 SCVTF_sw_fixed = SCVTF_fixed,
1693 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits,
1694 SCVTF_dw_fixed = SCVTF_fixed | FP64,
1695 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64,
1696 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000,
1697 UCVTF_hw_fixed = UCVTF_fixed | FP16,
1698 UCVTF_hx_fixed = UCVTF_fixed | SixtyFourBits | FP16,
1699 UCVTF_sw_fixed = UCVTF_fixed,
1700 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits,
1701 UCVTF_dw_fixed = UCVTF_fixed | FP64,
1702 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64
1703 };
1704
1705 // Crypto - two register SHA.
1706 enum Crypto2RegSHAOp {
1707 Crypto2RegSHAFixed = 0x5E280800,
1708 Crypto2RegSHAFMask = 0xFF3E0C00
1709 };
1710
1711 // Crypto - three register SHA.
1712 enum Crypto3RegSHAOp {
1713 Crypto3RegSHAFixed = 0x5E000000,
1714 Crypto3RegSHAFMask = 0xFF208C00
1715 };
1716
1717 // Crypto - AES.
1718 enum CryptoAESOp {
1719 CryptoAESFixed = 0x4E280800,
1720 CryptoAESFMask = 0xFF3E0C00
1721 };
1722
1723 // NEON instructions with two register operands.
1724 enum NEON2RegMiscOp {
1725 NEON2RegMiscFixed = 0x0E200800,
1726 NEON2RegMiscFMask = 0x9F3E0C00,
1727 NEON2RegMiscMask = 0xBF3FFC00,
1728 NEON2RegMiscUBit = 0x20000000,
1729 NEON_REV64 = NEON2RegMiscFixed | 0x00000000,
1730 NEON_REV32 = NEON2RegMiscFixed | 0x20000000,
1731 NEON_REV16 = NEON2RegMiscFixed | 0x00001000,
1732 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000,
1733 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit,
1734 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000,
1735 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit,
1736 NEON_CLS = NEON2RegMiscFixed | 0x00004000,
1737 NEON_CLZ = NEON2RegMiscFixed | 0x20004000,
1738 NEON_CNT = NEON2RegMiscFixed | 0x00005000,
1739 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000,
1740 NEON_SADALP = NEON2RegMiscFixed | 0x00006000,
1741 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit,
1742 NEON_SQABS = NEON2RegMiscFixed | 0x00007000,
1743 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000,
1744 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000,
1745 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000,
1746 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000,
1747 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000,
1748 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000,
1749 NEON_ABS = NEON2RegMiscFixed | 0x0000B000,
1750 NEON_NEG = NEON2RegMiscFixed | 0x2000B000,
1751 NEON_XTN = NEON2RegMiscFixed | 0x00012000,
1752 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000,
1753 NEON_SHLL = NEON2RegMiscFixed | 0x20013000,
1754 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000,
1755 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit,
1756
1757 NEON2RegMiscOpcode = 0x0001F000,
1758 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode,
1759 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode,
1760 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode,
1761 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode,
1762
1763 // These instructions use only one bit of the size field. The other bit is
1764 // used to distinguish between instructions.
1765 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000,
1766 NEON_FABS = NEON2RegMiscFixed | 0x0080F000,
1767 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000,
1768 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000,
1769 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000,
1770 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000,
1771 NEON_FRINT32X = NEON2RegMiscFixed | 0x2001E000,
1772 NEON_FRINT32Z = NEON2RegMiscFixed | 0x0001E000,
1773 NEON_FRINT64X = NEON2RegMiscFixed | 0x2001F000,
1774 NEON_FRINT64Z = NEON2RegMiscFixed | 0x0001F000,
1775 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000,
1776 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000,
1777 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000,
1778 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000,
1779 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000,
1780 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000,
1781 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000,
1782 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000,
1783 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit,
1784 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000,
1785 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit,
1786 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000,
1787 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit,
1788 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000,
1789 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit,
1790 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000,
1791 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit,
1792 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000,
1793 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000,
1794 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit,
1795 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000,
1796 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000,
1797 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000,
1798 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000,
1799 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000,
1800 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000,
1801 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000,
1802 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000,
1803 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000,
1804
1805 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode,
1806 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode
1807 };
1808
1809 // NEON instructions with two register operands (FP16).
1810 enum NEON2RegMiscFP16Op {
1811 NEON2RegMiscFP16Fixed = 0x0E780800,
1812 NEON2RegMiscFP16FMask = 0x9F7E0C00,
1813 NEON2RegMiscFP16Mask = 0xBFFFFC00,
1814 NEON_FRINTN_H = NEON2RegMiscFP16Fixed | 0x00018000,
1815 NEON_FRINTM_H = NEON2RegMiscFP16Fixed | 0x00019000,
1816 NEON_FCVTNS_H = NEON2RegMiscFP16Fixed | 0x0001A000,
1817 NEON_FCVTMS_H = NEON2RegMiscFP16Fixed | 0x0001B000,
1818 NEON_FCVTAS_H = NEON2RegMiscFP16Fixed | 0x0001C000,
1819 NEON_SCVTF_H = NEON2RegMiscFP16Fixed | 0x0001D000,
1820 NEON_FCMGT_H_zero = NEON2RegMiscFP16Fixed | 0x0080C000,
1821 NEON_FCMEQ_H_zero = NEON2RegMiscFP16Fixed | 0x0080D000,
1822 NEON_FCMLT_H_zero = NEON2RegMiscFP16Fixed | 0x0080E000,
1823 NEON_FABS_H = NEON2RegMiscFP16Fixed | 0x0080F000,
1824 NEON_FRINTP_H = NEON2RegMiscFP16Fixed | 0x00818000,
1825 NEON_FRINTZ_H = NEON2RegMiscFP16Fixed | 0x00819000,
1826 NEON_FCVTPS_H = NEON2RegMiscFP16Fixed | 0x0081A000,
1827 NEON_FCVTZS_H = NEON2RegMiscFP16Fixed | 0x0081B000,
1828 NEON_FRECPE_H = NEON2RegMiscFP16Fixed | 0x0081D000,
1829 NEON_FRINTA_H = NEON2RegMiscFP16Fixed | 0x20018000,
1830 NEON_FRINTX_H = NEON2RegMiscFP16Fixed | 0x20019000,
1831 NEON_FCVTNU_H = NEON2RegMiscFP16Fixed | 0x2001A000,
1832 NEON_FCVTMU_H = NEON2RegMiscFP16Fixed | 0x2001B000,
1833 NEON_FCVTAU_H = NEON2RegMiscFP16Fixed | 0x2001C000,
1834 NEON_UCVTF_H = NEON2RegMiscFP16Fixed | 0x2001D000,
1835 NEON_FCMGE_H_zero = NEON2RegMiscFP16Fixed | 0x2080C000,
1836 NEON_FCMLE_H_zero = NEON2RegMiscFP16Fixed | 0x2080D000,
1837 NEON_FNEG_H = NEON2RegMiscFP16Fixed | 0x2080F000,
1838 NEON_FRINTI_H = NEON2RegMiscFP16Fixed | 0x20819000,
1839 NEON_FCVTPU_H = NEON2RegMiscFP16Fixed | 0x2081A000,
1840 NEON_FCVTZU_H = NEON2RegMiscFP16Fixed | 0x2081B000,
1841 NEON_FRSQRTE_H = NEON2RegMiscFP16Fixed | 0x2081D000,
1842 NEON_FSQRT_H = NEON2RegMiscFP16Fixed | 0x2081F000
1843 };
1844
1845 // NEON instructions with three same-type operands.
1846 enum NEON3SameOp {
1847 NEON3SameFixed = 0x0E200400,
1848 NEON3SameFMask = 0x9F200400,
1849 NEON3SameMask = 0xBF20FC00,
1850 NEON3SameUBit = 0x20000000,
1851 NEON_ADD = NEON3SameFixed | 0x00008000,
1852 NEON_ADDP = NEON3SameFixed | 0x0000B800,
1853 NEON_SHADD = NEON3SameFixed | 0x00000000,
1854 NEON_SHSUB = NEON3SameFixed | 0x00002000,
1855 NEON_SRHADD = NEON3SameFixed | 0x00001000,
1856 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800,
1857 NEON_CMGE = NEON3SameFixed | 0x00003800,
1858 NEON_CMGT = NEON3SameFixed | 0x00003000,
1859 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT,
1860 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE,
1861 NEON_CMTST = NEON3SameFixed | 0x00008800,
1862 NEON_MLA = NEON3SameFixed | 0x00009000,
1863 NEON_MLS = NEON3SameFixed | 0x20009000,
1864 NEON_MUL = NEON3SameFixed | 0x00009800,
1865 NEON_PMUL = NEON3SameFixed | 0x20009800,
1866 NEON_SRSHL = NEON3SameFixed | 0x00005000,
1867 NEON_SQSHL = NEON3SameFixed | 0x00004800,
1868 NEON_SQRSHL = NEON3SameFixed | 0x00005800,
1869 NEON_SSHL = NEON3SameFixed | 0x00004000,
1870 NEON_SMAX = NEON3SameFixed | 0x00006000,
1871 NEON_SMAXP = NEON3SameFixed | 0x0000A000,
1872 NEON_SMIN = NEON3SameFixed | 0x00006800,
1873 NEON_SMINP = NEON3SameFixed | 0x0000A800,
1874 NEON_SABD = NEON3SameFixed | 0x00007000,
1875 NEON_SABA = NEON3SameFixed | 0x00007800,
1876 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD,
1877 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA,
1878 NEON_SQADD = NEON3SameFixed | 0x00000800,
1879 NEON_SQSUB = NEON3SameFixed | 0x00002800,
1880 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000,
1881 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD,
1882 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB,
1883 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD,
1884 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX,
1885 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP,
1886 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN,
1887 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP,
1888 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL,
1889 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD,
1890 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL,
1891 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL,
1892 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB,
1893 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL,
1894 NEON_SQDMULH = NEON3SameFixed | 0x0000B000,
1895 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000,
1896
1897 // NEON floating point instructions with three same-type operands.
1898 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000,
1899 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000,
1900 NEON3SameFPMask = NEON3SameMask | 0x00800000,
1901 NEON_FADD = NEON3SameFixed | 0x0000D000,
1902 NEON_FSUB = NEON3SameFixed | 0x0080D000,
1903 NEON_FMUL = NEON3SameFixed | 0x2000D800,
1904 NEON_FDIV = NEON3SameFixed | 0x2000F800,
1905 NEON_FMAX = NEON3SameFixed | 0x0000F000,
1906 NEON_FMAXNM = NEON3SameFixed | 0x0000C000,
1907 NEON_FMAXP = NEON3SameFixed | 0x2000F000,
1908 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000,
1909 NEON_FMIN = NEON3SameFixed | 0x0080F000,
1910 NEON_FMINNM = NEON3SameFixed | 0x0080C000,
1911 NEON_FMINP = NEON3SameFixed | 0x2080F000,
1912 NEON_FMINNMP = NEON3SameFixed | 0x2080C000,
1913 NEON_FMLA = NEON3SameFixed | 0x0000C800,
1914 NEON_FMLS = NEON3SameFixed | 0x0080C800,
1915 NEON_FMULX = NEON3SameFixed | 0x0000D800,
1916 NEON_FRECPS = NEON3SameFixed | 0x0000F800,
1917 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800,
1918 NEON_FABD = NEON3SameFixed | 0x2080D000,
1919 NEON_FADDP = NEON3SameFixed | 0x2000D000,
1920 NEON_FCMEQ = NEON3SameFixed | 0x0000E000,
1921 NEON_FCMGE = NEON3SameFixed | 0x2000E000,
1922 NEON_FCMGT = NEON3SameFixed | 0x2080E000,
1923 NEON_FACGE = NEON3SameFixed | 0x2000E800,
1924 NEON_FACGT = NEON3SameFixed | 0x2080E800,
1925
1926 // NEON logical instructions with three same-type operands.
1927 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800,
1928 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800,
1929 NEON3SameLogicalMask = 0xBFE0FC00,
1930 NEON3SameLogicalFormatMask = NEON_Q,
1931 NEON_AND = NEON3SameLogicalFixed | 0x00000000,
1932 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000,
1933 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000,
1934 NEON_EOR = NEON3SameLogicalFixed | 0x20000000,
1935 NEON_BIC = NEON3SameLogicalFixed | 0x00400000,
1936 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000,
1937 NEON_BIT = NEON3SameLogicalFixed | 0x20800000,
1938 NEON_BSL = NEON3SameLogicalFixed | 0x20400000,
1939
1940 // FHM (FMLAL-like) instructions have an oddball encoding scheme under 3Same.
1941 NEON3SameFHMMask = 0xBFE0FC00, // U size opcode
1942 NEON_FMLAL = NEON3SameFixed | 0x0000E800, // 0 00 11101
1943 NEON_FMLAL2 = NEON3SameFixed | 0x2000C800, // 1 00 11001
1944 NEON_FMLSL = NEON3SameFixed | 0x0080E800, // 0 10 11101
1945 NEON_FMLSL2 = NEON3SameFixed | 0x2080C800 // 1 10 11001
1946 };
1947
1948 enum NEON3SameFP16 {
1949 NEON3SameFP16Fixed = 0x0E400400,
1950 NEON3SameFP16FMask = 0x9F60C400,
1951 NEON3SameFP16Mask = 0xBFE0FC00,
1952 NEON_FMAXNM_H = NEON3SameFP16Fixed | 0x00000000,
1953 NEON_FMLA_H = NEON3SameFP16Fixed | 0x00000800,
1954 NEON_FADD_H = NEON3SameFP16Fixed | 0x00001000,
1955 NEON_FMULX_H = NEON3SameFP16Fixed | 0x00001800,
1956 NEON_FCMEQ_H = NEON3SameFP16Fixed | 0x00002000,
1957 NEON_FMAX_H = NEON3SameFP16Fixed | 0x00003000,
1958 NEON_FRECPS_H = NEON3SameFP16Fixed | 0x00003800,
1959 NEON_FMINNM_H = NEON3SameFP16Fixed | 0x00800000,
1960 NEON_FMLS_H = NEON3SameFP16Fixed | 0x00800800,
1961 NEON_FSUB_H = NEON3SameFP16Fixed | 0x00801000,
1962 NEON_FMIN_H = NEON3SameFP16Fixed | 0x00803000,
1963 NEON_FRSQRTS_H = NEON3SameFP16Fixed | 0x00803800,
1964 NEON_FMAXNMP_H = NEON3SameFP16Fixed | 0x20000000,
1965 NEON_FADDP_H = NEON3SameFP16Fixed | 0x20001000,
1966 NEON_FMUL_H = NEON3SameFP16Fixed | 0x20001800,
1967 NEON_FCMGE_H = NEON3SameFP16Fixed | 0x20002000,
1968 NEON_FACGE_H = NEON3SameFP16Fixed | 0x20002800,
1969 NEON_FMAXP_H = NEON3SameFP16Fixed | 0x20003000,
1970 NEON_FDIV_H = NEON3SameFP16Fixed | 0x20003800,
1971 NEON_FMINNMP_H = NEON3SameFP16Fixed | 0x20800000,
1972 NEON_FABD_H = NEON3SameFP16Fixed | 0x20801000,
1973 NEON_FCMGT_H = NEON3SameFP16Fixed | 0x20802000,
1974 NEON_FACGT_H = NEON3SameFP16Fixed | 0x20802800,
1975 NEON_FMINP_H = NEON3SameFP16Fixed | 0x20803000
1976 };
1977
1978 // 'Extra' NEON instructions with three same-type operands.
1979 enum NEON3SameExtraOp {
1980 NEON3SameExtraFixed = 0x0E008400,
1981 NEON3SameExtraUBit = 0x20000000,
1982 NEON3SameExtraFMask = 0x9E208400,
1983 NEON3SameExtraMask = 0xBE20FC00,
1984 NEON_SQRDMLAH = NEON3SameExtraFixed | NEON3SameExtraUBit,
1985 NEON_SQRDMLSH = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00000800,
1986 NEON_SDOT = NEON3SameExtraFixed | 0x00001000,
1987 NEON_UDOT = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00001000,
1988
1989 /* v8.3 Complex Numbers */
1990 NEON3SameExtraFCFixed = 0x2E00C400,
1991 NEON3SameExtraFCFMask = 0xBF20C400,
1992 // FCMLA fixes opcode<3:2>, and uses opcode<1:0> to encode <rotate>.
1993 NEON3SameExtraFCMLAMask = NEON3SameExtraFCFMask | 0x00006000,
1994 NEON_FCMLA = NEON3SameExtraFCFixed,
1995 // FCADD fixes opcode<3:2, 0>, and uses opcode<1> to encode <rotate>.
1996 NEON3SameExtraFCADDMask = NEON3SameExtraFCFMask | 0x00006800,
1997 NEON_FCADD = NEON3SameExtraFCFixed | 0x00002000
1998 // Other encodings under NEON3SameExtraFCFMask are UNALLOCATED.
1999 };
2000
2001 // NEON instructions with three different-type operands.
2002 enum NEON3DifferentOp {
2003 NEON3DifferentFixed = 0x0E200000,
2004 NEON3DifferentFMask = 0x9F200C00,
2005 NEON3DifferentMask = 0xFF20FC00,
2006 NEON_ADDHN = NEON3DifferentFixed | 0x00004000,
2007 NEON_ADDHN2 = NEON_ADDHN | NEON_Q,
2008 NEON_PMULL = NEON3DifferentFixed | 0x0000E000,
2009 NEON_PMULL2 = NEON_PMULL | NEON_Q,
2010 NEON_RADDHN = NEON3DifferentFixed | 0x20004000,
2011 NEON_RADDHN2 = NEON_RADDHN | NEON_Q,
2012 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000,
2013 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q,
2014 NEON_SABAL = NEON3DifferentFixed | 0x00005000,
2015 NEON_SABAL2 = NEON_SABAL | NEON_Q,
2016 NEON_SABDL = NEON3DifferentFixed | 0x00007000,
2017 NEON_SABDL2 = NEON_SABDL | NEON_Q,
2018 NEON_SADDL = NEON3DifferentFixed | 0x00000000,
2019 NEON_SADDL2 = NEON_SADDL | NEON_Q,
2020 NEON_SADDW = NEON3DifferentFixed | 0x00001000,
2021 NEON_SADDW2 = NEON_SADDW | NEON_Q,
2022 NEON_SMLAL = NEON3DifferentFixed | 0x00008000,
2023 NEON_SMLAL2 = NEON_SMLAL | NEON_Q,
2024 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000,
2025 NEON_SMLSL2 = NEON_SMLSL | NEON_Q,
2026 NEON_SMULL = NEON3DifferentFixed | 0x0000C000,
2027 NEON_SMULL2 = NEON_SMULL | NEON_Q,
2028 NEON_SSUBL = NEON3DifferentFixed | 0x00002000,
2029 NEON_SSUBL2 = NEON_SSUBL | NEON_Q,
2030 NEON_SSUBW = NEON3DifferentFixed | 0x00003000,
2031 NEON_SSUBW2 = NEON_SSUBW | NEON_Q,
2032 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000,
2033 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q,
2034 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000,
2035 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q,
2036 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000,
2037 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q,
2038 NEON_SUBHN = NEON3DifferentFixed | 0x00006000,
2039 NEON_SUBHN2 = NEON_SUBHN | NEON_Q,
2040 NEON_UABAL = NEON_SABAL | NEON3SameUBit,
2041 NEON_UABAL2 = NEON_UABAL | NEON_Q,
2042 NEON_UABDL = NEON_SABDL | NEON3SameUBit,
2043 NEON_UABDL2 = NEON_UABDL | NEON_Q,
2044 NEON_UADDL = NEON_SADDL | NEON3SameUBit,
2045 NEON_UADDL2 = NEON_UADDL | NEON_Q,
2046 NEON_UADDW = NEON_SADDW | NEON3SameUBit,
2047 NEON_UADDW2 = NEON_UADDW | NEON_Q,
2048 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit,
2049 NEON_UMLAL2 = NEON_UMLAL | NEON_Q,
2050 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit,
2051 NEON_UMLSL2 = NEON_UMLSL | NEON_Q,
2052 NEON_UMULL = NEON_SMULL | NEON3SameUBit,
2053 NEON_UMULL2 = NEON_UMULL | NEON_Q,
2054 NEON_USUBL = NEON_SSUBL | NEON3SameUBit,
2055 NEON_USUBL2 = NEON_USUBL | NEON_Q,
2056 NEON_USUBW = NEON_SSUBW | NEON3SameUBit,
2057 NEON_USUBW2 = NEON_USUBW | NEON_Q
2058 };
2059
2060 // NEON instructions operating across vectors.
2061 enum NEONAcrossLanesOp {
2062 NEONAcrossLanesFixed = 0x0E300800,
2063 NEONAcrossLanesFMask = 0x9F3E0C00,
2064 NEONAcrossLanesMask = 0xBF3FFC00,
2065 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000,
2066 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000,
2067 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000,
2068 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000,
2069 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000,
2070 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000,
2071 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000,
2072
2073 NEONAcrossLanesFP16Fixed = NEONAcrossLanesFixed | 0x0000C000,
2074 NEONAcrossLanesFP16FMask = NEONAcrossLanesFMask | 0x2000C000,
2075 NEONAcrossLanesFP16Mask = NEONAcrossLanesMask | 0x20800000,
2076 NEON_FMAXNMV_H = NEONAcrossLanesFP16Fixed | 0x00000000,
2077 NEON_FMAXV_H = NEONAcrossLanesFP16Fixed | 0x00003000,
2078 NEON_FMINNMV_H = NEONAcrossLanesFP16Fixed | 0x00800000,
2079 NEON_FMINV_H = NEONAcrossLanesFP16Fixed | 0x00803000,
2080
2081 // NEON floating point across instructions.
2082 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x2000C000,
2083 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x2000C000,
2084 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x20800000,
2085
2086 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000,
2087 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000,
2088 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000,
2089 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000
2090 };
2091
2092 // NEON instructions with indexed element operand.
2093 enum NEONByIndexedElementOp {
2094 NEONByIndexedElementFixed = 0x0F000000,
2095 NEONByIndexedElementFMask = 0x9F000400,
2096 NEONByIndexedElementMask = 0xBF00F400,
2097 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000,
2098 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000,
2099 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000,
2100 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000,
2101 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000,
2102 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000,
2103 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000,
2104 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000,
2105 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000,
2106 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000,
2107 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000,
2108 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000,
2109 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000,
2110 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000,
2111 NEON_SDOT_byelement = NEONByIndexedElementFixed | 0x0000E000,
2112 NEON_SQRDMLAH_byelement = NEONByIndexedElementFixed | 0x2000D000,
2113 NEON_UDOT_byelement = NEONByIndexedElementFixed | 0x2000E000,
2114 NEON_SQRDMLSH_byelement = NEONByIndexedElementFixed | 0x2000F000,
2115
2116 NEON_FMLA_H_byelement = NEONByIndexedElementFixed | 0x00001000,
2117 NEON_FMLS_H_byelement = NEONByIndexedElementFixed | 0x00005000,
2118 NEON_FMUL_H_byelement = NEONByIndexedElementFixed | 0x00009000,
2119 NEON_FMULX_H_byelement = NEONByIndexedElementFixed | 0x20009000,
2120
2121 // Floating point instructions.
2122 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000,
2123 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000,
2124 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000,
2125 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000,
2126 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000,
2127 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000,
2128
2129 // FMLAL-like instructions.
2130 // For all cases: U = x, size = 10, opcode = xx00
2131 NEONByIndexedElementFPLongFixed = NEONByIndexedElementFixed | 0x00800000,
2132 NEONByIndexedElementFPLongFMask = NEONByIndexedElementFMask | 0x00C03000,
2133 NEONByIndexedElementFPLongMask = 0xBFC0F400,
2134 NEON_FMLAL_H_byelement = NEONByIndexedElementFixed | 0x00800000,
2135 NEON_FMLAL2_H_byelement = NEONByIndexedElementFixed | 0x20808000,
2136 NEON_FMLSL_H_byelement = NEONByIndexedElementFixed | 0x00804000,
2137 NEON_FMLSL2_H_byelement = NEONByIndexedElementFixed | 0x2080C000,
2138
2139 // Complex instruction(s).
2140 // This is necessary because the 'rot' encoding moves into the
2141 // NEONByIndex..Mask space.
2142 NEONByIndexedElementFPComplexMask = 0xBF009400,
2143 NEON_FCMLA_byelement = NEONByIndexedElementFixed | 0x20001000
2144 };
2145
2146 // NEON register copy.
2147 enum NEONCopyOp {
2148 NEONCopyFixed = 0x0E000400,
2149 NEONCopyFMask = 0x9FE08400,
2150 NEONCopyMask = 0x3FE08400,
2151 NEONCopyInsElementMask = NEONCopyMask | 0x40000000,
2152 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800,
2153 NEONCopyDupElementMask = NEONCopyMask | 0x20007800,
2154 NEONCopyDupGeneralMask = NEONCopyDupElementMask,
2155 NEONCopyUmovMask = NEONCopyMask | 0x20007800,
2156 NEONCopySmovMask = NEONCopyMask | 0x20007800,
2157 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000,
2158 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800,
2159 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000,
2160 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800,
2161 NEON_SMOV = NEONCopyFixed | 0x00002800,
2162 NEON_UMOV = NEONCopyFixed | 0x00003800
2163 };
2164
2165 // NEON extract.
2166 enum NEONExtractOp {
2167 NEONExtractFixed = 0x2E000000,
2168 NEONExtractFMask = 0xBF208400,
2169 NEONExtractMask = 0xBFE08400,
2170 NEON_EXT = NEONExtractFixed | 0x00000000
2171 };
2172
2173 enum NEONLoadStoreMultiOp {
2174 NEONLoadStoreMultiL = 0x00400000,
2175 NEONLoadStoreMulti1_1v = 0x00007000,
2176 NEONLoadStoreMulti1_2v = 0x0000A000,
2177 NEONLoadStoreMulti1_3v = 0x00006000,
2178 NEONLoadStoreMulti1_4v = 0x00002000,
2179 NEONLoadStoreMulti2 = 0x00008000,
2180 NEONLoadStoreMulti3 = 0x00004000,
2181 NEONLoadStoreMulti4 = 0x00000000
2182 };
2183
2184 // NEON load/store multiple structures.
2185 enum NEONLoadStoreMultiStructOp {
2186 NEONLoadStoreMultiStructFixed = 0x0C000000,
2187 NEONLoadStoreMultiStructFMask = 0xBFBF0000,
2188 NEONLoadStoreMultiStructMask = 0xBFFFF000,
2189 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed,
2190 NEONLoadStoreMultiStructLoad = NEONLoadStoreMultiStructFixed |
2191 NEONLoadStoreMultiL,
2192 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v,
2193 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v,
2194 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v,
2195 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v,
2196 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2,
2197 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3,
2198 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4,
2199 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v,
2200 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v,
2201 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v,
2202 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v,
2203 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2,
2204 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3,
2205 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4
2206 };
2207
2208 // NEON load/store multiple structures with post-index addressing.
2209 enum NEONLoadStoreMultiStructPostIndexOp {
2210 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000,
2211 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000,
2212 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000,
2213 NEONLoadStoreMultiStructPostIndex = 0x00800000,
2214 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex,
2215 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex,
2216 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex,
2217 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex,
2218 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex,
2219 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex,
2220 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex,
2221 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex,
2222 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex,
2223 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex,
2224 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex,
2225 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex,
2226 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex,
2227 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex
2228 };
2229
2230 enum NEONLoadStoreSingleOp {
2231 NEONLoadStoreSingle1 = 0x00000000,
2232 NEONLoadStoreSingle2 = 0x00200000,
2233 NEONLoadStoreSingle3 = 0x00002000,
2234 NEONLoadStoreSingle4 = 0x00202000,
2235 NEONLoadStoreSingleL = 0x00400000,
2236 NEONLoadStoreSingle_b = 0x00000000,
2237 NEONLoadStoreSingle_h = 0x00004000,
2238 NEONLoadStoreSingle_s = 0x00008000,
2239 NEONLoadStoreSingle_d = 0x00008400,
2240 NEONLoadStoreSingleAllLanes = 0x0000C000,
2241 NEONLoadStoreSingleLenMask = 0x00202000
2242 };
2243
2244 // NEON load/store single structure.
2245 enum NEONLoadStoreSingleStructOp {
2246 NEONLoadStoreSingleStructFixed = 0x0D000000,
2247 NEONLoadStoreSingleStructFMask = 0xBF9F0000,
2248 NEONLoadStoreSingleStructMask = 0xBFFFE000,
2249 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed,
2250 NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed |
2251 NEONLoadStoreSingleL,
2252 NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 |
2253 NEONLoadStoreSingleStructLoad,
2254 NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 |
2255 NEONLoadStoreSingleStructLoad,
2256 NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 |
2257 NEONLoadStoreSingleStructLoad,
2258 NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 |
2259 NEONLoadStoreSingleStructLoad,
2260 NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 |
2261 NEONLoadStoreSingleStructFixed,
2262 NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 |
2263 NEONLoadStoreSingleStructFixed,
2264 NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 |
2265 NEONLoadStoreSingleStructFixed,
2266 NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 |
2267 NEONLoadStoreSingleStructFixed,
2268 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b,
2269 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h,
2270 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s,
2271 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d,
2272 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes,
2273 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b,
2274 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h,
2275 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s,
2276 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d,
2277
2278 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b,
2279 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h,
2280 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s,
2281 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d,
2282 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes,
2283 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b,
2284 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h,
2285 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s,
2286 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d,
2287
2288 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b,
2289 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h,
2290 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s,
2291 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d,
2292 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes,
2293 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b,
2294 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h,
2295 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s,
2296 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d,
2297
2298 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b,
2299 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h,
2300 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s,
2301 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d,
2302 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes,
2303 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b,
2304 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h,
2305 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s,
2306 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d
2307 };
2308
2309 // NEON load/store single structure with post-index addressing.
2310 enum NEONLoadStoreSingleStructPostIndexOp {
2311 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
2312 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
2313 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000,
2314 NEONLoadStoreSingleStructPostIndex = 0x00800000,
2315 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex,
2316 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex,
2317 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex,
2318 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex,
2319 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex,
2320 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex,
2321 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex,
2322 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex,
2323 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex,
2324
2325 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex,
2326 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex,
2327 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex,
2328 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex,
2329 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex,
2330 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex,
2331 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex,
2332 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex,
2333 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex,
2334
2335 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex,
2336 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex,
2337 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex,
2338 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex,
2339 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex,
2340 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex,
2341 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex,
2342 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex,
2343 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex,
2344
2345 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex,
2346 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex,
2347 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex,
2348 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex,
2349 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex,
2350 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex,
2351 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex,
2352 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex,
2353 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex
2354 };
2355
2356 // NEON modified immediate.
2357 enum NEONModifiedImmediateOp {
2358 NEONModifiedImmediateFixed = 0x0F000400,
2359 NEONModifiedImmediateFMask = 0x9FF80400,
2360 NEONModifiedImmediateOpBit = 0x20000000,
2361 NEONModifiedImmediate_FMOV = NEONModifiedImmediateFixed | 0x00000800,
2362 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000,
2363 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000,
2364 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000,
2365 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000
2366 };
2367
2368 // NEON shift immediate.
2369 enum NEONShiftImmediateOp {
2370 NEONShiftImmediateFixed = 0x0F000400,
2371 NEONShiftImmediateFMask = 0x9F800400,
2372 NEONShiftImmediateMask = 0xBF80FC00,
2373 NEONShiftImmediateUBit = 0x20000000,
2374 NEON_SHL = NEONShiftImmediateFixed | 0x00005000,
2375 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000,
2376 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000,
2377 NEON_SLI = NEONShiftImmediateFixed | 0x20005000,
2378 NEON_SRI = NEONShiftImmediateFixed | 0x20004000,
2379 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000,
2380 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800,
2381 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000,
2382 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800,
2383 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000,
2384 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800,
2385 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000,
2386 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800,
2387 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000,
2388 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000,
2389 NEON_USHR = NEONShiftImmediateFixed | 0x20000000,
2390 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000,
2391 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000,
2392 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000,
2393 NEON_USRA = NEONShiftImmediateFixed | 0x20001000,
2394 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000,
2395 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000,
2396 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000,
2397 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000,
2398 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800,
2399 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800,
2400 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000,
2401 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000
2402 };
2403
2404 // NEON table.
2405 enum NEONTableOp {
2406 NEONTableFixed = 0x0E000000,
2407 NEONTableFMask = 0xBF208C00,
2408 NEONTableExt = 0x00001000,
2409 NEONTableMask = 0xBF20FC00,
2410 NEON_TBL_1v = NEONTableFixed | 0x00000000,
2411 NEON_TBL_2v = NEONTableFixed | 0x00002000,
2412 NEON_TBL_3v = NEONTableFixed | 0x00004000,
2413 NEON_TBL_4v = NEONTableFixed | 0x00006000,
2414 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt,
2415 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt,
2416 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt,
2417 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt
2418 };
2419
2420 // NEON perm.
2421 enum NEONPermOp {
2422 NEONPermFixed = 0x0E000800,
2423 NEONPermFMask = 0xBF208C00,
2424 NEONPermMask = 0x3F20FC00,
2425 NEON_UZP1 = NEONPermFixed | 0x00001000,
2426 NEON_TRN1 = NEONPermFixed | 0x00002000,
2427 NEON_ZIP1 = NEONPermFixed | 0x00003000,
2428 NEON_UZP2 = NEONPermFixed | 0x00005000,
2429 NEON_TRN2 = NEONPermFixed | 0x00006000,
2430 NEON_ZIP2 = NEONPermFixed | 0x00007000
2431 };
2432
2433 // NEON scalar instructions with two register operands.
2434 enum NEONScalar2RegMiscOp {
2435 NEONScalar2RegMiscFixed = 0x5E200800,
2436 NEONScalar2RegMiscFMask = 0xDF3E0C00,
2437 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask,
2438 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero,
2439 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero,
2440 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero,
2441 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero,
2442 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero,
2443 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS,
2444 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS,
2445 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG,
2446 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG,
2447 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN,
2448 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN,
2449 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN,
2450 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD,
2451 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD,
2452
2453 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode,
2454 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode,
2455
2456 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000,
2457 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE,
2458 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE,
2459 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF,
2460 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF,
2461 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero,
2462 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero,
2463 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero,
2464 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero,
2465 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero,
2466 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000,
2467 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS,
2468 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU,
2469 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS,
2470 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU,
2471 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS,
2472 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU,
2473 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS,
2474 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU,
2475 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS,
2476 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU,
2477 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN
2478 };
2479
2480 // NEON instructions with two register operands (FP16).
2481 enum NEONScalar2RegMiscFP16Op {
2482 NEONScalar2RegMiscFP16Fixed = 0x5E780800,
2483 NEONScalar2RegMiscFP16FMask = 0xDF7E0C00,
2484 NEONScalar2RegMiscFP16Mask = 0xFFFFFC00,
2485 NEON_FCVTNS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNS_H,
2486 NEON_FCVTMS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMS_H,
2487 NEON_FCVTAS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAS_H,
2488 NEON_SCVTF_H_scalar = NEON_Q | NEONScalar | NEON_SCVTF_H,
2489 NEON_FCMGT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H_zero,
2490 NEON_FCMEQ_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H_zero,
2491 NEON_FCMLT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_H_zero,
2492 NEON_FCVTPS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPS_H,
2493 NEON_FCVTZS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_H,
2494 NEON_FRECPE_H_scalar = NEON_Q | NEONScalar | NEON_FRECPE_H,
2495 NEON_FRECPX_H_scalar = NEONScalar2RegMiscFP16Fixed | 0x0081F000,
2496 NEON_FCVTNU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNU_H,
2497 NEON_FCVTMU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMU_H,
2498 NEON_FCVTAU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAU_H,
2499 NEON_UCVTF_H_scalar = NEON_Q | NEONScalar | NEON_UCVTF_H,
2500 NEON_FCMGE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H_zero,
2501 NEON_FCMLE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_H_zero,
2502 NEON_FCVTPU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPU_H,
2503 NEON_FCVTZU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_H,
2504 NEON_FRSQRTE_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE_H
2505 };
2506
2507 // NEON scalar instructions with three same-type operands.
2508 enum NEONScalar3SameOp {
2509 NEONScalar3SameFixed = 0x5E200400,
2510 NEONScalar3SameFMask = 0xDF200400,
2511 NEONScalar3SameMask = 0xFF20FC00,
2512 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD,
2513 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ,
2514 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE,
2515 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT,
2516 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI,
2517 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS,
2518 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST,
2519 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB,
2520 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD,
2521 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD,
2522 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB,
2523 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB,
2524 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL,
2525 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL,
2526 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL,
2527 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL,
2528 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL,
2529 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL,
2530 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL,
2531 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL,
2532 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH,
2533 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH,
2534
2535 // NEON floating point scalar instructions with three same-type operands.
2536 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000,
2537 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000,
2538 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000,
2539 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE,
2540 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT,
2541 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ,
2542 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE,
2543 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT,
2544 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX,
2545 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS,
2546 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS,
2547 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD
2548 };
2549
2550 // NEON scalar instructions with three different-type operands.
2551 enum NEONScalar3DiffOp {
2552 NEONScalar3DiffFixed = 0x5E200000,
2553 NEONScalar3DiffFMask = 0xDF200C00,
2554 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask,
2555 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL,
2556 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL,
2557 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL
2558 };
2559
2560 // NEON scalar instructions with indexed element operand.
2561 enum NEONScalarByIndexedElementOp {
2562 NEONScalarByIndexedElementFixed = 0x5F000000,
2563 NEONScalarByIndexedElementFMask = 0xDF000400,
2564 NEONScalarByIndexedElementMask = 0xFF00F400,
2565 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement,
2566 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement,
2567 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement,
2568 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement,
2569 NEON_SQRDMULH_byelement_scalar
2570 = NEON_Q | NEONScalar | NEON_SQRDMULH_byelement,
2571 NEON_SQRDMLAH_byelement_scalar
2572 = NEON_Q | NEONScalar | NEON_SQRDMLAH_byelement,
2573 NEON_SQRDMLSH_byelement_scalar
2574 = NEON_Q | NEONScalar | NEON_SQRDMLSH_byelement,
2575 NEON_FMLA_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_H_byelement,
2576 NEON_FMLS_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_H_byelement,
2577 NEON_FMUL_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_H_byelement,
2578 NEON_FMULX_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_H_byelement,
2579
2580 // Floating point instructions.
2581 NEONScalarByIndexedElementFPFixed
2582 = NEONScalarByIndexedElementFixed | 0x00800000,
2583 NEONScalarByIndexedElementFPMask
2584 = NEONScalarByIndexedElementMask | 0x00800000,
2585 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement,
2586 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement,
2587 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement,
2588 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement
2589 };
2590
2591 // NEON scalar register copy.
2592 enum NEONScalarCopyOp {
2593 NEONScalarCopyFixed = 0x5E000400,
2594 NEONScalarCopyFMask = 0xDFE08400,
2595 NEONScalarCopyMask = 0xFFE0FC00,
2596 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT
2597 };
2598
2599 // NEON scalar pairwise instructions.
2600 enum NEONScalarPairwiseOp {
2601 NEONScalarPairwiseFixed = 0x5E300800,
2602 NEONScalarPairwiseFMask = 0xDF3E0C00,
2603 NEONScalarPairwiseMask = 0xFFB1F800,
2604 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000,
2605 NEON_FMAXNMP_h_scalar = NEONScalarPairwiseFixed | 0x0000C000,
2606 NEON_FADDP_h_scalar = NEONScalarPairwiseFixed | 0x0000D000,
2607 NEON_FMAXP_h_scalar = NEONScalarPairwiseFixed | 0x0000F000,
2608 NEON_FMINNMP_h_scalar = NEONScalarPairwiseFixed | 0x0080C000,
2609 NEON_FMINP_h_scalar = NEONScalarPairwiseFixed | 0x0080F000,
2610 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000,
2611 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000,
2612 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000,
2613 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000,
2614 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000
2615 };
2616
2617 // NEON scalar shift immediate.
2618 enum NEONScalarShiftImmediateOp {
2619 NEONScalarShiftImmediateFixed = 0x5F000400,
2620 NEONScalarShiftImmediateFMask = 0xDF800400,
2621 NEONScalarShiftImmediateMask = 0xFF80FC00,
2622 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL,
2623 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI,
2624 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI,
2625 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR,
2626 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR,
2627 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR,
2628 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR,
2629 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA,
2630 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA,
2631 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA,
2632 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA,
2633 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN,
2634 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN,
2635 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN,
2636 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN,
2637 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN,
2638 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN,
2639 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU,
2640 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm,
2641 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm,
2642 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm,
2643 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm,
2644 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm,
2645 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
2646 };
2647
2648 enum ReservedOp {
2649 ReservedFixed = 0x00000000,
2650 ReservedFMask = 0x1E000000,
2651 ReservedMask = 0xFFFF0000,
2652
2653 UDF = ReservedFixed | 0x00000000
2654 };
2655
2656 // Unimplemented and unallocated instructions. These are defined to make fixed
2657 // bit assertion easier.
2658 enum UnimplementedOp {
2659 UnimplementedFixed = 0x00000000,
2660 UnimplementedFMask = 0x00000000
2661 };
2662
2663 enum UnallocatedOp {
2664 UnallocatedFixed = 0x00000000,
2665 UnallocatedFMask = 0x00000000
2666 };
2667
2668 // Instruction bit pattern for an undefined instruction, that will trigger a
2669 // SIGILL at runtime.
2670 //
2671 // A couple of strategies we can use here. There are no unencoded
2672 // instructions in the instruction set that are guaranteed to remain that
2673 // way. However there are some currently (as of 2018) unencoded
2674 // instructions that are good candidates.
2675 //
2676 // Ideally, unencoded instructions should be non-destructive to the register
2677 // state, and should be unencoded at all exception levels.
2678 //
2679 // At the trap the pc will hold the address of the offending instruction.
2680 //
2681 // Some candidates for unencoded instructions:
2682 //
2683 // 0xd4a00000 (essentially dcps0, a good one since it is nonsensical and may
2684 // remain unencoded in the future for that reason)
2685 // 0x33000000 (bfm variant)
2686 // 0xd67f0000 (br variant)
2687 // 0x5ac00c00 (rbit variant)
2688 //
2689 // This instruction is "dcps0", also has 16-bit payload if needed.
2690 static constexpr uint32_t UNDEFINED_INST_PATTERN = 0xd4a00000;
2691
2692 } // namespace vixl
2693
2694 #endif // VIXL_A64_CONSTANTS_A64_H_
2695