1 use crate::ir::types::*;
2 use crate::isa::aarch64::inst::*;
3 use crate::isa::test_utils;
4 use crate::isa::CallConv;
5 use crate::settings;
6
7 use alloc::boxed::Box;
8 use alloc::vec::Vec;
9
10 #[test]
test_aarch64_binemit()11 fn test_aarch64_binemit() {
12 let mut insns = Vec::<(Inst, &str, &str)>::new();
13
14 // N.B.: the architecture is little-endian, so when transcribing the 32-bit
15 // hex instructions from e.g. objdump disassembly, one must swap the bytes
16 // seen below. (E.g., a `ret` is normally written as the u32 `D65F03C0`,
17 // but we write it here as C0035FD6.)
18
19 // Useful helper script to produce the encodings from the text:
20 //
21 // #!/bin/sh
22 // tmp=`mktemp /tmp/XXXXXXXX.o`
23 // aarch64-linux-gnu-as /dev/stdin -o $tmp
24 // aarch64-linux-gnu-objdump -d $tmp
25 // rm -f $tmp
26 //
27 // Then:
28 //
29 // $ echo "mov x1, x2" | aarch64inst.sh
30 insns.push((Inst::Ret, "C0035FD6", "ret"));
31 insns.push((Inst::Nop0, "", "nop-zero-len"));
32 insns.push((Inst::Nop4, "1F2003D5", "nop"));
33 insns.push((
34 Inst::AluRRR {
35 alu_op: ALUOp::Add32,
36 rd: writable_xreg(1),
37 rn: xreg(2),
38 rm: xreg(3),
39 },
40 "4100030B",
41 "add w1, w2, w3",
42 ));
43 insns.push((
44 Inst::AluRRR {
45 alu_op: ALUOp::Add64,
46 rd: writable_xreg(4),
47 rn: xreg(5),
48 rm: xreg(6),
49 },
50 "A400068B",
51 "add x4, x5, x6",
52 ));
53 insns.push((
54 Inst::AluRRR {
55 alu_op: ALUOp::Sub32,
56 rd: writable_xreg(1),
57 rn: xreg(2),
58 rm: xreg(3),
59 },
60 "4100034B",
61 "sub w1, w2, w3",
62 ));
63 insns.push((
64 Inst::AluRRR {
65 alu_op: ALUOp::Sub64,
66 rd: writable_xreg(4),
67 rn: xreg(5),
68 rm: xreg(6),
69 },
70 "A40006CB",
71 "sub x4, x5, x6",
72 ));
73 insns.push((
74 Inst::AluRRR {
75 alu_op: ALUOp::Orr32,
76 rd: writable_xreg(1),
77 rn: xreg(2),
78 rm: xreg(3),
79 },
80 "4100032A",
81 "orr w1, w2, w3",
82 ));
83 insns.push((
84 Inst::AluRRR {
85 alu_op: ALUOp::Orr64,
86 rd: writable_xreg(4),
87 rn: xreg(5),
88 rm: xreg(6),
89 },
90 "A40006AA",
91 "orr x4, x5, x6",
92 ));
93 insns.push((
94 Inst::AluRRR {
95 alu_op: ALUOp::And32,
96 rd: writable_xreg(1),
97 rn: xreg(2),
98 rm: xreg(3),
99 },
100 "4100030A",
101 "and w1, w2, w3",
102 ));
103 insns.push((
104 Inst::AluRRR {
105 alu_op: ALUOp::And64,
106 rd: writable_xreg(4),
107 rn: xreg(5),
108 rm: xreg(6),
109 },
110 "A400068A",
111 "and x4, x5, x6",
112 ));
113 insns.push((
114 Inst::AluRRR {
115 alu_op: ALUOp::SubS32,
116 rd: writable_zero_reg(),
117 rn: xreg(2),
118 rm: xreg(3),
119 },
120 "5F00036B",
121 // TODO: Display as cmp
122 "subs wzr, w2, w3",
123 ));
124 insns.push((
125 Inst::AluRRR {
126 alu_op: ALUOp::SubS32,
127 rd: writable_xreg(1),
128 rn: xreg(2),
129 rm: xreg(3),
130 },
131 "4100036B",
132 "subs w1, w2, w3",
133 ));
134 insns.push((
135 Inst::AluRRR {
136 alu_op: ALUOp::SubS64,
137 rd: writable_xreg(4),
138 rn: xreg(5),
139 rm: xreg(6),
140 },
141 "A40006EB",
142 "subs x4, x5, x6",
143 ));
144 insns.push((
145 Inst::AluRRR {
146 alu_op: ALUOp::AddS32,
147 rd: writable_xreg(1),
148 rn: xreg(2),
149 rm: xreg(3),
150 },
151 "4100032B",
152 "adds w1, w2, w3",
153 ));
154 insns.push((
155 Inst::AluRRR {
156 alu_op: ALUOp::AddS64,
157 rd: writable_xreg(4),
158 rn: xreg(5),
159 rm: xreg(6),
160 },
161 "A40006AB",
162 "adds x4, x5, x6",
163 ));
164 insns.push((
165 Inst::AluRRImm12 {
166 alu_op: ALUOp::AddS64,
167 rd: writable_zero_reg(),
168 rn: xreg(5),
169 imm12: Imm12::maybe_from_u64(1).unwrap(),
170 },
171 "BF0400B1",
172 // TODO: Display as cmn.
173 "adds xzr, x5, #1",
174 ));
175 insns.push((
176 Inst::AluRRR {
177 alu_op: ALUOp::SDiv64,
178 rd: writable_xreg(4),
179 rn: xreg(5),
180 rm: xreg(6),
181 },
182 "A40CC69A",
183 "sdiv x4, x5, x6",
184 ));
185 insns.push((
186 Inst::AluRRR {
187 alu_op: ALUOp::UDiv64,
188 rd: writable_xreg(4),
189 rn: xreg(5),
190 rm: xreg(6),
191 },
192 "A408C69A",
193 "udiv x4, x5, x6",
194 ));
195
196 insns.push((
197 Inst::AluRRR {
198 alu_op: ALUOp::Eor32,
199 rd: writable_xreg(4),
200 rn: xreg(5),
201 rm: xreg(6),
202 },
203 "A400064A",
204 "eor w4, w5, w6",
205 ));
206 insns.push((
207 Inst::AluRRR {
208 alu_op: ALUOp::Eor64,
209 rd: writable_xreg(4),
210 rn: xreg(5),
211 rm: xreg(6),
212 },
213 "A40006CA",
214 "eor x4, x5, x6",
215 ));
216 insns.push((
217 Inst::AluRRR {
218 alu_op: ALUOp::AndNot32,
219 rd: writable_xreg(4),
220 rn: xreg(5),
221 rm: xreg(6),
222 },
223 "A400260A",
224 "bic w4, w5, w6",
225 ));
226 insns.push((
227 Inst::AluRRR {
228 alu_op: ALUOp::AndNot64,
229 rd: writable_xreg(4),
230 rn: xreg(5),
231 rm: xreg(6),
232 },
233 "A400268A",
234 "bic x4, x5, x6",
235 ));
236 insns.push((
237 Inst::AluRRR {
238 alu_op: ALUOp::OrrNot32,
239 rd: writable_xreg(4),
240 rn: xreg(5),
241 rm: xreg(6),
242 },
243 "A400262A",
244 "orn w4, w5, w6",
245 ));
246 insns.push((
247 Inst::AluRRR {
248 alu_op: ALUOp::OrrNot64,
249 rd: writable_xreg(4),
250 rn: xreg(5),
251 rm: xreg(6),
252 },
253 "A40026AA",
254 "orn x4, x5, x6",
255 ));
256 insns.push((
257 Inst::AluRRR {
258 alu_op: ALUOp::EorNot32,
259 rd: writable_xreg(4),
260 rn: xreg(5),
261 rm: xreg(6),
262 },
263 "A400264A",
264 "eon w4, w5, w6",
265 ));
266 insns.push((
267 Inst::AluRRR {
268 alu_op: ALUOp::EorNot64,
269 rd: writable_xreg(4),
270 rn: xreg(5),
271 rm: xreg(6),
272 },
273 "A40026CA",
274 "eon x4, x5, x6",
275 ));
276
277 insns.push((
278 Inst::AluRRR {
279 alu_op: ALUOp::RotR32,
280 rd: writable_xreg(4),
281 rn: xreg(5),
282 rm: xreg(6),
283 },
284 "A42CC61A",
285 "ror w4, w5, w6",
286 ));
287 insns.push((
288 Inst::AluRRR {
289 alu_op: ALUOp::RotR64,
290 rd: writable_xreg(4),
291 rn: xreg(5),
292 rm: xreg(6),
293 },
294 "A42CC69A",
295 "ror x4, x5, x6",
296 ));
297 insns.push((
298 Inst::AluRRR {
299 alu_op: ALUOp::Lsr32,
300 rd: writable_xreg(4),
301 rn: xreg(5),
302 rm: xreg(6),
303 },
304 "A424C61A",
305 "lsr w4, w5, w6",
306 ));
307 insns.push((
308 Inst::AluRRR {
309 alu_op: ALUOp::Lsr64,
310 rd: writable_xreg(4),
311 rn: xreg(5),
312 rm: xreg(6),
313 },
314 "A424C69A",
315 "lsr x4, x5, x6",
316 ));
317 insns.push((
318 Inst::AluRRR {
319 alu_op: ALUOp::Asr32,
320 rd: writable_xreg(4),
321 rn: xreg(5),
322 rm: xreg(6),
323 },
324 "A428C61A",
325 "asr w4, w5, w6",
326 ));
327 insns.push((
328 Inst::AluRRR {
329 alu_op: ALUOp::Asr64,
330 rd: writable_xreg(4),
331 rn: xreg(5),
332 rm: xreg(6),
333 },
334 "A428C69A",
335 "asr x4, x5, x6",
336 ));
337 insns.push((
338 Inst::AluRRR {
339 alu_op: ALUOp::Lsl32,
340 rd: writable_xreg(4),
341 rn: xreg(5),
342 rm: xreg(6),
343 },
344 "A420C61A",
345 "lsl w4, w5, w6",
346 ));
347 insns.push((
348 Inst::AluRRR {
349 alu_op: ALUOp::Lsl64,
350 rd: writable_xreg(4),
351 rn: xreg(5),
352 rm: xreg(6),
353 },
354 "A420C69A",
355 "lsl x4, x5, x6",
356 ));
357
358 insns.push((
359 Inst::AluRRImm12 {
360 alu_op: ALUOp::Add32,
361 rd: writable_xreg(7),
362 rn: xreg(8),
363 imm12: Imm12 {
364 bits: 0x123,
365 shift12: false,
366 },
367 },
368 "078D0411",
369 "add w7, w8, #291",
370 ));
371 insns.push((
372 Inst::AluRRImm12 {
373 alu_op: ALUOp::Add32,
374 rd: writable_xreg(7),
375 rn: xreg(8),
376 imm12: Imm12 {
377 bits: 0x123,
378 shift12: true,
379 },
380 },
381 "078D4411",
382 "add w7, w8, #1191936",
383 ));
384 insns.push((
385 Inst::AluRRImm12 {
386 alu_op: ALUOp::Add64,
387 rd: writable_xreg(7),
388 rn: xreg(8),
389 imm12: Imm12 {
390 bits: 0x123,
391 shift12: false,
392 },
393 },
394 "078D0491",
395 "add x7, x8, #291",
396 ));
397 insns.push((
398 Inst::AluRRImm12 {
399 alu_op: ALUOp::Sub32,
400 rd: writable_xreg(7),
401 rn: xreg(8),
402 imm12: Imm12 {
403 bits: 0x123,
404 shift12: false,
405 },
406 },
407 "078D0451",
408 "sub w7, w8, #291",
409 ));
410 insns.push((
411 Inst::AluRRImm12 {
412 alu_op: ALUOp::Sub64,
413 rd: writable_xreg(7),
414 rn: xreg(8),
415 imm12: Imm12 {
416 bits: 0x123,
417 shift12: false,
418 },
419 },
420 "078D04D1",
421 "sub x7, x8, #291",
422 ));
423 insns.push((
424 Inst::AluRRImm12 {
425 alu_op: ALUOp::SubS32,
426 rd: writable_xreg(7),
427 rn: xreg(8),
428 imm12: Imm12 {
429 bits: 0x123,
430 shift12: false,
431 },
432 },
433 "078D0471",
434 "subs w7, w8, #291",
435 ));
436 insns.push((
437 Inst::AluRRImm12 {
438 alu_op: ALUOp::SubS64,
439 rd: writable_xreg(7),
440 rn: xreg(8),
441 imm12: Imm12 {
442 bits: 0x123,
443 shift12: false,
444 },
445 },
446 "078D04F1",
447 "subs x7, x8, #291",
448 ));
449
450 insns.push((
451 Inst::AluRRRExtend {
452 alu_op: ALUOp::Add32,
453 rd: writable_xreg(7),
454 rn: xreg(8),
455 rm: xreg(9),
456 extendop: ExtendOp::SXTB,
457 },
458 "0781290B",
459 "add w7, w8, w9, SXTB",
460 ));
461
462 insns.push((
463 Inst::AluRRRExtend {
464 alu_op: ALUOp::Add64,
465 rd: writable_xreg(15),
466 rn: xreg(16),
467 rm: xreg(17),
468 extendop: ExtendOp::UXTB,
469 },
470 "0F02318B",
471 "add x15, x16, x17, UXTB",
472 ));
473
474 insns.push((
475 Inst::AluRRRExtend {
476 alu_op: ALUOp::Sub32,
477 rd: writable_xreg(1),
478 rn: xreg(2),
479 rm: xreg(3),
480 extendop: ExtendOp::SXTH,
481 },
482 "41A0234B",
483 "sub w1, w2, w3, SXTH",
484 ));
485
486 insns.push((
487 Inst::AluRRRExtend {
488 alu_op: ALUOp::Sub64,
489 rd: writable_xreg(20),
490 rn: xreg(21),
491 rm: xreg(22),
492 extendop: ExtendOp::UXTW,
493 },
494 "B44236CB",
495 "sub x20, x21, x22, UXTW",
496 ));
497
498 insns.push((
499 Inst::AluRRRShift {
500 alu_op: ALUOp::Add32,
501 rd: writable_xreg(10),
502 rn: xreg(11),
503 rm: xreg(12),
504 shiftop: ShiftOpAndAmt::new(
505 ShiftOp::LSL,
506 ShiftOpShiftImm::maybe_from_shift(20).unwrap(),
507 ),
508 },
509 "6A510C0B",
510 "add w10, w11, w12, LSL 20",
511 ));
512 insns.push((
513 Inst::AluRRRShift {
514 alu_op: ALUOp::Add64,
515 rd: writable_xreg(10),
516 rn: xreg(11),
517 rm: xreg(12),
518 shiftop: ShiftOpAndAmt::new(
519 ShiftOp::ASR,
520 ShiftOpShiftImm::maybe_from_shift(42).unwrap(),
521 ),
522 },
523 "6AA98C8B",
524 "add x10, x11, x12, ASR 42",
525 ));
526 insns.push((
527 Inst::AluRRRShift {
528 alu_op: ALUOp::Sub32,
529 rd: writable_xreg(10),
530 rn: xreg(11),
531 rm: xreg(12),
532 shiftop: ShiftOpAndAmt::new(
533 ShiftOp::LSL,
534 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
535 ),
536 },
537 "6A5D0C4B",
538 "sub w10, w11, w12, LSL 23",
539 ));
540 insns.push((
541 Inst::AluRRRShift {
542 alu_op: ALUOp::Sub64,
543 rd: writable_xreg(10),
544 rn: xreg(11),
545 rm: xreg(12),
546 shiftop: ShiftOpAndAmt::new(
547 ShiftOp::LSL,
548 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
549 ),
550 },
551 "6A5D0CCB",
552 "sub x10, x11, x12, LSL 23",
553 ));
554 insns.push((
555 Inst::AluRRRShift {
556 alu_op: ALUOp::Orr32,
557 rd: writable_xreg(10),
558 rn: xreg(11),
559 rm: xreg(12),
560 shiftop: ShiftOpAndAmt::new(
561 ShiftOp::LSL,
562 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
563 ),
564 },
565 "6A5D0C2A",
566 "orr w10, w11, w12, LSL 23",
567 ));
568 insns.push((
569 Inst::AluRRRShift {
570 alu_op: ALUOp::Orr64,
571 rd: writable_xreg(10),
572 rn: xreg(11),
573 rm: xreg(12),
574 shiftop: ShiftOpAndAmt::new(
575 ShiftOp::LSL,
576 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
577 ),
578 },
579 "6A5D0CAA",
580 "orr x10, x11, x12, LSL 23",
581 ));
582 insns.push((
583 Inst::AluRRRShift {
584 alu_op: ALUOp::And32,
585 rd: writable_xreg(10),
586 rn: xreg(11),
587 rm: xreg(12),
588 shiftop: ShiftOpAndAmt::new(
589 ShiftOp::LSL,
590 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
591 ),
592 },
593 "6A5D0C0A",
594 "and w10, w11, w12, LSL 23",
595 ));
596 insns.push((
597 Inst::AluRRRShift {
598 alu_op: ALUOp::And64,
599 rd: writable_xreg(10),
600 rn: xreg(11),
601 rm: xreg(12),
602 shiftop: ShiftOpAndAmt::new(
603 ShiftOp::LSL,
604 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
605 ),
606 },
607 "6A5D0C8A",
608 "and x10, x11, x12, LSL 23",
609 ));
610 insns.push((
611 Inst::AluRRRShift {
612 alu_op: ALUOp::Eor32,
613 rd: writable_xreg(10),
614 rn: xreg(11),
615 rm: xreg(12),
616 shiftop: ShiftOpAndAmt::new(
617 ShiftOp::LSL,
618 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
619 ),
620 },
621 "6A5D0C4A",
622 "eor w10, w11, w12, LSL 23",
623 ));
624 insns.push((
625 Inst::AluRRRShift {
626 alu_op: ALUOp::Eor64,
627 rd: writable_xreg(10),
628 rn: xreg(11),
629 rm: xreg(12),
630 shiftop: ShiftOpAndAmt::new(
631 ShiftOp::LSL,
632 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
633 ),
634 },
635 "6A5D0CCA",
636 "eor x10, x11, x12, LSL 23",
637 ));
638 insns.push((
639 Inst::AluRRRShift {
640 alu_op: ALUOp::OrrNot32,
641 rd: writable_xreg(10),
642 rn: xreg(11),
643 rm: xreg(12),
644 shiftop: ShiftOpAndAmt::new(
645 ShiftOp::LSL,
646 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
647 ),
648 },
649 "6A5D2C2A",
650 "orn w10, w11, w12, LSL 23",
651 ));
652 insns.push((
653 Inst::AluRRRShift {
654 alu_op: ALUOp::OrrNot64,
655 rd: writable_xreg(10),
656 rn: xreg(11),
657 rm: xreg(12),
658 shiftop: ShiftOpAndAmt::new(
659 ShiftOp::LSL,
660 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
661 ),
662 },
663 "6A5D2CAA",
664 "orn x10, x11, x12, LSL 23",
665 ));
666 insns.push((
667 Inst::AluRRRShift {
668 alu_op: ALUOp::AndNot32,
669 rd: writable_xreg(10),
670 rn: xreg(11),
671 rm: xreg(12),
672 shiftop: ShiftOpAndAmt::new(
673 ShiftOp::LSL,
674 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
675 ),
676 },
677 "6A5D2C0A",
678 "bic w10, w11, w12, LSL 23",
679 ));
680 insns.push((
681 Inst::AluRRRShift {
682 alu_op: ALUOp::AndNot64,
683 rd: writable_xreg(10),
684 rn: xreg(11),
685 rm: xreg(12),
686 shiftop: ShiftOpAndAmt::new(
687 ShiftOp::LSL,
688 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
689 ),
690 },
691 "6A5D2C8A",
692 "bic x10, x11, x12, LSL 23",
693 ));
694 insns.push((
695 Inst::AluRRRShift {
696 alu_op: ALUOp::EorNot32,
697 rd: writable_xreg(10),
698 rn: xreg(11),
699 rm: xreg(12),
700 shiftop: ShiftOpAndAmt::new(
701 ShiftOp::LSL,
702 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
703 ),
704 },
705 "6A5D2C4A",
706 "eon w10, w11, w12, LSL 23",
707 ));
708 insns.push((
709 Inst::AluRRRShift {
710 alu_op: ALUOp::EorNot64,
711 rd: writable_xreg(10),
712 rn: xreg(11),
713 rm: xreg(12),
714 shiftop: ShiftOpAndAmt::new(
715 ShiftOp::LSL,
716 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
717 ),
718 },
719 "6A5D2CCA",
720 "eon x10, x11, x12, LSL 23",
721 ));
722 insns.push((
723 Inst::AluRRRShift {
724 alu_op: ALUOp::AddS32,
725 rd: writable_xreg(10),
726 rn: xreg(11),
727 rm: xreg(12),
728 shiftop: ShiftOpAndAmt::new(
729 ShiftOp::LSL,
730 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
731 ),
732 },
733 "6A5D0C2B",
734 "adds w10, w11, w12, LSL 23",
735 ));
736 insns.push((
737 Inst::AluRRRShift {
738 alu_op: ALUOp::AddS64,
739 rd: writable_xreg(10),
740 rn: xreg(11),
741 rm: xreg(12),
742 shiftop: ShiftOpAndAmt::new(
743 ShiftOp::LSL,
744 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
745 ),
746 },
747 "6A5D0CAB",
748 "adds x10, x11, x12, LSL 23",
749 ));
750 insns.push((
751 Inst::AluRRRShift {
752 alu_op: ALUOp::SubS32,
753 rd: writable_xreg(10),
754 rn: xreg(11),
755 rm: xreg(12),
756 shiftop: ShiftOpAndAmt::new(
757 ShiftOp::LSL,
758 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
759 ),
760 },
761 "6A5D0C6B",
762 "subs w10, w11, w12, LSL 23",
763 ));
764 insns.push((
765 Inst::AluRRRShift {
766 alu_op: ALUOp::SubS64,
767 rd: writable_xreg(10),
768 rn: xreg(11),
769 rm: xreg(12),
770 shiftop: ShiftOpAndAmt::new(
771 ShiftOp::LSL,
772 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
773 ),
774 },
775 "6A5D0CEB",
776 "subs x10, x11, x12, LSL 23",
777 ));
778
779 insns.push((
780 Inst::AluRRRExtend {
781 alu_op: ALUOp::SubS64,
782 rd: writable_zero_reg(),
783 rn: stack_reg(),
784 rm: xreg(12),
785 extendop: ExtendOp::UXTX,
786 },
787 "FF632CEB",
788 "subs xzr, sp, x12, UXTX",
789 ));
790
791 insns.push((
792 Inst::AluRRRR {
793 alu_op: ALUOp3::MAdd32,
794 rd: writable_xreg(1),
795 rn: xreg(2),
796 rm: xreg(3),
797 ra: xreg(4),
798 },
799 "4110031B",
800 "madd w1, w2, w3, w4",
801 ));
802 insns.push((
803 Inst::AluRRRR {
804 alu_op: ALUOp3::MAdd64,
805 rd: writable_xreg(1),
806 rn: xreg(2),
807 rm: xreg(3),
808 ra: xreg(4),
809 },
810 "4110039B",
811 "madd x1, x2, x3, x4",
812 ));
813 insns.push((
814 Inst::AluRRRR {
815 alu_op: ALUOp3::MSub32,
816 rd: writable_xreg(1),
817 rn: xreg(2),
818 rm: xreg(3),
819 ra: xreg(4),
820 },
821 "4190031B",
822 "msub w1, w2, w3, w4",
823 ));
824 insns.push((
825 Inst::AluRRRR {
826 alu_op: ALUOp3::MSub64,
827 rd: writable_xreg(1),
828 rn: xreg(2),
829 rm: xreg(3),
830 ra: xreg(4),
831 },
832 "4190039B",
833 "msub x1, x2, x3, x4",
834 ));
835 insns.push((
836 Inst::AluRRR {
837 alu_op: ALUOp::SMulH,
838 rd: writable_xreg(1),
839 rn: xreg(2),
840 rm: xreg(3),
841 },
842 "417C439B",
843 "smulh x1, x2, x3",
844 ));
845 insns.push((
846 Inst::AluRRR {
847 alu_op: ALUOp::UMulH,
848 rd: writable_xreg(1),
849 rn: xreg(2),
850 rm: xreg(3),
851 },
852 "417CC39B",
853 "umulh x1, x2, x3",
854 ));
855
856 insns.push((
857 Inst::AluRRImmShift {
858 alu_op: ALUOp::RotR32,
859 rd: writable_xreg(20),
860 rn: xreg(21),
861 immshift: ImmShift::maybe_from_u64(19).unwrap(),
862 },
863 "B44E9513",
864 "ror w20, w21, #19",
865 ));
866 insns.push((
867 Inst::AluRRImmShift {
868 alu_op: ALUOp::RotR64,
869 rd: writable_xreg(20),
870 rn: xreg(21),
871 immshift: ImmShift::maybe_from_u64(42).unwrap(),
872 },
873 "B4AAD593",
874 "ror x20, x21, #42",
875 ));
876 insns.push((
877 Inst::AluRRImmShift {
878 alu_op: ALUOp::Lsr32,
879 rd: writable_xreg(10),
880 rn: xreg(11),
881 immshift: ImmShift::maybe_from_u64(13).unwrap(),
882 },
883 "6A7D0D53",
884 "lsr w10, w11, #13",
885 ));
886 insns.push((
887 Inst::AluRRImmShift {
888 alu_op: ALUOp::Lsr64,
889 rd: writable_xreg(10),
890 rn: xreg(11),
891 immshift: ImmShift::maybe_from_u64(57).unwrap(),
892 },
893 "6AFD79D3",
894 "lsr x10, x11, #57",
895 ));
896 insns.push((
897 Inst::AluRRImmShift {
898 alu_op: ALUOp::Asr32,
899 rd: writable_xreg(4),
900 rn: xreg(5),
901 immshift: ImmShift::maybe_from_u64(7).unwrap(),
902 },
903 "A47C0713",
904 "asr w4, w5, #7",
905 ));
906 insns.push((
907 Inst::AluRRImmShift {
908 alu_op: ALUOp::Asr64,
909 rd: writable_xreg(4),
910 rn: xreg(5),
911 immshift: ImmShift::maybe_from_u64(35).unwrap(),
912 },
913 "A4FC6393",
914 "asr x4, x5, #35",
915 ));
916 insns.push((
917 Inst::AluRRImmShift {
918 alu_op: ALUOp::Lsl32,
919 rd: writable_xreg(8),
920 rn: xreg(9),
921 immshift: ImmShift::maybe_from_u64(24).unwrap(),
922 },
923 "281D0853",
924 "lsl w8, w9, #24",
925 ));
926 insns.push((
927 Inst::AluRRImmShift {
928 alu_op: ALUOp::Lsl64,
929 rd: writable_xreg(8),
930 rn: xreg(9),
931 immshift: ImmShift::maybe_from_u64(63).unwrap(),
932 },
933 "280141D3",
934 "lsl x8, x9, #63",
935 ));
936 insns.push((
937 Inst::AluRRImmShift {
938 alu_op: ALUOp::Lsl32,
939 rd: writable_xreg(10),
940 rn: xreg(11),
941 immshift: ImmShift::maybe_from_u64(0).unwrap(),
942 },
943 "6A7D0053",
944 "lsl w10, w11, #0",
945 ));
946 insns.push((
947 Inst::AluRRImmShift {
948 alu_op: ALUOp::Lsl64,
949 rd: writable_xreg(10),
950 rn: xreg(11),
951 immshift: ImmShift::maybe_from_u64(0).unwrap(),
952 },
953 "6AFD40D3",
954 "lsl x10, x11, #0",
955 ));
956
957 insns.push((
958 Inst::AluRRImmLogic {
959 alu_op: ALUOp::And32,
960 rd: writable_xreg(21),
961 rn: xreg(27),
962 imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
963 },
964 "753B0112",
965 "and w21, w27, #2147500031",
966 ));
967 insns.push((
968 Inst::AluRRImmLogic {
969 alu_op: ALUOp::And64,
970 rd: writable_xreg(7),
971 rn: xreg(6),
972 imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
973 },
974 "C7381592",
975 "and x7, x6, #288221580125796352",
976 ));
977 insns.push((
978 Inst::AluRRImmLogic {
979 alu_op: ALUOp::Orr32,
980 rd: writable_xreg(1),
981 rn: xreg(5),
982 imml: ImmLogic::maybe_from_u64(0x100000, I32).unwrap(),
983 },
984 "A1000C32",
985 "orr w1, w5, #1048576",
986 ));
987 insns.push((
988 Inst::AluRRImmLogic {
989 alu_op: ALUOp::Orr64,
990 rd: writable_xreg(4),
991 rn: xreg(5),
992 imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),
993 },
994 "A4C401B2",
995 "orr x4, x5, #9331882296111890817",
996 ));
997 insns.push((
998 Inst::AluRRImmLogic {
999 alu_op: ALUOp::Eor32,
1000 rd: writable_xreg(1),
1001 rn: xreg(5),
1002 imml: ImmLogic::maybe_from_u64(0x00007fff, I32).unwrap(),
1003 },
1004 "A1380052",
1005 "eor w1, w5, #32767",
1006 ));
1007 insns.push((
1008 Inst::AluRRImmLogic {
1009 alu_op: ALUOp::Eor64,
1010 rd: writable_xreg(10),
1011 rn: xreg(8),
1012 imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),
1013 },
1014 "0AC501D2",
1015 "eor x10, x8, #9331882296111890817",
1016 ));
1017
1018 insns.push((
1019 Inst::BitRR {
1020 op: BitOp::RBit32,
1021 rd: writable_xreg(1),
1022 rn: xreg(10),
1023 },
1024 "4101C05A",
1025 "rbit w1, w10",
1026 ));
1027
1028 insns.push((
1029 Inst::BitRR {
1030 op: BitOp::RBit64,
1031 rd: writable_xreg(1),
1032 rn: xreg(10),
1033 },
1034 "4101C0DA",
1035 "rbit x1, x10",
1036 ));
1037
1038 insns.push((
1039 Inst::BitRR {
1040 op: BitOp::Clz32,
1041 rd: writable_xreg(15),
1042 rn: xreg(3),
1043 },
1044 "6F10C05A",
1045 "clz w15, w3",
1046 ));
1047
1048 insns.push((
1049 Inst::BitRR {
1050 op: BitOp::Clz64,
1051 rd: writable_xreg(15),
1052 rn: xreg(3),
1053 },
1054 "6F10C0DA",
1055 "clz x15, x3",
1056 ));
1057
1058 insns.push((
1059 Inst::BitRR {
1060 op: BitOp::Cls32,
1061 rd: writable_xreg(21),
1062 rn: xreg(16),
1063 },
1064 "1516C05A",
1065 "cls w21, w16",
1066 ));
1067
1068 insns.push((
1069 Inst::BitRR {
1070 op: BitOp::Cls64,
1071 rd: writable_xreg(21),
1072 rn: xreg(16),
1073 },
1074 "1516C0DA",
1075 "cls x21, x16",
1076 ));
1077
1078 insns.push((
1079 Inst::ULoad8 {
1080 rd: writable_xreg(1),
1081 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1082 flags: MemFlags::trusted(),
1083 },
1084 "41004038",
1085 "ldurb w1, [x2]",
1086 ));
1087 insns.push((
1088 Inst::ULoad8 {
1089 rd: writable_xreg(1),
1090 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::zero(I8)),
1091 flags: MemFlags::trusted(),
1092 },
1093 "41004039",
1094 "ldrb w1, [x2]",
1095 ));
1096 insns.push((
1097 Inst::ULoad8 {
1098 rd: writable_xreg(1),
1099 mem: AMode::RegReg(xreg(2), xreg(5)),
1100 flags: MemFlags::trusted(),
1101 },
1102 "41686538",
1103 "ldrb w1, [x2, x5]",
1104 ));
1105 insns.push((
1106 Inst::SLoad8 {
1107 rd: writable_xreg(1),
1108 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1109 flags: MemFlags::trusted(),
1110 },
1111 "41008038",
1112 "ldursb x1, [x2]",
1113 ));
1114 insns.push((
1115 Inst::SLoad8 {
1116 rd: writable_xreg(1),
1117 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(63, I8).unwrap()),
1118 flags: MemFlags::trusted(),
1119 },
1120 "41FC8039",
1121 "ldrsb x1, [x2, #63]",
1122 ));
1123 insns.push((
1124 Inst::SLoad8 {
1125 rd: writable_xreg(1),
1126 mem: AMode::RegReg(xreg(2), xreg(5)),
1127 flags: MemFlags::trusted(),
1128 },
1129 "4168A538",
1130 "ldrsb x1, [x2, x5]",
1131 ));
1132 insns.push((
1133 Inst::ULoad16 {
1134 rd: writable_xreg(1),
1135 mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(5).unwrap()),
1136 flags: MemFlags::trusted(),
1137 },
1138 "41504078",
1139 "ldurh w1, [x2, #5]",
1140 ));
1141 insns.push((
1142 Inst::ULoad16 {
1143 rd: writable_xreg(1),
1144 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(8, I16).unwrap()),
1145 flags: MemFlags::trusted(),
1146 },
1147 "41104079",
1148 "ldrh w1, [x2, #8]",
1149 ));
1150 insns.push((
1151 Inst::ULoad16 {
1152 rd: writable_xreg(1),
1153 mem: AMode::RegScaled(xreg(2), xreg(3), I16),
1154 flags: MemFlags::trusted(),
1155 },
1156 "41786378",
1157 "ldrh w1, [x2, x3, LSL #1]",
1158 ));
1159 insns.push((
1160 Inst::SLoad16 {
1161 rd: writable_xreg(1),
1162 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1163 flags: MemFlags::trusted(),
1164 },
1165 "41008078",
1166 "ldursh x1, [x2]",
1167 ));
1168 insns.push((
1169 Inst::SLoad16 {
1170 rd: writable_xreg(28),
1171 mem: AMode::UnsignedOffset(xreg(20), UImm12Scaled::maybe_from_i64(24, I16).unwrap()),
1172 flags: MemFlags::trusted(),
1173 },
1174 "9C328079",
1175 "ldrsh x28, [x20, #24]",
1176 ));
1177 insns.push((
1178 Inst::SLoad16 {
1179 rd: writable_xreg(28),
1180 mem: AMode::RegScaled(xreg(20), xreg(20), I16),
1181 flags: MemFlags::trusted(),
1182 },
1183 "9C7AB478",
1184 "ldrsh x28, [x20, x20, LSL #1]",
1185 ));
1186 insns.push((
1187 Inst::ULoad32 {
1188 rd: writable_xreg(1),
1189 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1190 flags: MemFlags::trusted(),
1191 },
1192 "410040B8",
1193 "ldur w1, [x2]",
1194 ));
1195 insns.push((
1196 Inst::ULoad32 {
1197 rd: writable_xreg(12),
1198 mem: AMode::UnsignedOffset(xreg(0), UImm12Scaled::maybe_from_i64(204, I32).unwrap()),
1199 flags: MemFlags::trusted(),
1200 },
1201 "0CCC40B9",
1202 "ldr w12, [x0, #204]",
1203 ));
1204 insns.push((
1205 Inst::ULoad32 {
1206 rd: writable_xreg(1),
1207 mem: AMode::RegScaled(xreg(2), xreg(12), I32),
1208 flags: MemFlags::trusted(),
1209 },
1210 "41786CB8",
1211 "ldr w1, [x2, x12, LSL #2]",
1212 ));
1213 insns.push((
1214 Inst::SLoad32 {
1215 rd: writable_xreg(1),
1216 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1217 flags: MemFlags::trusted(),
1218 },
1219 "410080B8",
1220 "ldursw x1, [x2]",
1221 ));
1222 insns.push((
1223 Inst::SLoad32 {
1224 rd: writable_xreg(12),
1225 mem: AMode::UnsignedOffset(xreg(1), UImm12Scaled::maybe_from_i64(16380, I32).unwrap()),
1226 flags: MemFlags::trusted(),
1227 },
1228 "2CFCBFB9",
1229 "ldrsw x12, [x1, #16380]",
1230 ));
1231 insns.push((
1232 Inst::SLoad32 {
1233 rd: writable_xreg(1),
1234 mem: AMode::RegScaled(xreg(5), xreg(1), I32),
1235 flags: MemFlags::trusted(),
1236 },
1237 "A178A1B8",
1238 "ldrsw x1, [x5, x1, LSL #2]",
1239 ));
1240 insns.push((
1241 Inst::ULoad64 {
1242 rd: writable_xreg(1),
1243 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1244 flags: MemFlags::trusted(),
1245 },
1246 "410040F8",
1247 "ldur x1, [x2]",
1248 ));
1249 insns.push((
1250 Inst::ULoad64 {
1251 rd: writable_xreg(1),
1252 mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(-256).unwrap()),
1253 flags: MemFlags::trusted(),
1254 },
1255 "410050F8",
1256 "ldur x1, [x2, #-256]",
1257 ));
1258 insns.push((
1259 Inst::ULoad64 {
1260 rd: writable_xreg(1),
1261 mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(255).unwrap()),
1262 flags: MemFlags::trusted(),
1263 },
1264 "41F04FF8",
1265 "ldur x1, [x2, #255]",
1266 ));
1267 insns.push((
1268 Inst::ULoad64 {
1269 rd: writable_xreg(1),
1270 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(32760, I64).unwrap()),
1271 flags: MemFlags::trusted(),
1272 },
1273 "41FC7FF9",
1274 "ldr x1, [x2, #32760]",
1275 ));
1276 insns.push((
1277 Inst::ULoad64 {
1278 rd: writable_xreg(1),
1279 mem: AMode::RegReg(xreg(2), xreg(3)),
1280 flags: MemFlags::trusted(),
1281 },
1282 "416863F8",
1283 "ldr x1, [x2, x3]",
1284 ));
1285 insns.push((
1286 Inst::ULoad64 {
1287 rd: writable_xreg(1),
1288 mem: AMode::RegScaled(xreg(2), xreg(3), I64),
1289 flags: MemFlags::trusted(),
1290 },
1291 "417863F8",
1292 "ldr x1, [x2, x3, LSL #3]",
1293 ));
1294 insns.push((
1295 Inst::ULoad64 {
1296 rd: writable_xreg(1),
1297 mem: AMode::RegScaledExtended(xreg(2), xreg(3), I64, ExtendOp::SXTW),
1298 flags: MemFlags::trusted(),
1299 },
1300 "41D863F8",
1301 "ldr x1, [x2, w3, SXTW #3]",
1302 ));
1303 insns.push((
1304 Inst::ULoad64 {
1305 rd: writable_xreg(1),
1306 mem: AMode::RegExtended(xreg(2), xreg(3), ExtendOp::SXTW),
1307 flags: MemFlags::trusted(),
1308 },
1309 "41C863F8",
1310 "ldr x1, [x2, w3, SXTW]",
1311 ));
1312 insns.push((
1313 Inst::ULoad64 {
1314 rd: writable_xreg(1),
1315 mem: AMode::Label(MemLabel::PCRel(64)),
1316 flags: MemFlags::trusted(),
1317 },
1318 "01020058",
1319 "ldr x1, pc+64",
1320 ));
1321 insns.push((
1322 Inst::ULoad64 {
1323 rd: writable_xreg(1),
1324 mem: AMode::PreIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
1325 flags: MemFlags::trusted(),
1326 },
1327 "410C41F8",
1328 "ldr x1, [x2, #16]!",
1329 ));
1330 insns.push((
1331 Inst::ULoad64 {
1332 rd: writable_xreg(1),
1333 mem: AMode::PostIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
1334 flags: MemFlags::trusted(),
1335 },
1336 "410441F8",
1337 "ldr x1, [x2], #16",
1338 ));
1339 insns.push((
1340 Inst::ULoad64 {
1341 rd: writable_xreg(1),
1342 mem: AMode::FPOffset(32768, I8),
1343 flags: MemFlags::trusted(),
1344 },
1345 "100090D2B063308B010240F9",
1346 "movz x16, #32768 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
1347 ));
1348 insns.push((
1349 Inst::ULoad64 {
1350 rd: writable_xreg(1),
1351 mem: AMode::FPOffset(-32768, I8),
1352 flags: MemFlags::trusted(),
1353 },
1354 "F0FF8F92B063308B010240F9",
1355 "movn x16, #32767 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
1356 ));
1357 insns.push((
1358 Inst::ULoad64 {
1359 rd: writable_xreg(1),
1360 mem: AMode::FPOffset(1048576, I8), // 2^20
1361 flags: MemFlags::trusted(),
1362 },
1363 "1002A0D2B063308B010240F9",
1364 "movz x16, #16, LSL #16 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
1365 ));
1366 insns.push((
1367 Inst::ULoad64 {
1368 rd: writable_xreg(1),
1369 mem: AMode::FPOffset(1048576 + 1, I8), // 2^20 + 1
1370 flags: MemFlags::trusted(),
1371 },
1372 "300080521002A072B063308B010240F9",
1373 "movz w16, #1 ; movk w16, #16, LSL #16 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
1374 ));
1375
1376 insns.push((
1377 Inst::ULoad64 {
1378 rd: writable_xreg(1),
1379 mem: AMode::RegOffset(xreg(7), 8, I64),
1380 flags: MemFlags::trusted(),
1381 },
1382 "E18040F8",
1383 "ldur x1, [x7, #8]",
1384 ));
1385
1386 insns.push((
1387 Inst::ULoad64 {
1388 rd: writable_xreg(1),
1389 mem: AMode::RegOffset(xreg(7), 1024, I64),
1390 flags: MemFlags::trusted(),
1391 },
1392 "E10042F9",
1393 "ldr x1, [x7, #1024]",
1394 ));
1395
1396 insns.push((
1397 Inst::ULoad64 {
1398 rd: writable_xreg(1),
1399 mem: AMode::RegOffset(xreg(7), 1048576, I64),
1400 flags: MemFlags::trusted(),
1401 },
1402 "1002A0D2F060308B010240F9",
1403 "movz x16, #16, LSL #16 ; add x16, x7, x16, UXTX ; ldr x1, [x16]",
1404 ));
1405
1406 insns.push((
1407 Inst::Store8 {
1408 rd: xreg(1),
1409 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1410 flags: MemFlags::trusted(),
1411 },
1412 "41000038",
1413 "sturb w1, [x2]",
1414 ));
1415 insns.push((
1416 Inst::Store8 {
1417 rd: xreg(1),
1418 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(4095, I8).unwrap()),
1419 flags: MemFlags::trusted(),
1420 },
1421 "41FC3F39",
1422 "strb w1, [x2, #4095]",
1423 ));
1424 insns.push((
1425 Inst::Store16 {
1426 rd: xreg(1),
1427 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1428 flags: MemFlags::trusted(),
1429 },
1430 "41000078",
1431 "sturh w1, [x2]",
1432 ));
1433 insns.push((
1434 Inst::Store16 {
1435 rd: xreg(1),
1436 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(8190, I16).unwrap()),
1437 flags: MemFlags::trusted(),
1438 },
1439 "41FC3F79",
1440 "strh w1, [x2, #8190]",
1441 ));
1442 insns.push((
1443 Inst::Store32 {
1444 rd: xreg(1),
1445 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1446 flags: MemFlags::trusted(),
1447 },
1448 "410000B8",
1449 "stur w1, [x2]",
1450 ));
1451 insns.push((
1452 Inst::Store32 {
1453 rd: xreg(1),
1454 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(16380, I32).unwrap()),
1455 flags: MemFlags::trusted(),
1456 },
1457 "41FC3FB9",
1458 "str w1, [x2, #16380]",
1459 ));
1460 insns.push((
1461 Inst::Store64 {
1462 rd: xreg(1),
1463 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1464 flags: MemFlags::trusted(),
1465 },
1466 "410000F8",
1467 "stur x1, [x2]",
1468 ));
1469 insns.push((
1470 Inst::Store64 {
1471 rd: xreg(1),
1472 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(32760, I64).unwrap()),
1473 flags: MemFlags::trusted(),
1474 },
1475 "41FC3FF9",
1476 "str x1, [x2, #32760]",
1477 ));
1478 insns.push((
1479 Inst::Store64 {
1480 rd: xreg(1),
1481 mem: AMode::RegReg(xreg(2), xreg(3)),
1482 flags: MemFlags::trusted(),
1483 },
1484 "416823F8",
1485 "str x1, [x2, x3]",
1486 ));
1487 insns.push((
1488 Inst::Store64 {
1489 rd: xreg(1),
1490 mem: AMode::RegScaled(xreg(2), xreg(3), I64),
1491 flags: MemFlags::trusted(),
1492 },
1493 "417823F8",
1494 "str x1, [x2, x3, LSL #3]",
1495 ));
1496 insns.push((
1497 Inst::Store64 {
1498 rd: xreg(1),
1499 mem: AMode::RegScaledExtended(xreg(2), xreg(3), I64, ExtendOp::UXTW),
1500 flags: MemFlags::trusted(),
1501 },
1502 "415823F8",
1503 "str x1, [x2, w3, UXTW #3]",
1504 ));
1505 insns.push((
1506 Inst::Store64 {
1507 rd: xreg(1),
1508 mem: AMode::RegExtended(xreg(2), xreg(3), ExtendOp::UXTW),
1509 flags: MemFlags::trusted(),
1510 },
1511 "414823F8",
1512 "str x1, [x2, w3, UXTW]",
1513 ));
1514 insns.push((
1515 Inst::Store64 {
1516 rd: xreg(1),
1517 mem: AMode::PreIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
1518 flags: MemFlags::trusted(),
1519 },
1520 "410C01F8",
1521 "str x1, [x2, #16]!",
1522 ));
1523 insns.push((
1524 Inst::Store64 {
1525 rd: xreg(1),
1526 mem: AMode::PostIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
1527 flags: MemFlags::trusted(),
1528 },
1529 "410401F8",
1530 "str x1, [x2], #16",
1531 ));
1532
1533 insns.push((
1534 Inst::StoreP64 {
1535 rt: xreg(8),
1536 rt2: xreg(9),
1537 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::zero(I64)),
1538 flags: MemFlags::trusted(),
1539 },
1540 "482500A9",
1541 "stp x8, x9, [x10]",
1542 ));
1543 insns.push((
1544 Inst::StoreP64 {
1545 rt: xreg(8),
1546 rt2: xreg(9),
1547 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(504, I64).unwrap()),
1548 flags: MemFlags::trusted(),
1549 },
1550 "48A51FA9",
1551 "stp x8, x9, [x10, #504]",
1552 ));
1553 insns.push((
1554 Inst::StoreP64 {
1555 rt: xreg(8),
1556 rt2: xreg(9),
1557 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(-64, I64).unwrap()),
1558 flags: MemFlags::trusted(),
1559 },
1560 "48253CA9",
1561 "stp x8, x9, [x10, #-64]",
1562 ));
1563 insns.push((
1564 Inst::StoreP64 {
1565 rt: xreg(21),
1566 rt2: xreg(28),
1567 mem: PairAMode::SignedOffset(xreg(1), SImm7Scaled::maybe_from_i64(-512, I64).unwrap()),
1568 flags: MemFlags::trusted(),
1569 },
1570 "357020A9",
1571 "stp x21, x28, [x1, #-512]",
1572 ));
1573 insns.push((
1574 Inst::StoreP64 {
1575 rt: xreg(8),
1576 rt2: xreg(9),
1577 mem: PairAMode::PreIndexed(
1578 writable_xreg(10),
1579 SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
1580 ),
1581 flags: MemFlags::trusted(),
1582 },
1583 "4825BCA9",
1584 "stp x8, x9, [x10, #-64]!",
1585 ));
1586 insns.push((
1587 Inst::StoreP64 {
1588 rt: xreg(15),
1589 rt2: xreg(16),
1590 mem: PairAMode::PostIndexed(
1591 writable_xreg(20),
1592 SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
1593 ),
1594 flags: MemFlags::trusted(),
1595 },
1596 "8FC29FA8",
1597 "stp x15, x16, [x20], #504",
1598 ));
1599
1600 insns.push((
1601 Inst::LoadP64 {
1602 rt: writable_xreg(8),
1603 rt2: writable_xreg(9),
1604 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::zero(I64)),
1605 flags: MemFlags::trusted(),
1606 },
1607 "482540A9",
1608 "ldp x8, x9, [x10]",
1609 ));
1610 insns.push((
1611 Inst::LoadP64 {
1612 rt: writable_xreg(8),
1613 rt2: writable_xreg(9),
1614 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(504, I64).unwrap()),
1615 flags: MemFlags::trusted(),
1616 },
1617 "48A55FA9",
1618 "ldp x8, x9, [x10, #504]",
1619 ));
1620 insns.push((
1621 Inst::LoadP64 {
1622 rt: writable_xreg(8),
1623 rt2: writable_xreg(9),
1624 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(-64, I64).unwrap()),
1625 flags: MemFlags::trusted(),
1626 },
1627 "48257CA9",
1628 "ldp x8, x9, [x10, #-64]",
1629 ));
1630 insns.push((
1631 Inst::LoadP64 {
1632 rt: writable_xreg(8),
1633 rt2: writable_xreg(9),
1634 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(-512, I64).unwrap()),
1635 flags: MemFlags::trusted(),
1636 },
1637 "482560A9",
1638 "ldp x8, x9, [x10, #-512]",
1639 ));
1640 insns.push((
1641 Inst::LoadP64 {
1642 rt: writable_xreg(8),
1643 rt2: writable_xreg(9),
1644 mem: PairAMode::PreIndexed(
1645 writable_xreg(10),
1646 SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
1647 ),
1648 flags: MemFlags::trusted(),
1649 },
1650 "4825FCA9",
1651 "ldp x8, x9, [x10, #-64]!",
1652 ));
1653 insns.push((
1654 Inst::LoadP64 {
1655 rt: writable_xreg(8),
1656 rt2: writable_xreg(25),
1657 mem: PairAMode::PostIndexed(
1658 writable_xreg(12),
1659 SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
1660 ),
1661 flags: MemFlags::trusted(),
1662 },
1663 "88E5DFA8",
1664 "ldp x8, x25, [x12], #504",
1665 ));
1666
1667 insns.push((
1668 Inst::Mov64 {
1669 rd: writable_xreg(8),
1670 rm: xreg(9),
1671 },
1672 "E80309AA",
1673 "mov x8, x9",
1674 ));
1675 insns.push((
1676 Inst::Mov32 {
1677 rd: writable_xreg(8),
1678 rm: xreg(9),
1679 },
1680 "E803092A",
1681 "mov w8, w9",
1682 ));
1683
1684 insns.push((
1685 Inst::MovZ {
1686 rd: writable_xreg(8),
1687 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
1688 size: OperandSize::Size64,
1689 },
1690 "E8FF9FD2",
1691 "movz x8, #65535",
1692 ));
1693 insns.push((
1694 Inst::MovZ {
1695 rd: writable_xreg(8),
1696 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
1697 size: OperandSize::Size64,
1698 },
1699 "E8FFBFD2",
1700 "movz x8, #65535, LSL #16",
1701 ));
1702 insns.push((
1703 Inst::MovZ {
1704 rd: writable_xreg(8),
1705 imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
1706 size: OperandSize::Size64,
1707 },
1708 "E8FFDFD2",
1709 "movz x8, #65535, LSL #32",
1710 ));
1711 insns.push((
1712 Inst::MovZ {
1713 rd: writable_xreg(8),
1714 imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
1715 size: OperandSize::Size64,
1716 },
1717 "E8FFFFD2",
1718 "movz x8, #65535, LSL #48",
1719 ));
1720 insns.push((
1721 Inst::MovZ {
1722 rd: writable_xreg(8),
1723 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
1724 size: OperandSize::Size32,
1725 },
1726 "E8FFBF52",
1727 "movz w8, #65535, LSL #16",
1728 ));
1729
1730 insns.push((
1731 Inst::MovN {
1732 rd: writable_xreg(8),
1733 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
1734 size: OperandSize::Size64,
1735 },
1736 "E8FF9F92",
1737 "movn x8, #65535",
1738 ));
1739 insns.push((
1740 Inst::MovN {
1741 rd: writable_xreg(8),
1742 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
1743 size: OperandSize::Size64,
1744 },
1745 "E8FFBF92",
1746 "movn x8, #65535, LSL #16",
1747 ));
1748 insns.push((
1749 Inst::MovN {
1750 rd: writable_xreg(8),
1751 imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
1752 size: OperandSize::Size64,
1753 },
1754 "E8FFDF92",
1755 "movn x8, #65535, LSL #32",
1756 ));
1757 insns.push((
1758 Inst::MovN {
1759 rd: writable_xreg(8),
1760 imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
1761 size: OperandSize::Size64,
1762 },
1763 "E8FFFF92",
1764 "movn x8, #65535, LSL #48",
1765 ));
1766 insns.push((
1767 Inst::MovN {
1768 rd: writable_xreg(8),
1769 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
1770 size: OperandSize::Size32,
1771 },
1772 "E8FF9F12",
1773 "movn w8, #65535",
1774 ));
1775
1776 insns.push((
1777 Inst::MovK {
1778 rd: writable_xreg(12),
1779 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_0000).unwrap(),
1780 size: OperandSize::Size64,
1781 },
1782 "0C0080F2",
1783 "movk x12, #0",
1784 ));
1785 insns.push((
1786 Inst::MovK {
1787 rd: writable_xreg(19),
1788 imm: MoveWideConst::maybe_with_shift(0x0000, 16).unwrap(),
1789 size: OperandSize::Size64,
1790 },
1791 "1300A0F2",
1792 "movk x19, #0, LSL #16",
1793 ));
1794 insns.push((
1795 Inst::MovK {
1796 rd: writable_xreg(3),
1797 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
1798 size: OperandSize::Size64,
1799 },
1800 "E3FF9FF2",
1801 "movk x3, #65535",
1802 ));
1803 insns.push((
1804 Inst::MovK {
1805 rd: writable_xreg(8),
1806 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
1807 size: OperandSize::Size64,
1808 },
1809 "E8FFBFF2",
1810 "movk x8, #65535, LSL #16",
1811 ));
1812 insns.push((
1813 Inst::MovK {
1814 rd: writable_xreg(8),
1815 imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
1816 size: OperandSize::Size64,
1817 },
1818 "E8FFDFF2",
1819 "movk x8, #65535, LSL #32",
1820 ));
1821 insns.push((
1822 Inst::MovK {
1823 rd: writable_xreg(8),
1824 imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
1825 size: OperandSize::Size64,
1826 },
1827 "E8FFFFF2",
1828 "movk x8, #65535, LSL #48",
1829 ));
1830
1831 insns.push((
1832 Inst::CSel {
1833 rd: writable_xreg(10),
1834 rn: xreg(12),
1835 rm: xreg(14),
1836 cond: Cond::Hs,
1837 },
1838 "8A218E9A",
1839 "csel x10, x12, x14, hs",
1840 ));
1841 insns.push((
1842 Inst::CSet {
1843 rd: writable_xreg(15),
1844 cond: Cond::Ge,
1845 },
1846 "EFB79F9A",
1847 "cset x15, ge",
1848 ));
1849 insns.push((
1850 Inst::CSetm {
1851 rd: writable_xreg(0),
1852 cond: Cond::Eq,
1853 },
1854 "E0139FDA",
1855 "csetm x0, eq",
1856 ));
1857 insns.push((
1858 Inst::CSetm {
1859 rd: writable_xreg(16),
1860 cond: Cond::Vs,
1861 },
1862 "F0739FDA",
1863 "csetm x16, vs",
1864 ));
1865 insns.push((
1866 Inst::CCmpImm {
1867 size: OperandSize::Size64,
1868 rn: xreg(22),
1869 imm: UImm5::maybe_from_u8(5).unwrap(),
1870 nzcv: NZCV::new(false, false, true, true),
1871 cond: Cond::Eq,
1872 },
1873 "C30A45FA",
1874 "ccmp x22, #5, #nzCV, eq",
1875 ));
1876 insns.push((
1877 Inst::CCmpImm {
1878 size: OperandSize::Size32,
1879 rn: xreg(3),
1880 imm: UImm5::maybe_from_u8(30).unwrap(),
1881 nzcv: NZCV::new(true, true, true, true),
1882 cond: Cond::Gt,
1883 },
1884 "6FC85E7A",
1885 "ccmp w3, #30, #NZCV, gt",
1886 ));
1887 insns.push((
1888 Inst::MovToFpu {
1889 rd: writable_vreg(31),
1890 rn: xreg(0),
1891 size: ScalarSize::Size64,
1892 },
1893 "1F00679E",
1894 "fmov d31, x0",
1895 ));
1896 insns.push((
1897 Inst::MovToFpu {
1898 rd: writable_vreg(1),
1899 rn: xreg(28),
1900 size: ScalarSize::Size32,
1901 },
1902 "8103271E",
1903 "fmov s1, w28",
1904 ));
1905 insns.push((
1906 Inst::MovToVec {
1907 rd: writable_vreg(0),
1908 rn: xreg(0),
1909 idx: 7,
1910 size: VectorSize::Size8x8,
1911 },
1912 "001C0F4E",
1913 "mov v0.b[7], w0",
1914 ));
1915 insns.push((
1916 Inst::MovToVec {
1917 rd: writable_vreg(20),
1918 rn: xreg(21),
1919 idx: 0,
1920 size: VectorSize::Size64x2,
1921 },
1922 "B41E084E",
1923 "mov v20.d[0], x21",
1924 ));
1925 insns.push((
1926 Inst::MovFromVec {
1927 rd: writable_xreg(3),
1928 rn: vreg(27),
1929 idx: 14,
1930 size: VectorSize::Size8x16,
1931 },
1932 "633F1D0E",
1933 "umov w3, v27.b[14]",
1934 ));
1935 insns.push((
1936 Inst::MovFromVec {
1937 rd: writable_xreg(24),
1938 rn: vreg(5),
1939 idx: 3,
1940 size: VectorSize::Size16x8,
1941 },
1942 "B83C0E0E",
1943 "umov w24, v5.h[3]",
1944 ));
1945 insns.push((
1946 Inst::MovFromVec {
1947 rd: writable_xreg(12),
1948 rn: vreg(17),
1949 idx: 1,
1950 size: VectorSize::Size32x4,
1951 },
1952 "2C3E0C0E",
1953 "mov w12, v17.s[1]",
1954 ));
1955 insns.push((
1956 Inst::MovFromVec {
1957 rd: writable_xreg(21),
1958 rn: vreg(20),
1959 idx: 0,
1960 size: VectorSize::Size64x2,
1961 },
1962 "953E084E",
1963 "mov x21, v20.d[0]",
1964 ));
1965 insns.push((
1966 Inst::MovFromVecSigned {
1967 rd: writable_xreg(0),
1968 rn: vreg(0),
1969 idx: 15,
1970 size: VectorSize::Size8x16,
1971 scalar_size: OperandSize::Size32,
1972 },
1973 "002C1F0E",
1974 "smov w0, v0.b[15]",
1975 ));
1976 insns.push((
1977 Inst::MovFromVecSigned {
1978 rd: writable_xreg(12),
1979 rn: vreg(13),
1980 idx: 7,
1981 size: VectorSize::Size8x8,
1982 scalar_size: OperandSize::Size64,
1983 },
1984 "AC2D0F4E",
1985 "smov x12, v13.b[7]",
1986 ));
1987 insns.push((
1988 Inst::MovFromVecSigned {
1989 rd: writable_xreg(23),
1990 rn: vreg(31),
1991 idx: 7,
1992 size: VectorSize::Size16x8,
1993 scalar_size: OperandSize::Size32,
1994 },
1995 "F72F1E0E",
1996 "smov w23, v31.h[7]",
1997 ));
1998 insns.push((
1999 Inst::MovFromVecSigned {
2000 rd: writable_xreg(24),
2001 rn: vreg(5),
2002 idx: 1,
2003 size: VectorSize::Size32x2,
2004 scalar_size: OperandSize::Size64,
2005 },
2006 "B82C0C4E",
2007 "smov x24, v5.s[1]",
2008 ));
2009 insns.push((
2010 Inst::MovToNZCV { rn: xreg(13) },
2011 "0D421BD5",
2012 "msr nzcv, x13",
2013 ));
2014 insns.push((
2015 Inst::MovFromNZCV {
2016 rd: writable_xreg(27),
2017 },
2018 "1B423BD5",
2019 "mrs x27, nzcv",
2020 ));
2021 insns.push((
2022 Inst::VecDup {
2023 rd: writable_vreg(25),
2024 rn: xreg(7),
2025 size: VectorSize::Size8x16,
2026 },
2027 "F90C014E",
2028 "dup v25.16b, w7",
2029 ));
2030 insns.push((
2031 Inst::VecDup {
2032 rd: writable_vreg(2),
2033 rn: xreg(23),
2034 size: VectorSize::Size16x8,
2035 },
2036 "E20E024E",
2037 "dup v2.8h, w23",
2038 ));
2039 insns.push((
2040 Inst::VecDup {
2041 rd: writable_vreg(0),
2042 rn: xreg(28),
2043 size: VectorSize::Size32x4,
2044 },
2045 "800F044E",
2046 "dup v0.4s, w28",
2047 ));
2048 insns.push((
2049 Inst::VecDup {
2050 rd: writable_vreg(31),
2051 rn: xreg(5),
2052 size: VectorSize::Size64x2,
2053 },
2054 "BF0C084E",
2055 "dup v31.2d, x5",
2056 ));
2057 insns.push((
2058 Inst::VecDupFromFpu {
2059 rd: writable_vreg(14),
2060 rn: vreg(19),
2061 size: VectorSize::Size32x4,
2062 },
2063 "6E06044E",
2064 "dup v14.4s, v19.s[0]",
2065 ));
2066 insns.push((
2067 Inst::VecDupFromFpu {
2068 rd: writable_vreg(18),
2069 rn: vreg(10),
2070 size: VectorSize::Size64x2,
2071 },
2072 "5205084E",
2073 "dup v18.2d, v10.d[0]",
2074 ));
2075 insns.push((
2076 Inst::VecDupFPImm {
2077 rd: writable_vreg(31),
2078 imm: ASIMDFPModImm::maybe_from_u64(1_f32.to_bits() as u64, ScalarSize::Size32).unwrap(),
2079 size: VectorSize::Size32x2,
2080 },
2081 "1FF6030F",
2082 "fmov v31.2s, #1",
2083 ));
2084 insns.push((
2085 Inst::VecDupFPImm {
2086 rd: writable_vreg(0),
2087 imm: ASIMDFPModImm::maybe_from_u64(2_f64.to_bits(), ScalarSize::Size64).unwrap(),
2088 size: VectorSize::Size64x2,
2089 },
2090 "00F4006F",
2091 "fmov v0.2d, #2",
2092 ));
2093 insns.push((
2094 Inst::VecDupImm {
2095 rd: writable_vreg(31),
2096 imm: ASIMDMovModImm::maybe_from_u64(255, ScalarSize::Size8).unwrap(),
2097 invert: false,
2098 size: VectorSize::Size8x16,
2099 },
2100 "FFE7074F",
2101 "movi v31.16b, #255",
2102 ));
2103 insns.push((
2104 Inst::VecDupImm {
2105 rd: writable_vreg(30),
2106 imm: ASIMDMovModImm::maybe_from_u64(0, ScalarSize::Size16).unwrap(),
2107 invert: false,
2108 size: VectorSize::Size16x8,
2109 },
2110 "1E84004F",
2111 "movi v30.8h, #0",
2112 ));
2113 insns.push((
2114 Inst::VecDupImm {
2115 rd: writable_vreg(0),
2116 imm: ASIMDMovModImm::zero(ScalarSize::Size16),
2117 invert: true,
2118 size: VectorSize::Size16x4,
2119 },
2120 "0084002F",
2121 "mvni v0.4h, #0",
2122 ));
2123 insns.push((
2124 Inst::VecDupImm {
2125 rd: writable_vreg(0),
2126 imm: ASIMDMovModImm::maybe_from_u64(256, ScalarSize::Size16).unwrap(),
2127 invert: false,
2128 size: VectorSize::Size16x8,
2129 },
2130 "20A4004F",
2131 "movi v0.8h, #1, LSL #8",
2132 ));
2133 insns.push((
2134 Inst::VecDupImm {
2135 rd: writable_vreg(8),
2136 imm: ASIMDMovModImm::maybe_from_u64(2228223, ScalarSize::Size32).unwrap(),
2137 invert: false,
2138 size: VectorSize::Size32x4,
2139 },
2140 "28D4014F",
2141 "movi v8.4s, #33, MSL #16",
2142 ));
2143 insns.push((
2144 Inst::VecDupImm {
2145 rd: writable_vreg(16),
2146 imm: ASIMDMovModImm::maybe_from_u64(35071, ScalarSize::Size32).unwrap(),
2147 invert: true,
2148 size: VectorSize::Size32x2,
2149 },
2150 "10C5042F",
2151 "mvni v16.2s, #136, MSL #8",
2152 ));
2153 insns.push((
2154 Inst::VecDupImm {
2155 rd: writable_vreg(1),
2156 imm: ASIMDMovModImm::maybe_from_u64(0, ScalarSize::Size32).unwrap(),
2157 invert: false,
2158 size: VectorSize::Size32x2,
2159 },
2160 "0104000F",
2161 "movi v1.2s, #0",
2162 ));
2163 insns.push((
2164 Inst::VecDupImm {
2165 rd: writable_vreg(24),
2166 imm: ASIMDMovModImm::maybe_from_u64(1107296256, ScalarSize::Size32).unwrap(),
2167 invert: false,
2168 size: VectorSize::Size32x4,
2169 },
2170 "5864024F",
2171 "movi v24.4s, #66, LSL #24",
2172 ));
2173 insns.push((
2174 Inst::VecDupImm {
2175 rd: writable_vreg(8),
2176 imm: ASIMDMovModImm::zero(ScalarSize::Size64),
2177 invert: false,
2178 size: VectorSize::Size64x2,
2179 },
2180 "08E4006F",
2181 "movi v8.2d, #0",
2182 ));
2183 insns.push((
2184 Inst::VecDupImm {
2185 rd: writable_vreg(7),
2186 imm: ASIMDMovModImm::maybe_from_u64(18374687574904995840, ScalarSize::Size64).unwrap(),
2187 invert: false,
2188 size: VectorSize::Size64x2,
2189 },
2190 "87E6046F",
2191 "movi v7.2d, #18374687574904995840",
2192 ));
2193 insns.push((
2194 Inst::VecExtend {
2195 t: VecExtendOp::Sxtl8,
2196 rd: writable_vreg(4),
2197 rn: vreg(27),
2198 high_half: false,
2199 },
2200 "64A7080F",
2201 "sxtl v4.8h, v27.8b",
2202 ));
2203 insns.push((
2204 Inst::VecExtend {
2205 t: VecExtendOp::Sxtl16,
2206 rd: writable_vreg(17),
2207 rn: vreg(19),
2208 high_half: true,
2209 },
2210 "71A6104F",
2211 "sxtl2 v17.4s, v19.8h",
2212 ));
2213 insns.push((
2214 Inst::VecExtend {
2215 t: VecExtendOp::Sxtl32,
2216 rd: writable_vreg(30),
2217 rn: vreg(6),
2218 high_half: false,
2219 },
2220 "DEA4200F",
2221 "sxtl v30.2d, v6.2s",
2222 ));
2223 insns.push((
2224 Inst::VecExtend {
2225 t: VecExtendOp::Uxtl8,
2226 rd: writable_vreg(3),
2227 rn: vreg(29),
2228 high_half: true,
2229 },
2230 "A3A7086F",
2231 "uxtl2 v3.8h, v29.16b",
2232 ));
2233 insns.push((
2234 Inst::VecExtend {
2235 t: VecExtendOp::Uxtl16,
2236 rd: writable_vreg(15),
2237 rn: vreg(12),
2238 high_half: false,
2239 },
2240 "8FA5102F",
2241 "uxtl v15.4s, v12.4h",
2242 ));
2243 insns.push((
2244 Inst::VecExtend {
2245 t: VecExtendOp::Uxtl32,
2246 rd: writable_vreg(28),
2247 rn: vreg(2),
2248 high_half: true,
2249 },
2250 "5CA4206F",
2251 "uxtl2 v28.2d, v2.4s",
2252 ));
2253
2254 insns.push((
2255 Inst::VecMovElement {
2256 rd: writable_vreg(0),
2257 rn: vreg(31),
2258 dest_idx: 7,
2259 src_idx: 7,
2260 size: VectorSize::Size16x8,
2261 },
2262 "E0771E6E",
2263 "mov v0.h[7], v31.h[7]",
2264 ));
2265
2266 insns.push((
2267 Inst::VecMovElement {
2268 rd: writable_vreg(31),
2269 rn: vreg(16),
2270 dest_idx: 1,
2271 src_idx: 0,
2272 size: VectorSize::Size32x2,
2273 },
2274 "1F060C6E",
2275 "mov v31.s[1], v16.s[0]",
2276 ));
2277
2278 insns.push((
2279 Inst::VecMiscNarrow {
2280 op: VecMiscNarrowOp::Xtn,
2281 rd: writable_vreg(22),
2282 rn: vreg(8),
2283 size: VectorSize::Size32x2,
2284 high_half: false,
2285 },
2286 "1629A10E",
2287 "xtn v22.2s, v8.2d",
2288 ));
2289
2290 insns.push((
2291 Inst::VecMiscNarrow {
2292 op: VecMiscNarrowOp::Sqxtn,
2293 rd: writable_vreg(31),
2294 rn: vreg(0),
2295 size: VectorSize::Size16x8,
2296 high_half: true,
2297 },
2298 "1F48614E",
2299 "sqxtn2 v31.8h, v0.4s",
2300 ));
2301
2302 insns.push((
2303 Inst::VecMiscNarrow {
2304 op: VecMiscNarrowOp::Sqxtun,
2305 rd: writable_vreg(16),
2306 rn: vreg(23),
2307 size: VectorSize::Size8x16,
2308 high_half: false,
2309 },
2310 "F02A212E",
2311 "sqxtun v16.8b, v23.8h",
2312 ));
2313
2314 insns.push((
2315 Inst::VecRRPair {
2316 op: VecPairOp::Addp,
2317 rd: writable_vreg(0),
2318 rn: vreg(30),
2319 },
2320 "C0BBF15E",
2321 "addp d0, v30.2d",
2322 ));
2323
2324 insns.push((
2325 Inst::VecRRR {
2326 alu_op: VecALUOp::Sqadd,
2327 rd: writable_vreg(1),
2328 rn: vreg(2),
2329 rm: vreg(8),
2330 size: VectorSize::Size8x16,
2331 },
2332 "410C284E",
2333 "sqadd v1.16b, v2.16b, v8.16b",
2334 ));
2335
2336 insns.push((
2337 Inst::VecRRR {
2338 alu_op: VecALUOp::Sqadd,
2339 rd: writable_vreg(1),
2340 rn: vreg(12),
2341 rm: vreg(28),
2342 size: VectorSize::Size16x8,
2343 },
2344 "810D7C4E",
2345 "sqadd v1.8h, v12.8h, v28.8h",
2346 ));
2347
2348 insns.push((
2349 Inst::VecRRR {
2350 alu_op: VecALUOp::Sqadd,
2351 rd: writable_vreg(12),
2352 rn: vreg(2),
2353 rm: vreg(6),
2354 size: VectorSize::Size32x4,
2355 },
2356 "4C0CA64E",
2357 "sqadd v12.4s, v2.4s, v6.4s",
2358 ));
2359
2360 insns.push((
2361 Inst::VecRRR {
2362 alu_op: VecALUOp::Sqadd,
2363 rd: writable_vreg(20),
2364 rn: vreg(7),
2365 rm: vreg(13),
2366 size: VectorSize::Size64x2,
2367 },
2368 "F40CED4E",
2369 "sqadd v20.2d, v7.2d, v13.2d",
2370 ));
2371
2372 insns.push((
2373 Inst::VecRRR {
2374 alu_op: VecALUOp::Sqsub,
2375 rd: writable_vreg(1),
2376 rn: vreg(2),
2377 rm: vreg(8),
2378 size: VectorSize::Size8x16,
2379 },
2380 "412C284E",
2381 "sqsub v1.16b, v2.16b, v8.16b",
2382 ));
2383
2384 insns.push((
2385 Inst::VecRRR {
2386 alu_op: VecALUOp::Sqsub,
2387 rd: writable_vreg(1),
2388 rn: vreg(12),
2389 rm: vreg(28),
2390 size: VectorSize::Size16x8,
2391 },
2392 "812D7C4E",
2393 "sqsub v1.8h, v12.8h, v28.8h",
2394 ));
2395
2396 insns.push((
2397 Inst::VecRRR {
2398 alu_op: VecALUOp::Sqsub,
2399 rd: writable_vreg(12),
2400 rn: vreg(2),
2401 rm: vreg(6),
2402 size: VectorSize::Size32x4,
2403 },
2404 "4C2CA64E",
2405 "sqsub v12.4s, v2.4s, v6.4s",
2406 ));
2407
2408 insns.push((
2409 Inst::VecRRR {
2410 alu_op: VecALUOp::Sqsub,
2411 rd: writable_vreg(20),
2412 rn: vreg(7),
2413 rm: vreg(13),
2414 size: VectorSize::Size64x2,
2415 },
2416 "F42CED4E",
2417 "sqsub v20.2d, v7.2d, v13.2d",
2418 ));
2419
2420 insns.push((
2421 Inst::VecRRR {
2422 alu_op: VecALUOp::Uqadd,
2423 rd: writable_vreg(1),
2424 rn: vreg(2),
2425 rm: vreg(8),
2426 size: VectorSize::Size8x16,
2427 },
2428 "410C286E",
2429 "uqadd v1.16b, v2.16b, v8.16b",
2430 ));
2431
2432 insns.push((
2433 Inst::VecRRR {
2434 alu_op: VecALUOp::Uqadd,
2435 rd: writable_vreg(1),
2436 rn: vreg(12),
2437 rm: vreg(28),
2438 size: VectorSize::Size16x8,
2439 },
2440 "810D7C6E",
2441 "uqadd v1.8h, v12.8h, v28.8h",
2442 ));
2443
2444 insns.push((
2445 Inst::VecRRR {
2446 alu_op: VecALUOp::Uqadd,
2447 rd: writable_vreg(12),
2448 rn: vreg(2),
2449 rm: vreg(6),
2450 size: VectorSize::Size32x4,
2451 },
2452 "4C0CA66E",
2453 "uqadd v12.4s, v2.4s, v6.4s",
2454 ));
2455
2456 insns.push((
2457 Inst::VecRRR {
2458 alu_op: VecALUOp::Uqadd,
2459 rd: writable_vreg(20),
2460 rn: vreg(7),
2461 rm: vreg(13),
2462 size: VectorSize::Size64x2,
2463 },
2464 "F40CED6E",
2465 "uqadd v20.2d, v7.2d, v13.2d",
2466 ));
2467
2468 insns.push((
2469 Inst::VecRRR {
2470 alu_op: VecALUOp::Uqsub,
2471 rd: writable_vreg(1),
2472 rn: vreg(2),
2473 rm: vreg(8),
2474 size: VectorSize::Size8x16,
2475 },
2476 "412C286E",
2477 "uqsub v1.16b, v2.16b, v8.16b",
2478 ));
2479
2480 insns.push((
2481 Inst::VecRRR {
2482 alu_op: VecALUOp::Uqsub,
2483 rd: writable_vreg(1),
2484 rn: vreg(12),
2485 rm: vreg(28),
2486 size: VectorSize::Size16x8,
2487 },
2488 "812D7C6E",
2489 "uqsub v1.8h, v12.8h, v28.8h",
2490 ));
2491
2492 insns.push((
2493 Inst::VecRRR {
2494 alu_op: VecALUOp::Uqsub,
2495 rd: writable_vreg(12),
2496 rn: vreg(2),
2497 rm: vreg(6),
2498 size: VectorSize::Size32x4,
2499 },
2500 "4C2CA66E",
2501 "uqsub v12.4s, v2.4s, v6.4s",
2502 ));
2503
2504 insns.push((
2505 Inst::VecRRR {
2506 alu_op: VecALUOp::Uqsub,
2507 rd: writable_vreg(20),
2508 rn: vreg(7),
2509 rm: vreg(13),
2510 size: VectorSize::Size64x2,
2511 },
2512 "F42CED6E",
2513 "uqsub v20.2d, v7.2d, v13.2d",
2514 ));
2515
2516 insns.push((
2517 Inst::VecRRR {
2518 alu_op: VecALUOp::Cmeq,
2519 rd: writable_vreg(3),
2520 rn: vreg(23),
2521 rm: vreg(24),
2522 size: VectorSize::Size8x16,
2523 },
2524 "E38E386E",
2525 "cmeq v3.16b, v23.16b, v24.16b",
2526 ));
2527
2528 insns.push((
2529 Inst::VecRRR {
2530 alu_op: VecALUOp::Cmgt,
2531 rd: writable_vreg(3),
2532 rn: vreg(23),
2533 rm: vreg(24),
2534 size: VectorSize::Size8x16,
2535 },
2536 "E336384E",
2537 "cmgt v3.16b, v23.16b, v24.16b",
2538 ));
2539
2540 insns.push((
2541 Inst::VecRRR {
2542 alu_op: VecALUOp::Cmge,
2543 rd: writable_vreg(23),
2544 rn: vreg(9),
2545 rm: vreg(12),
2546 size: VectorSize::Size8x16,
2547 },
2548 "373D2C4E",
2549 "cmge v23.16b, v9.16b, v12.16b",
2550 ));
2551
2552 insns.push((
2553 Inst::VecRRR {
2554 alu_op: VecALUOp::Cmhi,
2555 rd: writable_vreg(5),
2556 rn: vreg(1),
2557 rm: vreg(1),
2558 size: VectorSize::Size8x16,
2559 },
2560 "2534216E",
2561 "cmhi v5.16b, v1.16b, v1.16b",
2562 ));
2563
2564 insns.push((
2565 Inst::VecRRR {
2566 alu_op: VecALUOp::Cmhs,
2567 rd: writable_vreg(8),
2568 rn: vreg(2),
2569 rm: vreg(15),
2570 size: VectorSize::Size8x16,
2571 },
2572 "483C2F6E",
2573 "cmhs v8.16b, v2.16b, v15.16b",
2574 ));
2575
2576 insns.push((
2577 Inst::VecRRR {
2578 alu_op: VecALUOp::Cmeq,
2579 rd: writable_vreg(3),
2580 rn: vreg(23),
2581 rm: vreg(24),
2582 size: VectorSize::Size16x8,
2583 },
2584 "E38E786E",
2585 "cmeq v3.8h, v23.8h, v24.8h",
2586 ));
2587
2588 insns.push((
2589 Inst::VecRRR {
2590 alu_op: VecALUOp::Cmgt,
2591 rd: writable_vreg(3),
2592 rn: vreg(23),
2593 rm: vreg(24),
2594 size: VectorSize::Size16x8,
2595 },
2596 "E336784E",
2597 "cmgt v3.8h, v23.8h, v24.8h",
2598 ));
2599
2600 insns.push((
2601 Inst::VecRRR {
2602 alu_op: VecALUOp::Cmge,
2603 rd: writable_vreg(23),
2604 rn: vreg(9),
2605 rm: vreg(12),
2606 size: VectorSize::Size16x8,
2607 },
2608 "373D6C4E",
2609 "cmge v23.8h, v9.8h, v12.8h",
2610 ));
2611
2612 insns.push((
2613 Inst::VecRRR {
2614 alu_op: VecALUOp::Cmhi,
2615 rd: writable_vreg(5),
2616 rn: vreg(1),
2617 rm: vreg(1),
2618 size: VectorSize::Size16x8,
2619 },
2620 "2534616E",
2621 "cmhi v5.8h, v1.8h, v1.8h",
2622 ));
2623
2624 insns.push((
2625 Inst::VecRRR {
2626 alu_op: VecALUOp::Cmhs,
2627 rd: writable_vreg(8),
2628 rn: vreg(2),
2629 rm: vreg(15),
2630 size: VectorSize::Size16x8,
2631 },
2632 "483C6F6E",
2633 "cmhs v8.8h, v2.8h, v15.8h",
2634 ));
2635
2636 insns.push((
2637 Inst::VecRRR {
2638 alu_op: VecALUOp::Cmeq,
2639 rd: writable_vreg(3),
2640 rn: vreg(23),
2641 rm: vreg(24),
2642 size: VectorSize::Size32x4,
2643 },
2644 "E38EB86E",
2645 "cmeq v3.4s, v23.4s, v24.4s",
2646 ));
2647
2648 insns.push((
2649 Inst::VecRRR {
2650 alu_op: VecALUOp::Cmgt,
2651 rd: writable_vreg(3),
2652 rn: vreg(23),
2653 rm: vreg(24),
2654 size: VectorSize::Size32x4,
2655 },
2656 "E336B84E",
2657 "cmgt v3.4s, v23.4s, v24.4s",
2658 ));
2659
2660 insns.push((
2661 Inst::VecRRR {
2662 alu_op: VecALUOp::Cmge,
2663 rd: writable_vreg(23),
2664 rn: vreg(9),
2665 rm: vreg(12),
2666 size: VectorSize::Size32x4,
2667 },
2668 "373DAC4E",
2669 "cmge v23.4s, v9.4s, v12.4s",
2670 ));
2671
2672 insns.push((
2673 Inst::VecRRR {
2674 alu_op: VecALUOp::Cmhi,
2675 rd: writable_vreg(5),
2676 rn: vreg(1),
2677 rm: vreg(1),
2678 size: VectorSize::Size32x4,
2679 },
2680 "2534A16E",
2681 "cmhi v5.4s, v1.4s, v1.4s",
2682 ));
2683
2684 insns.push((
2685 Inst::VecRRR {
2686 alu_op: VecALUOp::Cmhs,
2687 rd: writable_vreg(8),
2688 rn: vreg(2),
2689 rm: vreg(15),
2690 size: VectorSize::Size32x4,
2691 },
2692 "483CAF6E",
2693 "cmhs v8.4s, v2.4s, v15.4s",
2694 ));
2695
2696 insns.push((
2697 Inst::VecRRR {
2698 alu_op: VecALUOp::Fcmeq,
2699 rd: writable_vreg(28),
2700 rn: vreg(12),
2701 rm: vreg(4),
2702 size: VectorSize::Size32x2,
2703 },
2704 "9CE5240E",
2705 "fcmeq v28.2s, v12.2s, v4.2s",
2706 ));
2707
2708 insns.push((
2709 Inst::VecRRR {
2710 alu_op: VecALUOp::Fcmgt,
2711 rd: writable_vreg(3),
2712 rn: vreg(16),
2713 rm: vreg(31),
2714 size: VectorSize::Size64x2,
2715 },
2716 "03E6FF6E",
2717 "fcmgt v3.2d, v16.2d, v31.2d",
2718 ));
2719
2720 insns.push((
2721 Inst::VecRRR {
2722 alu_op: VecALUOp::Fcmge,
2723 rd: writable_vreg(18),
2724 rn: vreg(23),
2725 rm: vreg(0),
2726 size: VectorSize::Size64x2,
2727 },
2728 "F2E6606E",
2729 "fcmge v18.2d, v23.2d, v0.2d",
2730 ));
2731
2732 insns.push((
2733 Inst::VecRRR {
2734 alu_op: VecALUOp::And,
2735 rd: writable_vreg(20),
2736 rn: vreg(19),
2737 rm: vreg(18),
2738 size: VectorSize::Size32x4,
2739 },
2740 "741E324E",
2741 "and v20.16b, v19.16b, v18.16b",
2742 ));
2743
2744 insns.push((
2745 Inst::VecRRR {
2746 alu_op: VecALUOp::Bic,
2747 rd: writable_vreg(8),
2748 rn: vreg(11),
2749 rm: vreg(1),
2750 size: VectorSize::Size8x16,
2751 },
2752 "681D614E",
2753 "bic v8.16b, v11.16b, v1.16b",
2754 ));
2755
2756 insns.push((
2757 Inst::VecRRR {
2758 alu_op: VecALUOp::Orr,
2759 rd: writable_vreg(15),
2760 rn: vreg(2),
2761 rm: vreg(12),
2762 size: VectorSize::Size16x8,
2763 },
2764 "4F1CAC4E",
2765 "orr v15.16b, v2.16b, v12.16b",
2766 ));
2767
2768 insns.push((
2769 Inst::VecRRR {
2770 alu_op: VecALUOp::Eor,
2771 rd: writable_vreg(18),
2772 rn: vreg(3),
2773 rm: vreg(22),
2774 size: VectorSize::Size8x16,
2775 },
2776 "721C366E",
2777 "eor v18.16b, v3.16b, v22.16b",
2778 ));
2779
2780 insns.push((
2781 Inst::VecRRR {
2782 alu_op: VecALUOp::Bsl,
2783 rd: writable_vreg(8),
2784 rn: vreg(9),
2785 rm: vreg(1),
2786 size: VectorSize::Size8x16,
2787 },
2788 "281D616E",
2789 "bsl v8.16b, v9.16b, v1.16b",
2790 ));
2791
2792 insns.push((
2793 Inst::VecRRR {
2794 alu_op: VecALUOp::Umaxp,
2795 rd: writable_vreg(8),
2796 rn: vreg(12),
2797 rm: vreg(1),
2798 size: VectorSize::Size8x16,
2799 },
2800 "88A5216E",
2801 "umaxp v8.16b, v12.16b, v1.16b",
2802 ));
2803
2804 insns.push((
2805 Inst::VecRRR {
2806 alu_op: VecALUOp::Umaxp,
2807 rd: writable_vreg(1),
2808 rn: vreg(6),
2809 rm: vreg(1),
2810 size: VectorSize::Size16x8,
2811 },
2812 "C1A4616E",
2813 "umaxp v1.8h, v6.8h, v1.8h",
2814 ));
2815
2816 insns.push((
2817 Inst::VecRRR {
2818 alu_op: VecALUOp::Umaxp,
2819 rd: writable_vreg(1),
2820 rn: vreg(20),
2821 rm: vreg(16),
2822 size: VectorSize::Size32x4,
2823 },
2824 "81A6B06E",
2825 "umaxp v1.4s, v20.4s, v16.4s",
2826 ));
2827
2828 insns.push((
2829 Inst::VecRRR {
2830 alu_op: VecALUOp::Add,
2831 rd: writable_vreg(5),
2832 rn: vreg(1),
2833 rm: vreg(1),
2834 size: VectorSize::Size8x16,
2835 },
2836 "2584214E",
2837 "add v5.16b, v1.16b, v1.16b",
2838 ));
2839
2840 insns.push((
2841 Inst::VecRRR {
2842 alu_op: VecALUOp::Add,
2843 rd: writable_vreg(7),
2844 rn: vreg(13),
2845 rm: vreg(2),
2846 size: VectorSize::Size16x8,
2847 },
2848 "A785624E",
2849 "add v7.8h, v13.8h, v2.8h",
2850 ));
2851
2852 insns.push((
2853 Inst::VecRRR {
2854 alu_op: VecALUOp::Add,
2855 rd: writable_vreg(18),
2856 rn: vreg(9),
2857 rm: vreg(6),
2858 size: VectorSize::Size32x4,
2859 },
2860 "3285A64E",
2861 "add v18.4s, v9.4s, v6.4s",
2862 ));
2863
2864 insns.push((
2865 Inst::VecRRR {
2866 alu_op: VecALUOp::Add,
2867 rd: writable_vreg(1),
2868 rn: vreg(3),
2869 rm: vreg(2),
2870 size: VectorSize::Size64x2,
2871 },
2872 "6184E24E",
2873 "add v1.2d, v3.2d, v2.2d",
2874 ));
2875
2876 insns.push((
2877 Inst::VecRRR {
2878 alu_op: VecALUOp::Sub,
2879 rd: writable_vreg(5),
2880 rn: vreg(1),
2881 rm: vreg(1),
2882 size: VectorSize::Size8x16,
2883 },
2884 "2584216E",
2885 "sub v5.16b, v1.16b, v1.16b",
2886 ));
2887
2888 insns.push((
2889 Inst::VecRRR {
2890 alu_op: VecALUOp::Sub,
2891 rd: writable_vreg(7),
2892 rn: vreg(13),
2893 rm: vreg(2),
2894 size: VectorSize::Size16x8,
2895 },
2896 "A785626E",
2897 "sub v7.8h, v13.8h, v2.8h",
2898 ));
2899
2900 insns.push((
2901 Inst::VecRRR {
2902 alu_op: VecALUOp::Sub,
2903 rd: writable_vreg(18),
2904 rn: vreg(9),
2905 rm: vreg(6),
2906 size: VectorSize::Size32x4,
2907 },
2908 "3285A66E",
2909 "sub v18.4s, v9.4s, v6.4s",
2910 ));
2911
2912 insns.push((
2913 Inst::VecRRR {
2914 alu_op: VecALUOp::Sub,
2915 rd: writable_vreg(18),
2916 rn: vreg(0),
2917 rm: vreg(8),
2918 size: VectorSize::Size64x2,
2919 },
2920 "1284E86E",
2921 "sub v18.2d, v0.2d, v8.2d",
2922 ));
2923
2924 insns.push((
2925 Inst::VecRRR {
2926 alu_op: VecALUOp::Mul,
2927 rd: writable_vreg(25),
2928 rn: vreg(9),
2929 rm: vreg(8),
2930 size: VectorSize::Size8x16,
2931 },
2932 "399D284E",
2933 "mul v25.16b, v9.16b, v8.16b",
2934 ));
2935
2936 insns.push((
2937 Inst::VecRRR {
2938 alu_op: VecALUOp::Mul,
2939 rd: writable_vreg(30),
2940 rn: vreg(30),
2941 rm: vreg(12),
2942 size: VectorSize::Size16x8,
2943 },
2944 "DE9F6C4E",
2945 "mul v30.8h, v30.8h, v12.8h",
2946 ));
2947
2948 insns.push((
2949 Inst::VecRRR {
2950 alu_op: VecALUOp::Mul,
2951 rd: writable_vreg(18),
2952 rn: vreg(18),
2953 rm: vreg(18),
2954 size: VectorSize::Size32x4,
2955 },
2956 "529EB24E",
2957 "mul v18.4s, v18.4s, v18.4s",
2958 ));
2959
2960 insns.push((
2961 Inst::VecRRR {
2962 alu_op: VecALUOp::Ushl,
2963 rd: writable_vreg(18),
2964 rn: vreg(18),
2965 rm: vreg(18),
2966 size: VectorSize::Size8x16,
2967 },
2968 "5246326E",
2969 "ushl v18.16b, v18.16b, v18.16b",
2970 ));
2971
2972 insns.push((
2973 Inst::VecRRR {
2974 alu_op: VecALUOp::Ushl,
2975 rd: writable_vreg(18),
2976 rn: vreg(18),
2977 rm: vreg(18),
2978 size: VectorSize::Size16x8,
2979 },
2980 "5246726E",
2981 "ushl v18.8h, v18.8h, v18.8h",
2982 ));
2983
2984 insns.push((
2985 Inst::VecRRR {
2986 alu_op: VecALUOp::Ushl,
2987 rd: writable_vreg(18),
2988 rn: vreg(1),
2989 rm: vreg(21),
2990 size: VectorSize::Size32x4,
2991 },
2992 "3244B56E",
2993 "ushl v18.4s, v1.4s, v21.4s",
2994 ));
2995
2996 insns.push((
2997 Inst::VecRRR {
2998 alu_op: VecALUOp::Ushl,
2999 rd: writable_vreg(5),
3000 rn: vreg(7),
3001 rm: vreg(19),
3002 size: VectorSize::Size64x2,
3003 },
3004 "E544F36E",
3005 "ushl v5.2d, v7.2d, v19.2d",
3006 ));
3007
3008 insns.push((
3009 Inst::VecRRR {
3010 alu_op: VecALUOp::Sshl,
3011 rd: writable_vreg(18),
3012 rn: vreg(18),
3013 rm: vreg(18),
3014 size: VectorSize::Size8x16,
3015 },
3016 "5246324E",
3017 "sshl v18.16b, v18.16b, v18.16b",
3018 ));
3019
3020 insns.push((
3021 Inst::VecRRR {
3022 alu_op: VecALUOp::Sshl,
3023 rd: writable_vreg(30),
3024 rn: vreg(1),
3025 rm: vreg(29),
3026 size: VectorSize::Size16x8,
3027 },
3028 "3E447D4E",
3029 "sshl v30.8h, v1.8h, v29.8h",
3030 ));
3031
3032 insns.push((
3033 Inst::VecRRR {
3034 alu_op: VecALUOp::Sshl,
3035 rd: writable_vreg(8),
3036 rn: vreg(22),
3037 rm: vreg(21),
3038 size: VectorSize::Size32x4,
3039 },
3040 "C846B54E",
3041 "sshl v8.4s, v22.4s, v21.4s",
3042 ));
3043
3044 insns.push((
3045 Inst::VecRRR {
3046 alu_op: VecALUOp::Sshl,
3047 rd: writable_vreg(8),
3048 rn: vreg(22),
3049 rm: vreg(2),
3050 size: VectorSize::Size64x2,
3051 },
3052 "C846E24E",
3053 "sshl v8.2d, v22.2d, v2.2d",
3054 ));
3055
3056 insns.push((
3057 Inst::VecRRR {
3058 alu_op: VecALUOp::Umin,
3059 rd: writable_vreg(1),
3060 rn: vreg(12),
3061 rm: vreg(3),
3062 size: VectorSize::Size8x16,
3063 },
3064 "816D236E",
3065 "umin v1.16b, v12.16b, v3.16b",
3066 ));
3067
3068 insns.push((
3069 Inst::VecRRR {
3070 alu_op: VecALUOp::Umin,
3071 rd: writable_vreg(30),
3072 rn: vreg(20),
3073 rm: vreg(10),
3074 size: VectorSize::Size16x8,
3075 },
3076 "9E6E6A6E",
3077 "umin v30.8h, v20.8h, v10.8h",
3078 ));
3079
3080 insns.push((
3081 Inst::VecRRR {
3082 alu_op: VecALUOp::Umin,
3083 rd: writable_vreg(8),
3084 rn: vreg(22),
3085 rm: vreg(21),
3086 size: VectorSize::Size32x4,
3087 },
3088 "C86EB56E",
3089 "umin v8.4s, v22.4s, v21.4s",
3090 ));
3091
3092 insns.push((
3093 Inst::VecRRR {
3094 alu_op: VecALUOp::Smin,
3095 rd: writable_vreg(1),
3096 rn: vreg(12),
3097 rm: vreg(3),
3098 size: VectorSize::Size8x16,
3099 },
3100 "816D234E",
3101 "smin v1.16b, v12.16b, v3.16b",
3102 ));
3103
3104 insns.push((
3105 Inst::VecRRR {
3106 alu_op: VecALUOp::Smin,
3107 rd: writable_vreg(30),
3108 rn: vreg(20),
3109 rm: vreg(10),
3110 size: VectorSize::Size16x8,
3111 },
3112 "9E6E6A4E",
3113 "smin v30.8h, v20.8h, v10.8h",
3114 ));
3115
3116 insns.push((
3117 Inst::VecRRR {
3118 alu_op: VecALUOp::Smin,
3119 rd: writable_vreg(8),
3120 rn: vreg(22),
3121 rm: vreg(21),
3122 size: VectorSize::Size32x4,
3123 },
3124 "C86EB54E",
3125 "smin v8.4s, v22.4s, v21.4s",
3126 ));
3127
3128 insns.push((
3129 Inst::VecRRR {
3130 alu_op: VecALUOp::Umax,
3131 rd: writable_vreg(6),
3132 rn: vreg(9),
3133 rm: vreg(8),
3134 size: VectorSize::Size8x8,
3135 },
3136 "2665282E",
3137 "umax v6.8b, v9.8b, v8.8b",
3138 ));
3139
3140 insns.push((
3141 Inst::VecRRR {
3142 alu_op: VecALUOp::Umax,
3143 rd: writable_vreg(11),
3144 rn: vreg(13),
3145 rm: vreg(2),
3146 size: VectorSize::Size16x8,
3147 },
3148 "AB65626E",
3149 "umax v11.8h, v13.8h, v2.8h",
3150 ));
3151
3152 insns.push((
3153 Inst::VecRRR {
3154 alu_op: VecALUOp::Umax,
3155 rd: writable_vreg(8),
3156 rn: vreg(12),
3157 rm: vreg(14),
3158 size: VectorSize::Size32x4,
3159 },
3160 "8865AE6E",
3161 "umax v8.4s, v12.4s, v14.4s",
3162 ));
3163
3164 insns.push((
3165 Inst::VecRRR {
3166 alu_op: VecALUOp::Smax,
3167 rd: writable_vreg(6),
3168 rn: vreg(9),
3169 rm: vreg(8),
3170 size: VectorSize::Size8x16,
3171 },
3172 "2665284E",
3173 "smax v6.16b, v9.16b, v8.16b",
3174 ));
3175
3176 insns.push((
3177 Inst::VecRRR {
3178 alu_op: VecALUOp::Smax,
3179 rd: writable_vreg(11),
3180 rn: vreg(13),
3181 rm: vreg(2),
3182 size: VectorSize::Size16x8,
3183 },
3184 "AB65624E",
3185 "smax v11.8h, v13.8h, v2.8h",
3186 ));
3187
3188 insns.push((
3189 Inst::VecRRR {
3190 alu_op: VecALUOp::Smax,
3191 rd: writable_vreg(8),
3192 rn: vreg(12),
3193 rm: vreg(14),
3194 size: VectorSize::Size32x4,
3195 },
3196 "8865AE4E",
3197 "smax v8.4s, v12.4s, v14.4s",
3198 ));
3199
3200 insns.push((
3201 Inst::VecRRR {
3202 alu_op: VecALUOp::Urhadd,
3203 rd: writable_vreg(8),
3204 rn: vreg(1),
3205 rm: vreg(3),
3206 size: VectorSize::Size8x16,
3207 },
3208 "2814236E",
3209 "urhadd v8.16b, v1.16b, v3.16b",
3210 ));
3211
3212 insns.push((
3213 Inst::VecRRR {
3214 alu_op: VecALUOp::Urhadd,
3215 rd: writable_vreg(2),
3216 rn: vreg(13),
3217 rm: vreg(6),
3218 size: VectorSize::Size16x8,
3219 },
3220 "A215666E",
3221 "urhadd v2.8h, v13.8h, v6.8h",
3222 ));
3223
3224 insns.push((
3225 Inst::VecRRR {
3226 alu_op: VecALUOp::Urhadd,
3227 rd: writable_vreg(8),
3228 rn: vreg(12),
3229 rm: vreg(14),
3230 size: VectorSize::Size32x4,
3231 },
3232 "8815AE6E",
3233 "urhadd v8.4s, v12.4s, v14.4s",
3234 ));
3235
3236 insns.push((
3237 Inst::VecRRR {
3238 alu_op: VecALUOp::Fadd,
3239 rd: writable_vreg(31),
3240 rn: vreg(0),
3241 rm: vreg(16),
3242 size: VectorSize::Size32x4,
3243 },
3244 "1FD4304E",
3245 "fadd v31.4s, v0.4s, v16.4s",
3246 ));
3247
3248 insns.push((
3249 Inst::VecRRR {
3250 alu_op: VecALUOp::Fsub,
3251 rd: writable_vreg(8),
3252 rn: vreg(7),
3253 rm: vreg(15),
3254 size: VectorSize::Size64x2,
3255 },
3256 "E8D4EF4E",
3257 "fsub v8.2d, v7.2d, v15.2d",
3258 ));
3259
3260 insns.push((
3261 Inst::VecRRR {
3262 alu_op: VecALUOp::Fdiv,
3263 rd: writable_vreg(1),
3264 rn: vreg(3),
3265 rm: vreg(4),
3266 size: VectorSize::Size32x4,
3267 },
3268 "61FC246E",
3269 "fdiv v1.4s, v3.4s, v4.4s",
3270 ));
3271
3272 insns.push((
3273 Inst::VecRRR {
3274 alu_op: VecALUOp::Fmax,
3275 rd: writable_vreg(31),
3276 rn: vreg(16),
3277 rm: vreg(0),
3278 size: VectorSize::Size64x2,
3279 },
3280 "1FF6604E",
3281 "fmax v31.2d, v16.2d, v0.2d",
3282 ));
3283
3284 insns.push((
3285 Inst::VecRRR {
3286 alu_op: VecALUOp::Fmin,
3287 rd: writable_vreg(5),
3288 rn: vreg(19),
3289 rm: vreg(26),
3290 size: VectorSize::Size32x4,
3291 },
3292 "65F6BA4E",
3293 "fmin v5.4s, v19.4s, v26.4s",
3294 ));
3295
3296 insns.push((
3297 Inst::VecRRR {
3298 alu_op: VecALUOp::Fmul,
3299 rd: writable_vreg(2),
3300 rn: vreg(0),
3301 rm: vreg(5),
3302 size: VectorSize::Size64x2,
3303 },
3304 "02DC656E",
3305 "fmul v2.2d, v0.2d, v5.2d",
3306 ));
3307
3308 insns.push((
3309 Inst::VecRRR {
3310 alu_op: VecALUOp::Addp,
3311 rd: writable_vreg(16),
3312 rn: vreg(12),
3313 rm: vreg(1),
3314 size: VectorSize::Size8x16,
3315 },
3316 "90BD214E",
3317 "addp v16.16b, v12.16b, v1.16b",
3318 ));
3319
3320 insns.push((
3321 Inst::VecRRR {
3322 alu_op: VecALUOp::Addp,
3323 rd: writable_vreg(8),
3324 rn: vreg(12),
3325 rm: vreg(14),
3326 size: VectorSize::Size32x4,
3327 },
3328 "88BDAE4E",
3329 "addp v8.4s, v12.4s, v14.4s",
3330 ));
3331
3332 insns.push((
3333 Inst::VecRRR {
3334 alu_op: VecALUOp::Umlal,
3335 rd: writable_vreg(9),
3336 rn: vreg(20),
3337 rm: vreg(17),
3338 size: VectorSize::Size32x2,
3339 },
3340 "8982B12E",
3341 "umlal v9.2d, v20.2s, v17.2s",
3342 ));
3343
3344 insns.push((
3345 Inst::VecRRR {
3346 alu_op: VecALUOp::Zip1,
3347 rd: writable_vreg(16),
3348 rn: vreg(12),
3349 rm: vreg(1),
3350 size: VectorSize::Size8x16,
3351 },
3352 "9039014E",
3353 "zip1 v16.16b, v12.16b, v1.16b",
3354 ));
3355
3356 insns.push((
3357 Inst::VecRRR {
3358 alu_op: VecALUOp::Zip1,
3359 rd: writable_vreg(2),
3360 rn: vreg(13),
3361 rm: vreg(6),
3362 size: VectorSize::Size16x8,
3363 },
3364 "A239464E",
3365 "zip1 v2.8h, v13.8h, v6.8h",
3366 ));
3367
3368 insns.push((
3369 Inst::VecRRR {
3370 alu_op: VecALUOp::Zip1,
3371 rd: writable_vreg(8),
3372 rn: vreg(12),
3373 rm: vreg(14),
3374 size: VectorSize::Size32x4,
3375 },
3376 "88398E4E",
3377 "zip1 v8.4s, v12.4s, v14.4s",
3378 ));
3379
3380 insns.push((
3381 Inst::VecRRR {
3382 alu_op: VecALUOp::Zip1,
3383 rd: writable_vreg(9),
3384 rn: vreg(20),
3385 rm: vreg(17),
3386 size: VectorSize::Size64x2,
3387 },
3388 "893AD14E",
3389 "zip1 v9.2d, v20.2d, v17.2d",
3390 ));
3391
3392 insns.push((
3393 Inst::VecRRR {
3394 alu_op: VecALUOp::Smull,
3395 rd: writable_vreg(16),
3396 rn: vreg(12),
3397 rm: vreg(1),
3398 size: VectorSize::Size8x16,
3399 },
3400 "90C1210E",
3401 "smull v16.8h, v12.8b, v1.8b",
3402 ));
3403
3404 insns.push((
3405 Inst::VecRRR {
3406 alu_op: VecALUOp::Smull,
3407 rd: writable_vreg(2),
3408 rn: vreg(13),
3409 rm: vreg(6),
3410 size: VectorSize::Size16x8,
3411 },
3412 "A2C1660E",
3413 "smull v2.4s, v13.4h, v6.4h",
3414 ));
3415
3416 insns.push((
3417 Inst::VecRRR {
3418 alu_op: VecALUOp::Smull,
3419 rd: writable_vreg(8),
3420 rn: vreg(12),
3421 rm: vreg(14),
3422 size: VectorSize::Size32x4,
3423 },
3424 "88C1AE0E",
3425 "smull v8.2d, v12.2s, v14.2s",
3426 ));
3427
3428 insns.push((
3429 Inst::VecRRR {
3430 alu_op: VecALUOp::Smull2,
3431 rd: writable_vreg(16),
3432 rn: vreg(12),
3433 rm: vreg(1),
3434 size: VectorSize::Size8x16,
3435 },
3436 "90C1214E",
3437 "smull2 v16.8h, v12.16b, v1.16b",
3438 ));
3439
3440 insns.push((
3441 Inst::VecRRR {
3442 alu_op: VecALUOp::Smull2,
3443 rd: writable_vreg(2),
3444 rn: vreg(13),
3445 rm: vreg(6),
3446 size: VectorSize::Size16x8,
3447 },
3448 "A2C1664E",
3449 "smull2 v2.4s, v13.8h, v6.8h",
3450 ));
3451
3452 insns.push((
3453 Inst::VecRRR {
3454 alu_op: VecALUOp::Smull2,
3455 rd: writable_vreg(8),
3456 rn: vreg(12),
3457 rm: vreg(14),
3458 size: VectorSize::Size32x4,
3459 },
3460 "88C1AE4E",
3461 "smull2 v8.2d, v12.4s, v14.4s",
3462 ));
3463
3464 insns.push((
3465 Inst::VecMisc {
3466 op: VecMisc2::Not,
3467 rd: writable_vreg(20),
3468 rn: vreg(17),
3469 size: VectorSize::Size8x8,
3470 },
3471 "345A202E",
3472 "mvn v20.8b, v17.8b",
3473 ));
3474
3475 insns.push((
3476 Inst::VecMisc {
3477 op: VecMisc2::Not,
3478 rd: writable_vreg(2),
3479 rn: vreg(1),
3480 size: VectorSize::Size32x4,
3481 },
3482 "2258206E",
3483 "mvn v2.16b, v1.16b",
3484 ));
3485
3486 insns.push((
3487 Inst::VecMisc {
3488 op: VecMisc2::Neg,
3489 rd: writable_vreg(3),
3490 rn: vreg(7),
3491 size: VectorSize::Size8x8,
3492 },
3493 "E3B8202E",
3494 "neg v3.8b, v7.8b",
3495 ));
3496
3497 insns.push((
3498 Inst::VecMisc {
3499 op: VecMisc2::Neg,
3500 rd: writable_vreg(8),
3501 rn: vreg(12),
3502 size: VectorSize::Size8x16,
3503 },
3504 "88B9206E",
3505 "neg v8.16b, v12.16b",
3506 ));
3507
3508 insns.push((
3509 Inst::VecMisc {
3510 op: VecMisc2::Neg,
3511 rd: writable_vreg(0),
3512 rn: vreg(31),
3513 size: VectorSize::Size16x8,
3514 },
3515 "E0BB606E",
3516 "neg v0.8h, v31.8h",
3517 ));
3518
3519 insns.push((
3520 Inst::VecMisc {
3521 op: VecMisc2::Neg,
3522 rd: writable_vreg(2),
3523 rn: vreg(3),
3524 size: VectorSize::Size32x4,
3525 },
3526 "62B8A06E",
3527 "neg v2.4s, v3.4s",
3528 ));
3529
3530 insns.push((
3531 Inst::VecMisc {
3532 op: VecMisc2::Neg,
3533 rd: writable_vreg(10),
3534 rn: vreg(8),
3535 size: VectorSize::Size64x2,
3536 },
3537 "0AB9E06E",
3538 "neg v10.2d, v8.2d",
3539 ));
3540
3541 insns.push((
3542 Inst::VecMisc {
3543 op: VecMisc2::Abs,
3544 rd: writable_vreg(3),
3545 rn: vreg(1),
3546 size: VectorSize::Size8x8,
3547 },
3548 "23B8200E",
3549 "abs v3.8b, v1.8b",
3550 ));
3551
3552 insns.push((
3553 Inst::VecMisc {
3554 op: VecMisc2::Abs,
3555 rd: writable_vreg(1),
3556 rn: vreg(1),
3557 size: VectorSize::Size8x16,
3558 },
3559 "21B8204E",
3560 "abs v1.16b, v1.16b",
3561 ));
3562
3563 insns.push((
3564 Inst::VecMisc {
3565 op: VecMisc2::Abs,
3566 rd: writable_vreg(29),
3567 rn: vreg(28),
3568 size: VectorSize::Size16x8,
3569 },
3570 "9DBB604E",
3571 "abs v29.8h, v28.8h",
3572 ));
3573
3574 insns.push((
3575 Inst::VecMisc {
3576 op: VecMisc2::Abs,
3577 rd: writable_vreg(7),
3578 rn: vreg(8),
3579 size: VectorSize::Size32x4,
3580 },
3581 "07B9A04E",
3582 "abs v7.4s, v8.4s",
3583 ));
3584
3585 insns.push((
3586 Inst::VecMisc {
3587 op: VecMisc2::Abs,
3588 rd: writable_vreg(1),
3589 rn: vreg(10),
3590 size: VectorSize::Size64x2,
3591 },
3592 "41B9E04E",
3593 "abs v1.2d, v10.2d",
3594 ));
3595
3596 insns.push((
3597 Inst::VecMisc {
3598 op: VecMisc2::Fabs,
3599 rd: writable_vreg(15),
3600 rn: vreg(16),
3601 size: VectorSize::Size32x4,
3602 },
3603 "0FFAA04E",
3604 "fabs v15.4s, v16.4s",
3605 ));
3606
3607 insns.push((
3608 Inst::VecMisc {
3609 op: VecMisc2::Fneg,
3610 rd: writable_vreg(31),
3611 rn: vreg(0),
3612 size: VectorSize::Size32x4,
3613 },
3614 "1FF8A06E",
3615 "fneg v31.4s, v0.4s",
3616 ));
3617
3618 insns.push((
3619 Inst::VecMisc {
3620 op: VecMisc2::Fsqrt,
3621 rd: writable_vreg(7),
3622 rn: vreg(18),
3623 size: VectorSize::Size64x2,
3624 },
3625 "47FAE16E",
3626 "fsqrt v7.2d, v18.2d",
3627 ));
3628
3629 insns.push((
3630 Inst::VecMisc {
3631 op: VecMisc2::Rev64,
3632 rd: writable_vreg(1),
3633 rn: vreg(10),
3634 size: VectorSize::Size32x4,
3635 },
3636 "4109A04E",
3637 "rev64 v1.4s, v10.4s",
3638 ));
3639
3640 insns.push((
3641 Inst::VecMisc {
3642 op: VecMisc2::Shll,
3643 rd: writable_vreg(12),
3644 rn: vreg(5),
3645 size: VectorSize::Size8x8,
3646 },
3647 "AC38212E",
3648 "shll v12.8h, v5.8b, #8",
3649 ));
3650
3651 insns.push((
3652 Inst::VecMisc {
3653 op: VecMisc2::Shll,
3654 rd: writable_vreg(9),
3655 rn: vreg(1),
3656 size: VectorSize::Size16x4,
3657 },
3658 "2938612E",
3659 "shll v9.4s, v1.4h, #16",
3660 ));
3661
3662 insns.push((
3663 Inst::VecMisc {
3664 op: VecMisc2::Shll,
3665 rd: writable_vreg(1),
3666 rn: vreg(10),
3667 size: VectorSize::Size32x2,
3668 },
3669 "4139A12E",
3670 "shll v1.2d, v10.2s, #32",
3671 ));
3672
3673 insns.push((
3674 Inst::VecMisc {
3675 op: VecMisc2::Fcvtzs,
3676 rd: writable_vreg(4),
3677 rn: vreg(22),
3678 size: VectorSize::Size32x4,
3679 },
3680 "C4BAA14E",
3681 "fcvtzs v4.4s, v22.4s",
3682 ));
3683
3684 insns.push((
3685 Inst::VecMisc {
3686 op: VecMisc2::Fcvtzu,
3687 rd: writable_vreg(29),
3688 rn: vreg(15),
3689 size: VectorSize::Size64x2,
3690 },
3691 "FDB9E16E",
3692 "fcvtzu v29.2d, v15.2d",
3693 ));
3694
3695 insns.push((
3696 Inst::VecMisc {
3697 op: VecMisc2::Scvtf,
3698 rd: writable_vreg(20),
3699 rn: vreg(8),
3700 size: VectorSize::Size32x4,
3701 },
3702 "14D9214E",
3703 "scvtf v20.4s, v8.4s",
3704 ));
3705
3706 insns.push((
3707 Inst::VecMisc {
3708 op: VecMisc2::Ucvtf,
3709 rd: writable_vreg(10),
3710 rn: vreg(19),
3711 size: VectorSize::Size64x2,
3712 },
3713 "6ADA616E",
3714 "ucvtf v10.2d, v19.2d",
3715 ));
3716
3717 insns.push((
3718 Inst::VecMisc {
3719 op: VecMisc2::Frintn,
3720 rd: writable_vreg(11),
3721 rn: vreg(18),
3722 size: VectorSize::Size32x4,
3723 },
3724 "4B8A214E",
3725 "frintn v11.4s, v18.4s",
3726 ));
3727
3728 insns.push((
3729 Inst::VecMisc {
3730 op: VecMisc2::Frintn,
3731 rd: writable_vreg(12),
3732 rn: vreg(17),
3733 size: VectorSize::Size64x2,
3734 },
3735 "2C8A614E",
3736 "frintn v12.2d, v17.2d",
3737 ));
3738
3739 insns.push((
3740 Inst::VecMisc {
3741 op: VecMisc2::Frintz,
3742 rd: writable_vreg(11),
3743 rn: vreg(18),
3744 size: VectorSize::Size32x4,
3745 },
3746 "4B9AA14E",
3747 "frintz v11.4s, v18.4s",
3748 ));
3749
3750 insns.push((
3751 Inst::VecMisc {
3752 op: VecMisc2::Frintz,
3753 rd: writable_vreg(12),
3754 rn: vreg(17),
3755 size: VectorSize::Size64x2,
3756 },
3757 "2C9AE14E",
3758 "frintz v12.2d, v17.2d",
3759 ));
3760
3761 insns.push((
3762 Inst::VecMisc {
3763 op: VecMisc2::Frintm,
3764 rd: writable_vreg(11),
3765 rn: vreg(18),
3766 size: VectorSize::Size32x4,
3767 },
3768 "4B9A214E",
3769 "frintm v11.4s, v18.4s",
3770 ));
3771
3772 insns.push((
3773 Inst::VecMisc {
3774 op: VecMisc2::Frintm,
3775 rd: writable_vreg(12),
3776 rn: vreg(17),
3777 size: VectorSize::Size64x2,
3778 },
3779 "2C9A614E",
3780 "frintm v12.2d, v17.2d",
3781 ));
3782
3783 insns.push((
3784 Inst::VecMisc {
3785 op: VecMisc2::Frintp,
3786 rd: writable_vreg(11),
3787 rn: vreg(18),
3788 size: VectorSize::Size32x4,
3789 },
3790 "4B8AA14E",
3791 "frintp v11.4s, v18.4s",
3792 ));
3793
3794 insns.push((
3795 Inst::VecMisc {
3796 op: VecMisc2::Frintp,
3797 rd: writable_vreg(12),
3798 rn: vreg(17),
3799 size: VectorSize::Size64x2,
3800 },
3801 "2C8AE14E",
3802 "frintp v12.2d, v17.2d",
3803 ));
3804
3805 insns.push((
3806 Inst::VecMisc {
3807 op: VecMisc2::Cnt,
3808 rd: writable_vreg(23),
3809 rn: vreg(5),
3810 size: VectorSize::Size8x8,
3811 },
3812 "B758200E",
3813 "cnt v23.8b, v5.8b",
3814 ));
3815
3816 insns.push((
3817 Inst::VecMisc {
3818 op: VecMisc2::Cmeq0,
3819 rd: writable_vreg(12),
3820 rn: vreg(27),
3821 size: VectorSize::Size16x8,
3822 },
3823 "6C9B604E",
3824 "cmeq v12.8h, v27.8h, #0",
3825 ));
3826
3827 insns.push((
3828 Inst::VecLanes {
3829 op: VecLanesOp::Uminv,
3830 rd: writable_vreg(0),
3831 rn: vreg(31),
3832 size: VectorSize::Size8x8,
3833 },
3834 "E0AB312E",
3835 "uminv b0, v31.8b",
3836 ));
3837
3838 insns.push((
3839 Inst::VecLanes {
3840 op: VecLanesOp::Uminv,
3841 rd: writable_vreg(2),
3842 rn: vreg(1),
3843 size: VectorSize::Size8x16,
3844 },
3845 "22A8316E",
3846 "uminv b2, v1.16b",
3847 ));
3848
3849 insns.push((
3850 Inst::VecLanes {
3851 op: VecLanesOp::Uminv,
3852 rd: writable_vreg(3),
3853 rn: vreg(11),
3854 size: VectorSize::Size16x8,
3855 },
3856 "63A9716E",
3857 "uminv h3, v11.8h",
3858 ));
3859
3860 insns.push((
3861 Inst::VecLanes {
3862 op: VecLanesOp::Uminv,
3863 rd: writable_vreg(18),
3864 rn: vreg(4),
3865 size: VectorSize::Size32x4,
3866 },
3867 "92A8B16E",
3868 "uminv s18, v4.4s",
3869 ));
3870
3871 insns.push((
3872 Inst::VecLanes {
3873 op: VecLanesOp::Addv,
3874 rd: writable_vreg(2),
3875 rn: vreg(29),
3876 size: VectorSize::Size8x16,
3877 },
3878 "A2BB314E",
3879 "addv b2, v29.16b",
3880 ));
3881
3882 insns.push((
3883 Inst::VecLanes {
3884 op: VecLanesOp::Addv,
3885 rd: writable_vreg(15),
3886 rn: vreg(7),
3887 size: VectorSize::Size16x4,
3888 },
3889 "EFB8710E",
3890 "addv h15, v7.4h",
3891 ));
3892
3893 insns.push((
3894 Inst::VecLanes {
3895 op: VecLanesOp::Addv,
3896 rd: writable_vreg(3),
3897 rn: vreg(21),
3898 size: VectorSize::Size16x8,
3899 },
3900 "A3BA714E",
3901 "addv h3, v21.8h",
3902 ));
3903
3904 insns.push((
3905 Inst::VecLanes {
3906 op: VecLanesOp::Addv,
3907 rd: writable_vreg(18),
3908 rn: vreg(5),
3909 size: VectorSize::Size32x4,
3910 },
3911 "B2B8B14E",
3912 "addv s18, v5.4s",
3913 ));
3914
3915 insns.push((
3916 Inst::VecShiftImm {
3917 op: VecShiftImmOp::Shl,
3918 rd: writable_vreg(27),
3919 rn: vreg(5),
3920 imm: 7,
3921 size: VectorSize::Size8x16,
3922 },
3923 "BB540F4F",
3924 "shl v27.16b, v5.16b, #7",
3925 ));
3926
3927 insns.push((
3928 Inst::VecShiftImm {
3929 op: VecShiftImmOp::Shl,
3930 rd: writable_vreg(1),
3931 rn: vreg(30),
3932 imm: 0,
3933 size: VectorSize::Size8x16,
3934 },
3935 "C157084F",
3936 "shl v1.16b, v30.16b, #0",
3937 ));
3938
3939 insns.push((
3940 Inst::VecShiftImm {
3941 op: VecShiftImmOp::Sshr,
3942 rd: writable_vreg(26),
3943 rn: vreg(6),
3944 imm: 16,
3945 size: VectorSize::Size16x8,
3946 },
3947 "DA04104F",
3948 "sshr v26.8h, v6.8h, #16",
3949 ));
3950
3951 insns.push((
3952 Inst::VecShiftImm {
3953 op: VecShiftImmOp::Sshr,
3954 rd: writable_vreg(3),
3955 rn: vreg(19),
3956 imm: 1,
3957 size: VectorSize::Size16x8,
3958 },
3959 "63061F4F",
3960 "sshr v3.8h, v19.8h, #1",
3961 ));
3962
3963 insns.push((
3964 Inst::VecShiftImm {
3965 op: VecShiftImmOp::Ushr,
3966 rd: writable_vreg(25),
3967 rn: vreg(6),
3968 imm: 32,
3969 size: VectorSize::Size32x4,
3970 },
3971 "D904206F",
3972 "ushr v25.4s, v6.4s, #32",
3973 ));
3974
3975 insns.push((
3976 Inst::VecShiftImm {
3977 op: VecShiftImmOp::Ushr,
3978 rd: writable_vreg(5),
3979 rn: vreg(21),
3980 imm: 1,
3981 size: VectorSize::Size32x4,
3982 },
3983 "A5063F6F",
3984 "ushr v5.4s, v21.4s, #1",
3985 ));
3986
3987 insns.push((
3988 Inst::VecShiftImm {
3989 op: VecShiftImmOp::Shl,
3990 rd: writable_vreg(22),
3991 rn: vreg(13),
3992 imm: 63,
3993 size: VectorSize::Size64x2,
3994 },
3995 "B6557F4F",
3996 "shl v22.2d, v13.2d, #63",
3997 ));
3998
3999 insns.push((
4000 Inst::VecShiftImm {
4001 op: VecShiftImmOp::Shl,
4002 rd: writable_vreg(23),
4003 rn: vreg(9),
4004 imm: 0,
4005 size: VectorSize::Size64x2,
4006 },
4007 "3755404F",
4008 "shl v23.2d, v9.2d, #0",
4009 ));
4010
4011 insns.push((
4012 Inst::VecExtract {
4013 rd: writable_vreg(1),
4014 rn: vreg(30),
4015 rm: vreg(17),
4016 imm4: 0,
4017 },
4018 "C103116E",
4019 "ext v1.16b, v30.16b, v17.16b, #0",
4020 ));
4021
4022 insns.push((
4023 Inst::VecExtract {
4024 rd: writable_vreg(1),
4025 rn: vreg(30),
4026 rm: vreg(17),
4027 imm4: 8,
4028 },
4029 "C143116E",
4030 "ext v1.16b, v30.16b, v17.16b, #8",
4031 ));
4032
4033 insns.push((
4034 Inst::VecExtract {
4035 rd: writable_vreg(1),
4036 rn: vreg(30),
4037 rm: vreg(17),
4038 imm4: 15,
4039 },
4040 "C17B116E",
4041 "ext v1.16b, v30.16b, v17.16b, #15",
4042 ));
4043
4044 insns.push((
4045 Inst::VecTbl {
4046 rd: writable_vreg(0),
4047 rn: vreg(31),
4048 rm: vreg(16),
4049 is_extension: false,
4050 },
4051 "E003104E",
4052 "tbl v0.16b, { v31.16b }, v16.16b",
4053 ));
4054
4055 insns.push((
4056 Inst::VecTbl {
4057 rd: writable_vreg(4),
4058 rn: vreg(12),
4059 rm: vreg(23),
4060 is_extension: true,
4061 },
4062 "8411174E",
4063 "tbx v4.16b, { v12.16b }, v23.16b",
4064 ));
4065
4066 insns.push((
4067 Inst::VecTbl2 {
4068 rd: writable_vreg(16),
4069 rn: vreg(31),
4070 rn2: vreg(0),
4071 rm: vreg(26),
4072 is_extension: false,
4073 },
4074 "F0231A4E",
4075 "tbl v16.16b, { v31.16b, v0.16b }, v26.16b",
4076 ));
4077
4078 insns.push((
4079 Inst::VecTbl2 {
4080 rd: writable_vreg(3),
4081 rn: vreg(11),
4082 rn2: vreg(12),
4083 rm: vreg(19),
4084 is_extension: true,
4085 },
4086 "6331134E",
4087 "tbx v3.16b, { v11.16b, v12.16b }, v19.16b",
4088 ));
4089
4090 insns.push((
4091 Inst::VecLoadReplicate {
4092 rd: writable_vreg(31),
4093 rn: xreg(0),
4094
4095 size: VectorSize::Size64x2,
4096 },
4097 "1FCC404D",
4098 "ld1r { v31.2d }, [x0]",
4099 ));
4100
4101 insns.push((
4102 Inst::VecLoadReplicate {
4103 rd: writable_vreg(0),
4104 rn: xreg(25),
4105
4106 size: VectorSize::Size8x8,
4107 },
4108 "20C3400D",
4109 "ld1r { v0.8b }, [x25]",
4110 ));
4111
4112 insns.push((
4113 Inst::VecCSel {
4114 rd: writable_vreg(5),
4115 rn: vreg(10),
4116 rm: vreg(19),
4117 cond: Cond::Gt,
4118 },
4119 "6C000054651EB34E02000014451DAA4E",
4120 "vcsel v5.16b, v10.16b, v19.16b, gt (if-then-else diamond)",
4121 ));
4122
4123 insns.push((
4124 Inst::Extend {
4125 rd: writable_xreg(3),
4126 rn: xreg(5),
4127 signed: false,
4128 from_bits: 1,
4129 to_bits: 32,
4130 },
4131 "A3000012",
4132 "and w3, w5, #1",
4133 ));
4134 insns.push((
4135 Inst::Extend {
4136 rd: writable_xreg(3),
4137 rn: xreg(5),
4138 signed: false,
4139 from_bits: 1,
4140 to_bits: 64,
4141 },
4142 "A3000012",
4143 "and w3, w5, #1",
4144 ));
4145 insns.push((
4146 Inst::Extend {
4147 rd: writable_xreg(10),
4148 rn: xreg(21),
4149 signed: true,
4150 from_bits: 1,
4151 to_bits: 32,
4152 },
4153 "AA020013",
4154 "sbfx w10, w21, #0, #1",
4155 ));
4156 insns.push((
4157 Inst::Extend {
4158 rd: writable_xreg(1),
4159 rn: xreg(2),
4160 signed: true,
4161 from_bits: 1,
4162 to_bits: 64,
4163 },
4164 "41004093",
4165 "sbfx x1, x2, #0, #1",
4166 ));
4167 insns.push((
4168 Inst::Extend {
4169 rd: writable_xreg(1),
4170 rn: xreg(2),
4171 signed: false,
4172 from_bits: 8,
4173 to_bits: 32,
4174 },
4175 "411C0053",
4176 "uxtb w1, w2",
4177 ));
4178 insns.push((
4179 Inst::Extend {
4180 rd: writable_xreg(1),
4181 rn: xreg(2),
4182 signed: true,
4183 from_bits: 8,
4184 to_bits: 32,
4185 },
4186 "411C0013",
4187 "sxtb w1, w2",
4188 ));
4189 insns.push((
4190 Inst::Extend {
4191 rd: writable_xreg(1),
4192 rn: xreg(2),
4193 signed: false,
4194 from_bits: 16,
4195 to_bits: 32,
4196 },
4197 "413C0053",
4198 "uxth w1, w2",
4199 ));
4200 insns.push((
4201 Inst::Extend {
4202 rd: writable_xreg(1),
4203 rn: xreg(2),
4204 signed: true,
4205 from_bits: 16,
4206 to_bits: 32,
4207 },
4208 "413C0013",
4209 "sxth w1, w2",
4210 ));
4211 insns.push((
4212 Inst::Extend {
4213 rd: writable_xreg(1),
4214 rn: xreg(2),
4215 signed: false,
4216 from_bits: 8,
4217 to_bits: 64,
4218 },
4219 "411C0053",
4220 "uxtb w1, w2",
4221 ));
4222 insns.push((
4223 Inst::Extend {
4224 rd: writable_xreg(1),
4225 rn: xreg(2),
4226 signed: true,
4227 from_bits: 8,
4228 to_bits: 64,
4229 },
4230 "411C4093",
4231 "sxtb x1, w2",
4232 ));
4233 insns.push((
4234 Inst::Extend {
4235 rd: writable_xreg(1),
4236 rn: xreg(2),
4237 signed: false,
4238 from_bits: 16,
4239 to_bits: 64,
4240 },
4241 "413C0053",
4242 "uxth w1, w2",
4243 ));
4244 insns.push((
4245 Inst::Extend {
4246 rd: writable_xreg(1),
4247 rn: xreg(2),
4248 signed: true,
4249 from_bits: 16,
4250 to_bits: 64,
4251 },
4252 "413C4093",
4253 "sxth x1, w2",
4254 ));
4255 insns.push((
4256 Inst::Extend {
4257 rd: writable_xreg(1),
4258 rn: xreg(2),
4259 signed: false,
4260 from_bits: 32,
4261 to_bits: 64,
4262 },
4263 "E103022A",
4264 "mov w1, w2",
4265 ));
4266 insns.push((
4267 Inst::Extend {
4268 rd: writable_xreg(1),
4269 rn: xreg(2),
4270 signed: true,
4271 from_bits: 32,
4272 to_bits: 64,
4273 },
4274 "417C4093",
4275 "sxtw x1, w2",
4276 ));
4277
4278 insns.push((
4279 Inst::Jump {
4280 dest: BranchTarget::ResolvedOffset(64),
4281 },
4282 "10000014",
4283 "b 64",
4284 ));
4285
4286 insns.push((
4287 Inst::TrapIf {
4288 trap_code: TrapCode::Interrupt,
4289 kind: CondBrKind::NotZero(xreg(8)),
4290 },
4291 "480000B40000A0D4",
4292 "cbz x8, 8 ; udf",
4293 ));
4294 insns.push((
4295 Inst::TrapIf {
4296 trap_code: TrapCode::Interrupt,
4297 kind: CondBrKind::Zero(xreg(8)),
4298 },
4299 "480000B50000A0D4",
4300 "cbnz x8, 8 ; udf",
4301 ));
4302 insns.push((
4303 Inst::TrapIf {
4304 trap_code: TrapCode::Interrupt,
4305 kind: CondBrKind::Cond(Cond::Ne),
4306 },
4307 "400000540000A0D4",
4308 "b.eq 8 ; udf",
4309 ));
4310 insns.push((
4311 Inst::TrapIf {
4312 trap_code: TrapCode::Interrupt,
4313 kind: CondBrKind::Cond(Cond::Eq),
4314 },
4315 "410000540000A0D4",
4316 "b.ne 8 ; udf",
4317 ));
4318 insns.push((
4319 Inst::TrapIf {
4320 trap_code: TrapCode::Interrupt,
4321 kind: CondBrKind::Cond(Cond::Lo),
4322 },
4323 "420000540000A0D4",
4324 "b.hs 8 ; udf",
4325 ));
4326 insns.push((
4327 Inst::TrapIf {
4328 trap_code: TrapCode::Interrupt,
4329 kind: CondBrKind::Cond(Cond::Hs),
4330 },
4331 "430000540000A0D4",
4332 "b.lo 8 ; udf",
4333 ));
4334 insns.push((
4335 Inst::TrapIf {
4336 trap_code: TrapCode::Interrupt,
4337 kind: CondBrKind::Cond(Cond::Pl),
4338 },
4339 "440000540000A0D4",
4340 "b.mi 8 ; udf",
4341 ));
4342 insns.push((
4343 Inst::TrapIf {
4344 trap_code: TrapCode::Interrupt,
4345 kind: CondBrKind::Cond(Cond::Mi),
4346 },
4347 "450000540000A0D4",
4348 "b.pl 8 ; udf",
4349 ));
4350 insns.push((
4351 Inst::TrapIf {
4352 trap_code: TrapCode::Interrupt,
4353 kind: CondBrKind::Cond(Cond::Vc),
4354 },
4355 "460000540000A0D4",
4356 "b.vs 8 ; udf",
4357 ));
4358 insns.push((
4359 Inst::TrapIf {
4360 trap_code: TrapCode::Interrupt,
4361 kind: CondBrKind::Cond(Cond::Vs),
4362 },
4363 "470000540000A0D4",
4364 "b.vc 8 ; udf",
4365 ));
4366 insns.push((
4367 Inst::TrapIf {
4368 trap_code: TrapCode::Interrupt,
4369 kind: CondBrKind::Cond(Cond::Ls),
4370 },
4371 "480000540000A0D4",
4372 "b.hi 8 ; udf",
4373 ));
4374 insns.push((
4375 Inst::TrapIf {
4376 trap_code: TrapCode::Interrupt,
4377 kind: CondBrKind::Cond(Cond::Hi),
4378 },
4379 "490000540000A0D4",
4380 "b.ls 8 ; udf",
4381 ));
4382 insns.push((
4383 Inst::TrapIf {
4384 trap_code: TrapCode::Interrupt,
4385 kind: CondBrKind::Cond(Cond::Lt),
4386 },
4387 "4A0000540000A0D4",
4388 "b.ge 8 ; udf",
4389 ));
4390 insns.push((
4391 Inst::TrapIf {
4392 trap_code: TrapCode::Interrupt,
4393 kind: CondBrKind::Cond(Cond::Ge),
4394 },
4395 "4B0000540000A0D4",
4396 "b.lt 8 ; udf",
4397 ));
4398 insns.push((
4399 Inst::TrapIf {
4400 trap_code: TrapCode::Interrupt,
4401 kind: CondBrKind::Cond(Cond::Le),
4402 },
4403 "4C0000540000A0D4",
4404 "b.gt 8 ; udf",
4405 ));
4406 insns.push((
4407 Inst::TrapIf {
4408 trap_code: TrapCode::Interrupt,
4409 kind: CondBrKind::Cond(Cond::Gt),
4410 },
4411 "4D0000540000A0D4",
4412 "b.le 8 ; udf",
4413 ));
4414 insns.push((
4415 Inst::TrapIf {
4416 trap_code: TrapCode::Interrupt,
4417 kind: CondBrKind::Cond(Cond::Nv),
4418 },
4419 "4E0000540000A0D4",
4420 "b.al 8 ; udf",
4421 ));
4422 insns.push((
4423 Inst::TrapIf {
4424 trap_code: TrapCode::Interrupt,
4425 kind: CondBrKind::Cond(Cond::Al),
4426 },
4427 "4F0000540000A0D4",
4428 "b.nv 8 ; udf",
4429 ));
4430
4431 insns.push((
4432 Inst::CondBr {
4433 taken: BranchTarget::ResolvedOffset(64),
4434 not_taken: BranchTarget::ResolvedOffset(128),
4435 kind: CondBrKind::Cond(Cond::Le),
4436 },
4437 "0D02005420000014",
4438 "b.le 64 ; b 128",
4439 ));
4440
4441 insns.push((
4442 Inst::Call {
4443 info: Box::new(CallInfo {
4444 dest: ExternalName::testcase("test0"),
4445 uses: Vec::new(),
4446 defs: Vec::new(),
4447 opcode: Opcode::Call,
4448 caller_callconv: CallConv::SystemV,
4449 callee_callconv: CallConv::SystemV,
4450 }),
4451 },
4452 "00000094",
4453 "bl 0",
4454 ));
4455
4456 insns.push((
4457 Inst::CallInd {
4458 info: Box::new(CallIndInfo {
4459 rn: xreg(10),
4460 uses: Vec::new(),
4461 defs: Vec::new(),
4462 opcode: Opcode::CallIndirect,
4463 caller_callconv: CallConv::SystemV,
4464 callee_callconv: CallConv::SystemV,
4465 }),
4466 },
4467 "40013FD6",
4468 "blr x10",
4469 ));
4470
4471 insns.push((
4472 Inst::IndirectBr {
4473 rn: xreg(3),
4474 targets: vec![],
4475 },
4476 "60001FD6",
4477 "br x3",
4478 ));
4479
4480 insns.push((Inst::Brk, "000020D4", "brk #0"));
4481
4482 insns.push((
4483 Inst::Adr {
4484 rd: writable_xreg(15),
4485 off: (1 << 20) - 4,
4486 },
4487 "EFFF7F10",
4488 "adr x15, pc+1048572",
4489 ));
4490
4491 insns.push((
4492 Inst::FpuMove64 {
4493 rd: writable_vreg(8),
4494 rn: vreg(4),
4495 },
4496 "8840601E",
4497 "fmov d8, d4",
4498 ));
4499
4500 insns.push((
4501 Inst::FpuMove128 {
4502 rd: writable_vreg(17),
4503 rn: vreg(26),
4504 },
4505 "511FBA4E",
4506 "mov v17.16b, v26.16b",
4507 ));
4508
4509 insns.push((
4510 Inst::FpuMoveFromVec {
4511 rd: writable_vreg(1),
4512 rn: vreg(30),
4513 idx: 2,
4514 size: VectorSize::Size32x4,
4515 },
4516 "C107145E",
4517 "mov s1, v30.s[2]",
4518 ));
4519
4520 insns.push((
4521 Inst::FpuMoveFromVec {
4522 rd: writable_vreg(23),
4523 rn: vreg(11),
4524 idx: 0,
4525 size: VectorSize::Size64x2,
4526 },
4527 "7705085E",
4528 "mov d23, v11.d[0]",
4529 ));
4530
4531 insns.push((
4532 Inst::FpuExtend {
4533 rd: writable_vreg(31),
4534 rn: vreg(0),
4535 size: ScalarSize::Size32,
4536 },
4537 "1F40201E",
4538 "fmov s31, s0",
4539 ));
4540
4541 insns.push((
4542 Inst::FpuRR {
4543 fpu_op: FPUOp1::Abs32,
4544 rd: writable_vreg(15),
4545 rn: vreg(30),
4546 },
4547 "CFC3201E",
4548 "fabs s15, s30",
4549 ));
4550
4551 insns.push((
4552 Inst::FpuRR {
4553 fpu_op: FPUOp1::Abs64,
4554 rd: writable_vreg(15),
4555 rn: vreg(30),
4556 },
4557 "CFC3601E",
4558 "fabs d15, d30",
4559 ));
4560
4561 insns.push((
4562 Inst::FpuRR {
4563 fpu_op: FPUOp1::Neg32,
4564 rd: writable_vreg(15),
4565 rn: vreg(30),
4566 },
4567 "CF43211E",
4568 "fneg s15, s30",
4569 ));
4570
4571 insns.push((
4572 Inst::FpuRR {
4573 fpu_op: FPUOp1::Neg64,
4574 rd: writable_vreg(15),
4575 rn: vreg(30),
4576 },
4577 "CF43611E",
4578 "fneg d15, d30",
4579 ));
4580
4581 insns.push((
4582 Inst::FpuRR {
4583 fpu_op: FPUOp1::Sqrt32,
4584 rd: writable_vreg(15),
4585 rn: vreg(30),
4586 },
4587 "CFC3211E",
4588 "fsqrt s15, s30",
4589 ));
4590
4591 insns.push((
4592 Inst::FpuRR {
4593 fpu_op: FPUOp1::Sqrt64,
4594 rd: writable_vreg(15),
4595 rn: vreg(30),
4596 },
4597 "CFC3611E",
4598 "fsqrt d15, d30",
4599 ));
4600
4601 insns.push((
4602 Inst::FpuRR {
4603 fpu_op: FPUOp1::Cvt32To64,
4604 rd: writable_vreg(15),
4605 rn: vreg(30),
4606 },
4607 "CFC3221E",
4608 "fcvt d15, s30",
4609 ));
4610
4611 insns.push((
4612 Inst::FpuRR {
4613 fpu_op: FPUOp1::Cvt64To32,
4614 rd: writable_vreg(15),
4615 rn: vreg(30),
4616 },
4617 "CF43621E",
4618 "fcvt s15, d30",
4619 ));
4620
4621 insns.push((
4622 Inst::FpuRRR {
4623 fpu_op: FPUOp2::Add32,
4624 rd: writable_vreg(15),
4625 rn: vreg(30),
4626 rm: vreg(31),
4627 },
4628 "CF2B3F1E",
4629 "fadd s15, s30, s31",
4630 ));
4631
4632 insns.push((
4633 Inst::FpuRRR {
4634 fpu_op: FPUOp2::Add64,
4635 rd: writable_vreg(15),
4636 rn: vreg(30),
4637 rm: vreg(31),
4638 },
4639 "CF2B7F1E",
4640 "fadd d15, d30, d31",
4641 ));
4642
4643 insns.push((
4644 Inst::FpuRRR {
4645 fpu_op: FPUOp2::Sub32,
4646 rd: writable_vreg(15),
4647 rn: vreg(30),
4648 rm: vreg(31),
4649 },
4650 "CF3B3F1E",
4651 "fsub s15, s30, s31",
4652 ));
4653
4654 insns.push((
4655 Inst::FpuRRR {
4656 fpu_op: FPUOp2::Sub64,
4657 rd: writable_vreg(15),
4658 rn: vreg(30),
4659 rm: vreg(31),
4660 },
4661 "CF3B7F1E",
4662 "fsub d15, d30, d31",
4663 ));
4664
4665 insns.push((
4666 Inst::FpuRRR {
4667 fpu_op: FPUOp2::Mul32,
4668 rd: writable_vreg(15),
4669 rn: vreg(30),
4670 rm: vreg(31),
4671 },
4672 "CF0B3F1E",
4673 "fmul s15, s30, s31",
4674 ));
4675
4676 insns.push((
4677 Inst::FpuRRR {
4678 fpu_op: FPUOp2::Mul64,
4679 rd: writable_vreg(15),
4680 rn: vreg(30),
4681 rm: vreg(31),
4682 },
4683 "CF0B7F1E",
4684 "fmul d15, d30, d31",
4685 ));
4686
4687 insns.push((
4688 Inst::FpuRRR {
4689 fpu_op: FPUOp2::Div32,
4690 rd: writable_vreg(15),
4691 rn: vreg(30),
4692 rm: vreg(31),
4693 },
4694 "CF1B3F1E",
4695 "fdiv s15, s30, s31",
4696 ));
4697
4698 insns.push((
4699 Inst::FpuRRR {
4700 fpu_op: FPUOp2::Div64,
4701 rd: writable_vreg(15),
4702 rn: vreg(30),
4703 rm: vreg(31),
4704 },
4705 "CF1B7F1E",
4706 "fdiv d15, d30, d31",
4707 ));
4708
4709 insns.push((
4710 Inst::FpuRRR {
4711 fpu_op: FPUOp2::Max32,
4712 rd: writable_vreg(15),
4713 rn: vreg(30),
4714 rm: vreg(31),
4715 },
4716 "CF4B3F1E",
4717 "fmax s15, s30, s31",
4718 ));
4719
4720 insns.push((
4721 Inst::FpuRRR {
4722 fpu_op: FPUOp2::Max64,
4723 rd: writable_vreg(15),
4724 rn: vreg(30),
4725 rm: vreg(31),
4726 },
4727 "CF4B7F1E",
4728 "fmax d15, d30, d31",
4729 ));
4730
4731 insns.push((
4732 Inst::FpuRRR {
4733 fpu_op: FPUOp2::Min32,
4734 rd: writable_vreg(15),
4735 rn: vreg(30),
4736 rm: vreg(31),
4737 },
4738 "CF5B3F1E",
4739 "fmin s15, s30, s31",
4740 ));
4741
4742 insns.push((
4743 Inst::FpuRRR {
4744 fpu_op: FPUOp2::Min64,
4745 rd: writable_vreg(15),
4746 rn: vreg(30),
4747 rm: vreg(31),
4748 },
4749 "CF5B7F1E",
4750 "fmin d15, d30, d31",
4751 ));
4752
4753 insns.push((
4754 Inst::FpuRRR {
4755 fpu_op: FPUOp2::Uqadd64,
4756 rd: writable_vreg(21),
4757 rn: vreg(22),
4758 rm: vreg(23),
4759 },
4760 "D50EF77E",
4761 "uqadd d21, d22, d23",
4762 ));
4763
4764 insns.push((
4765 Inst::FpuRRR {
4766 fpu_op: FPUOp2::Sqadd64,
4767 rd: writable_vreg(21),
4768 rn: vreg(22),
4769 rm: vreg(23),
4770 },
4771 "D50EF75E",
4772 "sqadd d21, d22, d23",
4773 ));
4774
4775 insns.push((
4776 Inst::FpuRRR {
4777 fpu_op: FPUOp2::Uqsub64,
4778 rd: writable_vreg(21),
4779 rn: vreg(22),
4780 rm: vreg(23),
4781 },
4782 "D52EF77E",
4783 "uqsub d21, d22, d23",
4784 ));
4785
4786 insns.push((
4787 Inst::FpuRRR {
4788 fpu_op: FPUOp2::Sqsub64,
4789 rd: writable_vreg(21),
4790 rn: vreg(22),
4791 rm: vreg(23),
4792 },
4793 "D52EF75E",
4794 "sqsub d21, d22, d23",
4795 ));
4796
4797 insns.push((
4798 Inst::FpuRRRR {
4799 fpu_op: FPUOp3::MAdd32,
4800 rd: writable_vreg(15),
4801 rn: vreg(30),
4802 rm: vreg(31),
4803 ra: vreg(1),
4804 },
4805 "CF071F1F",
4806 "fmadd s15, s30, s31, s1",
4807 ));
4808
4809 insns.push((
4810 Inst::FpuRRRR {
4811 fpu_op: FPUOp3::MAdd64,
4812 rd: writable_vreg(15),
4813 rn: vreg(30),
4814 rm: vreg(31),
4815 ra: vreg(1),
4816 },
4817 "CF075F1F",
4818 "fmadd d15, d30, d31, d1",
4819 ));
4820
4821 insns.push((
4822 Inst::FpuRRI {
4823 fpu_op: FPUOpRI::UShr32(FPURightShiftImm::maybe_from_u8(32, 32).unwrap()),
4824 rd: writable_vreg(2),
4825 rn: vreg(5),
4826 },
4827 "A204202F",
4828 "ushr v2.2s, v5.2s, #32",
4829 ));
4830
4831 insns.push((
4832 Inst::FpuRRI {
4833 fpu_op: FPUOpRI::UShr64(FPURightShiftImm::maybe_from_u8(63, 64).unwrap()),
4834 rd: writable_vreg(2),
4835 rn: vreg(5),
4836 },
4837 "A204417F",
4838 "ushr d2, d5, #63",
4839 ));
4840
4841 insns.push((
4842 Inst::FpuRRI {
4843 fpu_op: FPUOpRI::Sli32(FPULeftShiftImm::maybe_from_u8(31, 32).unwrap()),
4844 rd: writable_vreg(4),
4845 rn: vreg(10),
4846 },
4847 "44553F2F",
4848 "sli v4.2s, v10.2s, #31",
4849 ));
4850
4851 insns.push((
4852 Inst::FpuRRI {
4853 fpu_op: FPUOpRI::Sli64(FPULeftShiftImm::maybe_from_u8(63, 64).unwrap()),
4854 rd: writable_vreg(4),
4855 rn: vreg(10),
4856 },
4857 "44557F7F",
4858 "sli d4, d10, #63",
4859 ));
4860
4861 insns.push((
4862 Inst::FpuToInt {
4863 op: FpuToIntOp::F32ToU32,
4864 rd: writable_xreg(1),
4865 rn: vreg(4),
4866 },
4867 "8100391E",
4868 "fcvtzu w1, s4",
4869 ));
4870
4871 insns.push((
4872 Inst::FpuToInt {
4873 op: FpuToIntOp::F32ToU64,
4874 rd: writable_xreg(1),
4875 rn: vreg(4),
4876 },
4877 "8100399E",
4878 "fcvtzu x1, s4",
4879 ));
4880
4881 insns.push((
4882 Inst::FpuToInt {
4883 op: FpuToIntOp::F32ToI32,
4884 rd: writable_xreg(1),
4885 rn: vreg(4),
4886 },
4887 "8100381E",
4888 "fcvtzs w1, s4",
4889 ));
4890
4891 insns.push((
4892 Inst::FpuToInt {
4893 op: FpuToIntOp::F32ToI64,
4894 rd: writable_xreg(1),
4895 rn: vreg(4),
4896 },
4897 "8100389E",
4898 "fcvtzs x1, s4",
4899 ));
4900
4901 insns.push((
4902 Inst::FpuToInt {
4903 op: FpuToIntOp::F64ToU32,
4904 rd: writable_xreg(1),
4905 rn: vreg(4),
4906 },
4907 "8100791E",
4908 "fcvtzu w1, d4",
4909 ));
4910
4911 insns.push((
4912 Inst::FpuToInt {
4913 op: FpuToIntOp::F64ToU64,
4914 rd: writable_xreg(1),
4915 rn: vreg(4),
4916 },
4917 "8100799E",
4918 "fcvtzu x1, d4",
4919 ));
4920
4921 insns.push((
4922 Inst::FpuToInt {
4923 op: FpuToIntOp::F64ToI32,
4924 rd: writable_xreg(1),
4925 rn: vreg(4),
4926 },
4927 "8100781E",
4928 "fcvtzs w1, d4",
4929 ));
4930
4931 insns.push((
4932 Inst::FpuToInt {
4933 op: FpuToIntOp::F64ToI64,
4934 rd: writable_xreg(1),
4935 rn: vreg(4),
4936 },
4937 "8100789E",
4938 "fcvtzs x1, d4",
4939 ));
4940
4941 insns.push((
4942 Inst::IntToFpu {
4943 op: IntToFpuOp::U32ToF32,
4944 rd: writable_vreg(1),
4945 rn: xreg(4),
4946 },
4947 "8100231E",
4948 "ucvtf s1, w4",
4949 ));
4950
4951 insns.push((
4952 Inst::IntToFpu {
4953 op: IntToFpuOp::I32ToF32,
4954 rd: writable_vreg(1),
4955 rn: xreg(4),
4956 },
4957 "8100221E",
4958 "scvtf s1, w4",
4959 ));
4960
4961 insns.push((
4962 Inst::IntToFpu {
4963 op: IntToFpuOp::U32ToF64,
4964 rd: writable_vreg(1),
4965 rn: xreg(4),
4966 },
4967 "8100631E",
4968 "ucvtf d1, w4",
4969 ));
4970
4971 insns.push((
4972 Inst::IntToFpu {
4973 op: IntToFpuOp::I32ToF64,
4974 rd: writable_vreg(1),
4975 rn: xreg(4),
4976 },
4977 "8100621E",
4978 "scvtf d1, w4",
4979 ));
4980
4981 insns.push((
4982 Inst::IntToFpu {
4983 op: IntToFpuOp::U64ToF32,
4984 rd: writable_vreg(1),
4985 rn: xreg(4),
4986 },
4987 "8100239E",
4988 "ucvtf s1, x4",
4989 ));
4990
4991 insns.push((
4992 Inst::IntToFpu {
4993 op: IntToFpuOp::I64ToF32,
4994 rd: writable_vreg(1),
4995 rn: xreg(4),
4996 },
4997 "8100229E",
4998 "scvtf s1, x4",
4999 ));
5000
5001 insns.push((
5002 Inst::IntToFpu {
5003 op: IntToFpuOp::U64ToF64,
5004 rd: writable_vreg(1),
5005 rn: xreg(4),
5006 },
5007 "8100639E",
5008 "ucvtf d1, x4",
5009 ));
5010
5011 insns.push((
5012 Inst::IntToFpu {
5013 op: IntToFpuOp::I64ToF64,
5014 rd: writable_vreg(1),
5015 rn: xreg(4),
5016 },
5017 "8100629E",
5018 "scvtf d1, x4",
5019 ));
5020
5021 insns.push((
5022 Inst::FpuCmp32 {
5023 rn: vreg(23),
5024 rm: vreg(24),
5025 },
5026 "E022381E",
5027 "fcmp s23, s24",
5028 ));
5029
5030 insns.push((
5031 Inst::FpuCmp64 {
5032 rn: vreg(23),
5033 rm: vreg(24),
5034 },
5035 "E022781E",
5036 "fcmp d23, d24",
5037 ));
5038
5039 insns.push((
5040 Inst::FpuLoad32 {
5041 rd: writable_vreg(16),
5042 mem: AMode::RegScaled(xreg(8), xreg(9), F32),
5043 flags: MemFlags::trusted(),
5044 },
5045 "107969BC",
5046 "ldr s16, [x8, x9, LSL #2]",
5047 ));
5048
5049 insns.push((
5050 Inst::FpuLoad64 {
5051 rd: writable_vreg(16),
5052 mem: AMode::RegScaled(xreg(8), xreg(9), F64),
5053 flags: MemFlags::trusted(),
5054 },
5055 "107969FC",
5056 "ldr d16, [x8, x9, LSL #3]",
5057 ));
5058
5059 insns.push((
5060 Inst::FpuLoad128 {
5061 rd: writable_vreg(16),
5062 mem: AMode::RegScaled(xreg(8), xreg(9), I128),
5063 flags: MemFlags::trusted(),
5064 },
5065 "1079E93C",
5066 "ldr q16, [x8, x9, LSL #4]",
5067 ));
5068
5069 insns.push((
5070 Inst::FpuLoad32 {
5071 rd: writable_vreg(16),
5072 mem: AMode::Label(MemLabel::PCRel(8)),
5073 flags: MemFlags::trusted(),
5074 },
5075 "5000001C",
5076 "ldr s16, pc+8",
5077 ));
5078
5079 insns.push((
5080 Inst::FpuLoad64 {
5081 rd: writable_vreg(16),
5082 mem: AMode::Label(MemLabel::PCRel(8)),
5083 flags: MemFlags::trusted(),
5084 },
5085 "5000005C",
5086 "ldr d16, pc+8",
5087 ));
5088
5089 insns.push((
5090 Inst::FpuLoad128 {
5091 rd: writable_vreg(16),
5092 mem: AMode::Label(MemLabel::PCRel(8)),
5093 flags: MemFlags::trusted(),
5094 },
5095 "5000009C",
5096 "ldr q16, pc+8",
5097 ));
5098
5099 insns.push((
5100 Inst::FpuStore32 {
5101 rd: vreg(16),
5102 mem: AMode::RegScaled(xreg(8), xreg(9), F32),
5103 flags: MemFlags::trusted(),
5104 },
5105 "107929BC",
5106 "str s16, [x8, x9, LSL #2]",
5107 ));
5108
5109 insns.push((
5110 Inst::FpuStore64 {
5111 rd: vreg(16),
5112 mem: AMode::RegScaled(xreg(8), xreg(9), F64),
5113 flags: MemFlags::trusted(),
5114 },
5115 "107929FC",
5116 "str d16, [x8, x9, LSL #3]",
5117 ));
5118
5119 insns.push((
5120 Inst::FpuStore128 {
5121 rd: vreg(16),
5122 mem: AMode::RegScaled(xreg(8), xreg(9), I128),
5123 flags: MemFlags::trusted(),
5124 },
5125 "1079A93C",
5126 "str q16, [x8, x9, LSL #4]",
5127 ));
5128
5129 insns.push((
5130 Inst::FpuLoadP64 {
5131 rt: writable_vreg(0),
5132 rt2: writable_vreg(31),
5133 mem: PairAMode::SignedOffset(xreg(0), SImm7Scaled::zero(F64)),
5134 flags: MemFlags::trusted(),
5135 },
5136 "007C406D",
5137 "ldp d0, d31, [x0]",
5138 ));
5139
5140 insns.push((
5141 Inst::FpuLoadP64 {
5142 rt: writable_vreg(19),
5143 rt2: writable_vreg(11),
5144 mem: PairAMode::PreIndexed(
5145 writable_xreg(25),
5146 SImm7Scaled::maybe_from_i64(-512, F64).unwrap(),
5147 ),
5148 flags: MemFlags::trusted(),
5149 },
5150 "332FE06D",
5151 "ldp d19, d11, [x25, #-512]!",
5152 ));
5153
5154 insns.push((
5155 Inst::FpuLoadP64 {
5156 rt: writable_vreg(7),
5157 rt2: writable_vreg(20),
5158 mem: PairAMode::PostIndexed(
5159 writable_stack_reg(),
5160 SImm7Scaled::maybe_from_i64(64, F64).unwrap(),
5161 ),
5162 flags: MemFlags::trusted(),
5163 },
5164 "E753C46C",
5165 "ldp d7, d20, [sp], #64",
5166 ));
5167
5168 insns.push((
5169 Inst::FpuStoreP64 {
5170 rt: vreg(4),
5171 rt2: vreg(26),
5172 mem: PairAMode::SignedOffset(
5173 stack_reg(),
5174 SImm7Scaled::maybe_from_i64(504, F64).unwrap(),
5175 ),
5176 flags: MemFlags::trusted(),
5177 },
5178 "E4EB1F6D",
5179 "stp d4, d26, [sp, #504]",
5180 ));
5181
5182 insns.push((
5183 Inst::FpuStoreP64 {
5184 rt: vreg(16),
5185 rt2: vreg(8),
5186 mem: PairAMode::PreIndexed(
5187 writable_xreg(15),
5188 SImm7Scaled::maybe_from_i64(48, F64).unwrap(),
5189 ),
5190 flags: MemFlags::trusted(),
5191 },
5192 "F021836D",
5193 "stp d16, d8, [x15, #48]!",
5194 ));
5195
5196 insns.push((
5197 Inst::FpuStoreP64 {
5198 rt: vreg(5),
5199 rt2: vreg(6),
5200 mem: PairAMode::PostIndexed(
5201 writable_xreg(28),
5202 SImm7Scaled::maybe_from_i64(-32, F64).unwrap(),
5203 ),
5204 flags: MemFlags::trusted(),
5205 },
5206 "851BBE6C",
5207 "stp d5, d6, [x28], #-32",
5208 ));
5209
5210 insns.push((
5211 Inst::FpuLoadP128 {
5212 rt: writable_vreg(0),
5213 rt2: writable_vreg(17),
5214 mem: PairAMode::SignedOffset(xreg(3), SImm7Scaled::zero(I8X16)),
5215 flags: MemFlags::trusted(),
5216 },
5217 "604440AD",
5218 "ldp q0, q17, [x3]",
5219 ));
5220
5221 insns.push((
5222 Inst::FpuLoadP128 {
5223 rt: writable_vreg(29),
5224 rt2: writable_vreg(9),
5225 mem: PairAMode::PreIndexed(
5226 writable_xreg(16),
5227 SImm7Scaled::maybe_from_i64(-1024, I8X16).unwrap(),
5228 ),
5229 flags: MemFlags::trusted(),
5230 },
5231 "1D26E0AD",
5232 "ldp q29, q9, [x16, #-1024]!",
5233 ));
5234
5235 insns.push((
5236 Inst::FpuLoadP128 {
5237 rt: writable_vreg(10),
5238 rt2: writable_vreg(20),
5239 mem: PairAMode::PostIndexed(
5240 writable_xreg(26),
5241 SImm7Scaled::maybe_from_i64(256, I8X16).unwrap(),
5242 ),
5243 flags: MemFlags::trusted(),
5244 },
5245 "4A53C8AC",
5246 "ldp q10, q20, [x26], #256",
5247 ));
5248
5249 insns.push((
5250 Inst::FpuStoreP128 {
5251 rt: vreg(9),
5252 rt2: vreg(31),
5253 mem: PairAMode::SignedOffset(
5254 stack_reg(),
5255 SImm7Scaled::maybe_from_i64(1008, I8X16).unwrap(),
5256 ),
5257 flags: MemFlags::trusted(),
5258 },
5259 "E9FF1FAD",
5260 "stp q9, q31, [sp, #1008]",
5261 ));
5262
5263 insns.push((
5264 Inst::FpuStoreP128 {
5265 rt: vreg(27),
5266 rt2: vreg(13),
5267 mem: PairAMode::PreIndexed(
5268 writable_stack_reg(),
5269 SImm7Scaled::maybe_from_i64(-192, I8X16).unwrap(),
5270 ),
5271 flags: MemFlags::trusted(),
5272 },
5273 "FB37BAAD",
5274 "stp q27, q13, [sp, #-192]!",
5275 ));
5276
5277 insns.push((
5278 Inst::FpuStoreP128 {
5279 rt: vreg(18),
5280 rt2: vreg(22),
5281 mem: PairAMode::PostIndexed(
5282 writable_xreg(13),
5283 SImm7Scaled::maybe_from_i64(304, I8X16).unwrap(),
5284 ),
5285 flags: MemFlags::trusted(),
5286 },
5287 "B2D989AC",
5288 "stp q18, q22, [x13], #304",
5289 ));
5290
5291 insns.push((
5292 Inst::LoadFpuConst64 {
5293 rd: writable_vreg(16),
5294 const_data: 1.0_f64.to_bits(),
5295 },
5296 "5000005C03000014000000000000F03F",
5297 "ldr d16, pc+8 ; b 12 ; data.f64 1",
5298 ));
5299
5300 insns.push((
5301 Inst::LoadFpuConst128 {
5302 rd: writable_vreg(5),
5303 const_data: 0x0f0e0d0c0b0a09080706050403020100,
5304 },
5305 "4500009C05000014000102030405060708090A0B0C0D0E0F",
5306 "ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100",
5307 ));
5308
5309 insns.push((
5310 Inst::FpuCSel32 {
5311 rd: writable_vreg(1),
5312 rn: vreg(2),
5313 rm: vreg(3),
5314 cond: Cond::Hi,
5315 },
5316 "418C231E",
5317 "fcsel s1, s2, s3, hi",
5318 ));
5319
5320 insns.push((
5321 Inst::FpuCSel64 {
5322 rd: writable_vreg(1),
5323 rn: vreg(2),
5324 rm: vreg(3),
5325 cond: Cond::Eq,
5326 },
5327 "410C631E",
5328 "fcsel d1, d2, d3, eq",
5329 ));
5330
5331 insns.push((
5332 Inst::FpuRound {
5333 rd: writable_vreg(23),
5334 rn: vreg(24),
5335 op: FpuRoundMode::Minus32,
5336 },
5337 "1743251E",
5338 "frintm s23, s24",
5339 ));
5340 insns.push((
5341 Inst::FpuRound {
5342 rd: writable_vreg(23),
5343 rn: vreg(24),
5344 op: FpuRoundMode::Minus64,
5345 },
5346 "1743651E",
5347 "frintm d23, d24",
5348 ));
5349 insns.push((
5350 Inst::FpuRound {
5351 rd: writable_vreg(23),
5352 rn: vreg(24),
5353 op: FpuRoundMode::Plus32,
5354 },
5355 "17C3241E",
5356 "frintp s23, s24",
5357 ));
5358 insns.push((
5359 Inst::FpuRound {
5360 rd: writable_vreg(23),
5361 rn: vreg(24),
5362 op: FpuRoundMode::Plus64,
5363 },
5364 "17C3641E",
5365 "frintp d23, d24",
5366 ));
5367 insns.push((
5368 Inst::FpuRound {
5369 rd: writable_vreg(23),
5370 rn: vreg(24),
5371 op: FpuRoundMode::Zero32,
5372 },
5373 "17C3251E",
5374 "frintz s23, s24",
5375 ));
5376 insns.push((
5377 Inst::FpuRound {
5378 rd: writable_vreg(23),
5379 rn: vreg(24),
5380 op: FpuRoundMode::Zero64,
5381 },
5382 "17C3651E",
5383 "frintz d23, d24",
5384 ));
5385 insns.push((
5386 Inst::FpuRound {
5387 rd: writable_vreg(23),
5388 rn: vreg(24),
5389 op: FpuRoundMode::Nearest32,
5390 },
5391 "1743241E",
5392 "frintn s23, s24",
5393 ));
5394 insns.push((
5395 Inst::FpuRound {
5396 rd: writable_vreg(23),
5397 rn: vreg(24),
5398 op: FpuRoundMode::Nearest64,
5399 },
5400 "1743641E",
5401 "frintn d23, d24",
5402 ));
5403
5404 insns.push((
5405 Inst::AtomicRMW {
5406 ty: I16,
5407 op: inst_common::AtomicRmwOp::Xor,
5408 },
5409 "BF3B03D53B7F5F487C031ACA3C7F1848B8FFFFB5BF3B03D5",
5410 "atomically { 16_bits_at_[x25]) Xor= x26 ; x27 = old_value_at_[x25]; x24,x28 = trash }",
5411 ));
5412
5413 insns.push((
5414 Inst::AtomicRMW {
5415 ty: I32,
5416 op: inst_common::AtomicRmwOp::Xchg,
5417 },
5418 "BF3B03D53B7F5F88FC031AAA3C7F1888B8FFFFB5BF3B03D5",
5419 "atomically { 32_bits_at_[x25]) Xchg= x26 ; x27 = old_value_at_[x25]; x24,x28 = trash }",
5420 ));
5421 insns.push((
5422 Inst::AtomicCAS {
5423 rs: writable_xreg(28),
5424 rt: xreg(20),
5425 rn: xreg(10),
5426 ty: I8,
5427 },
5428 "54FDFC08",
5429 "casalb w28, w20, [x10]",
5430 ));
5431 insns.push((
5432 Inst::AtomicCAS {
5433 rs: writable_xreg(2),
5434 rt: xreg(19),
5435 rn: xreg(23),
5436 ty: I16,
5437 },
5438 "F3FEE248",
5439 "casalh w2, w19, [x23]",
5440 ));
5441 insns.push((
5442 Inst::AtomicCAS {
5443 rs: writable_xreg(0),
5444 rt: zero_reg(),
5445 rn: stack_reg(),
5446 ty: I32,
5447 },
5448 "FFFFE088",
5449 "casal w0, wzr, [sp]",
5450 ));
5451 insns.push((
5452 Inst::AtomicCAS {
5453 rs: writable_xreg(7),
5454 rt: xreg(15),
5455 rn: xreg(27),
5456 ty: I64,
5457 },
5458 "6FFFE7C8",
5459 "casal x7, x15, [x27]",
5460 ));
5461 insns.push((
5462 Inst::AtomicCASLoop {
5463 ty: I8,
5464 },
5465 "BF3B03D53B7F5F08581F40927F0318EB610000543C7F180878FFFFB5BF3B03D5",
5466 "atomically { compare-and-swap(8_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }"
5467 ));
5468
5469 insns.push((
5470 Inst::AtomicCASLoop {
5471 ty: I64,
5472 },
5473 "BF3B03D53B7F5FC8F8031AAA7F0318EB610000543C7F18C878FFFFB5BF3B03D5",
5474 "atomically { compare-and-swap(64_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }"
5475 ));
5476
5477 insns.push((
5478 Inst::AtomicLoad {
5479 ty: I8,
5480 r_data: writable_xreg(7),
5481 r_addr: xreg(28),
5482 },
5483 "BF3B03D587034039",
5484 "atomically { x7 = zero_extend_8_bits_at[x28] }",
5485 ));
5486
5487 insns.push((
5488 Inst::AtomicLoad {
5489 ty: I64,
5490 r_data: writable_xreg(28),
5491 r_addr: xreg(7),
5492 },
5493 "BF3B03D5FC0040F9",
5494 "atomically { x28 = zero_extend_64_bits_at[x7] }",
5495 ));
5496
5497 insns.push((
5498 Inst::AtomicStore {
5499 ty: I16,
5500 r_data: xreg(17),
5501 r_addr: xreg(8),
5502 },
5503 "11010079BF3B03D5",
5504 "atomically { 16_bits_at[x8] = x17 }",
5505 ));
5506
5507 insns.push((
5508 Inst::AtomicStore {
5509 ty: I32,
5510 r_data: xreg(18),
5511 r_addr: xreg(7),
5512 },
5513 "F20000B9BF3B03D5",
5514 "atomically { 32_bits_at[x7] = x18 }",
5515 ));
5516
5517 insns.push((Inst::Fence {}, "BF3B03D5", "dmb ish"));
5518
5519 let flags = settings::Flags::new(settings::builder());
5520 let rru = create_reg_universe(&flags);
5521 let emit_info = EmitInfo::new(flags);
5522 for (insn, expected_encoding, expected_printing) in insns {
5523 println!(
5524 "AArch64: {:?}, {}, {}",
5525 insn, expected_encoding, expected_printing
5526 );
5527
5528 // Check the printed text is as expected.
5529 let actual_printing = insn.show_rru(Some(&rru));
5530 assert_eq!(expected_printing, actual_printing);
5531
5532 let mut sink = test_utils::TestCodeSink::new();
5533 let mut buffer = MachBuffer::new();
5534 insn.emit(&mut buffer, &emit_info, &mut Default::default());
5535 let buffer = buffer.finish();
5536 buffer.emit(&mut sink);
5537 let actual_encoding = &sink.stringify();
5538 assert_eq!(expected_encoding, actual_encoding);
5539 }
5540 }
5541
5542 #[test]
test_cond_invert()5543 fn test_cond_invert() {
5544 for cond in vec![
5545 Cond::Eq,
5546 Cond::Ne,
5547 Cond::Hs,
5548 Cond::Lo,
5549 Cond::Mi,
5550 Cond::Pl,
5551 Cond::Vs,
5552 Cond::Vc,
5553 Cond::Hi,
5554 Cond::Ls,
5555 Cond::Ge,
5556 Cond::Lt,
5557 Cond::Gt,
5558 Cond::Le,
5559 Cond::Al,
5560 Cond::Nv,
5561 ]
5562 .into_iter()
5563 {
5564 assert_eq!(cond.invert().invert(), cond);
5565 }
5566 }
5567