1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions
6 // are met:
7 //
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
10 //
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
14 // distribution.
15 //
16 // - Neither the name of Sun Microsystems or the names of contributors may
17 // be used to endorse or promote products derived from this software without
18 // specific prior written permission.
19 //
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE.
32
33 // The original source code covered by the above license above has been modified
34 // significantly by Google Inc.
35 // Copyright 2014 the V8 project authors. All rights reserved.
36
37 #ifndef V8_CODEGEN_S390_ASSEMBLER_S390_INL_H_
38 #define V8_CODEGEN_S390_ASSEMBLER_S390_INL_H_
39
40 #include "src/codegen/s390/assembler-s390.h"
41
42 #include "src/codegen/assembler.h"
43 #include "src/debug/debug.h"
44 #include "src/objects/objects-inl.h"
45
46 namespace v8 {
47 namespace internal {
48
SupportsOptimizer()49 bool CpuFeatures::SupportsOptimizer() { return true; }
50
SupportsWasmSimd128()51 bool CpuFeatures::SupportsWasmSimd128() {
52 return CpuFeatures::IsSupported(VECTOR_ENHANCE_FACILITY_1);
53 }
54
apply(intptr_t delta)55 void RelocInfo::apply(intptr_t delta) {
56 // Absolute code pointer inside code object moves with the code object.
57 if (IsInternalReference(rmode_)) {
58 // Jump table entry
59 Address target = Memory<Address>(pc_);
60 Memory<Address>(pc_) = target + delta;
61 } else if (IsCodeTarget(rmode_)) {
62 SixByteInstr instr =
63 Instruction::InstructionBits(reinterpret_cast<const byte*>(pc_));
64 int32_t dis = static_cast<int32_t>(instr & 0xFFFFFFFF) * 2 // halfwords
65 - static_cast<int32_t>(delta);
66 instr >>= 32; // Clear the 4-byte displacement field.
67 instr <<= 32;
68 instr |= static_cast<uint32_t>(dis / 2);
69 Instruction::SetInstructionBits<SixByteInstr>(reinterpret_cast<byte*>(pc_),
70 instr);
71 } else {
72 // mov sequence
73 DCHECK(IsInternalReferenceEncoded(rmode_));
74 Address target = Assembler::target_address_at(pc_, constant_pool_);
75 Assembler::set_target_address_at(pc_, constant_pool_, target + delta,
76 SKIP_ICACHE_FLUSH);
77 }
78 }
79
target_internal_reference()80 Address RelocInfo::target_internal_reference() {
81 if (IsInternalReference(rmode_)) {
82 // Jump table entry
83 return Memory<Address>(pc_);
84 } else {
85 // mov sequence
86 DCHECK(IsInternalReferenceEncoded(rmode_));
87 return Assembler::target_address_at(pc_, constant_pool_);
88 }
89 }
90
target_internal_reference_address()91 Address RelocInfo::target_internal_reference_address() {
92 DCHECK(IsInternalReference(rmode_) || IsInternalReferenceEncoded(rmode_));
93 return pc_;
94 }
95
target_address()96 Address RelocInfo::target_address() {
97 DCHECK(IsRelativeCodeTarget(rmode_) || IsCodeTarget(rmode_) ||
98 IsRuntimeEntry(rmode_) || IsWasmCall(rmode_));
99 return Assembler::target_address_at(pc_, constant_pool_);
100 }
101
target_address_address()102 Address RelocInfo::target_address_address() {
103 DCHECK(HasTargetAddressAddress());
104
105 // Read the address of the word containing the target_address in an
106 // instruction stream.
107 // The only architecture-independent user of this function is the serializer.
108 // The serializer uses it to find out how many raw bytes of instruction to
109 // output before the next target.
110 // For an instruction like LIS/ORI where the target bits are mixed into the
111 // instruction bits, the size of the target will be zero, indicating that the
112 // serializer should not step forward in memory after a target is resolved
113 // and written.
114 return pc_;
115 }
116
constant_pool_entry_address()117 Address RelocInfo::constant_pool_entry_address() { UNREACHABLE(); }
118
set_target_compressed_address_at(Address pc,Address constant_pool,Tagged_t target,ICacheFlushMode icache_flush_mode)119 void Assembler::set_target_compressed_address_at(
120 Address pc, Address constant_pool, Tagged_t target,
121 ICacheFlushMode icache_flush_mode) {
122 Assembler::set_target_address_at(
123 pc, constant_pool, static_cast<Address>(target), icache_flush_mode);
124 }
125
target_address_size()126 int RelocInfo::target_address_size() {
127 if (IsCodedSpecially()) {
128 return Assembler::kSpecialTargetSize;
129 } else {
130 return kSystemPointerSize;
131 }
132 }
133
target_compressed_address_at(Address pc,Address constant_pool)134 Tagged_t Assembler::target_compressed_address_at(Address pc,
135 Address constant_pool) {
136 return static_cast<Tagged_t>(target_address_at(pc, constant_pool));
137 }
138
code_target_object_handle_at(Address pc)139 Handle<Object> Assembler::code_target_object_handle_at(Address pc) {
140 SixByteInstr instr =
141 Instruction::InstructionBits(reinterpret_cast<const byte*>(pc));
142 int index = instr & 0xFFFFFFFF;
143 return GetCodeTarget(index);
144 }
145
target_object()146 HeapObject RelocInfo::target_object() {
147 DCHECK(IsCodeTarget(rmode_) || IsEmbeddedObjectMode(rmode_));
148 if (IsCompressedEmbeddedObject(rmode_)) {
149 return HeapObject::cast(Object(DecompressTaggedAny(
150 host_.address(),
151 Assembler::target_compressed_address_at(pc_, constant_pool_))));
152 } else {
153 return HeapObject::cast(
154 Object(Assembler::target_address_at(pc_, constant_pool_)));
155 }
156 }
157
target_object_no_host(Isolate * isolate)158 HeapObject RelocInfo::target_object_no_host(Isolate* isolate) {
159 if (IsCompressedEmbeddedObject(rmode_)) {
160 return HeapObject::cast(Object(DecompressTaggedAny(
161 isolate,
162 Assembler::target_compressed_address_at(pc_, constant_pool_))));
163 } else {
164 return target_object();
165 }
166 }
167
compressed_embedded_object_handle_at(Address pc,Address const_pool)168 Handle<HeapObject> Assembler::compressed_embedded_object_handle_at(
169 Address pc, Address const_pool) {
170 return GetEmbeddedObject(target_compressed_address_at(pc, const_pool));
171 }
172
target_object_handle(Assembler * origin)173 Handle<HeapObject> RelocInfo::target_object_handle(Assembler* origin) {
174 DCHECK(IsRelativeCodeTarget(rmode_) || IsCodeTarget(rmode_) ||
175 IsEmbeddedObjectMode(rmode_));
176 if (IsCodeTarget(rmode_) || IsRelativeCodeTarget(rmode_)) {
177 return Handle<HeapObject>::cast(origin->code_target_object_handle_at(pc_));
178 } else {
179 if (IsCompressedEmbeddedObject(rmode_)) {
180 return origin->compressed_embedded_object_handle_at(pc_, constant_pool_);
181 }
182 return Handle<HeapObject>(reinterpret_cast<Address*>(
183 Assembler::target_address_at(pc_, constant_pool_)));
184 }
185 }
186
set_target_object(Heap * heap,HeapObject target,WriteBarrierMode write_barrier_mode,ICacheFlushMode icache_flush_mode)187 void RelocInfo::set_target_object(Heap* heap, HeapObject target,
188 WriteBarrierMode write_barrier_mode,
189 ICacheFlushMode icache_flush_mode) {
190 DCHECK(IsCodeTarget(rmode_) || IsEmbeddedObjectMode(rmode_));
191 if (IsCompressedEmbeddedObject(rmode_)) {
192 Assembler::set_target_compressed_address_at(
193 pc_, constant_pool_, CompressTagged(target.ptr()), icache_flush_mode);
194 } else {
195 DCHECK(IsFullEmbeddedObject(rmode_));
196 Assembler::set_target_address_at(pc_, constant_pool_, target.ptr(),
197 icache_flush_mode);
198 }
199 if (write_barrier_mode == UPDATE_WRITE_BARRIER && !host().is_null() &&
200 !FLAG_disable_write_barriers) {
201 WriteBarrierForCode(host(), this, target);
202 }
203 }
204
target_external_reference()205 Address RelocInfo::target_external_reference() {
206 DCHECK(rmode_ == EXTERNAL_REFERENCE);
207 return Assembler::target_address_at(pc_, constant_pool_);
208 }
209
set_target_external_reference(Address target,ICacheFlushMode icache_flush_mode)210 void RelocInfo::set_target_external_reference(
211 Address target, ICacheFlushMode icache_flush_mode) {
212 DCHECK(rmode_ == RelocInfo::EXTERNAL_REFERENCE);
213 Assembler::set_target_address_at(pc_, constant_pool_, target,
214 icache_flush_mode);
215 }
216
target_runtime_entry(Assembler * origin)217 Address RelocInfo::target_runtime_entry(Assembler* origin) {
218 DCHECK(IsRuntimeEntry(rmode_));
219 return target_address();
220 }
221
target_off_heap_target()222 Address RelocInfo::target_off_heap_target() {
223 DCHECK(IsOffHeapTarget(rmode_));
224 return Assembler::target_address_at(pc_, constant_pool_);
225 }
226
set_target_runtime_entry(Address target,WriteBarrierMode write_barrier_mode,ICacheFlushMode icache_flush_mode)227 void RelocInfo::set_target_runtime_entry(Address target,
228 WriteBarrierMode write_barrier_mode,
229 ICacheFlushMode icache_flush_mode) {
230 DCHECK(IsRuntimeEntry(rmode_));
231 if (target_address() != target)
232 set_target_address(target, write_barrier_mode, icache_flush_mode);
233 }
234
WipeOut()235 void RelocInfo::WipeOut() {
236 DCHECK(IsEmbeddedObjectMode(rmode_) || IsCodeTarget(rmode_) ||
237 IsRuntimeEntry(rmode_) || IsExternalReference(rmode_) ||
238 IsInternalReference(rmode_) || IsInternalReferenceEncoded(rmode_) ||
239 IsOffHeapTarget(rmode_));
240 if (IsInternalReference(rmode_)) {
241 // Jump table entry
242 Memory<Address>(pc_) = kNullAddress;
243 } else if (IsCompressedEmbeddedObject(rmode_)) {
244 Assembler::set_target_compressed_address_at(pc_, constant_pool_,
245 kNullAddress);
246 } else if (IsInternalReferenceEncoded(rmode_) || IsOffHeapTarget(rmode_)) {
247 // mov sequence
248 // Currently used only by deserializer, no need to flush.
249 Assembler::set_target_address_at(pc_, constant_pool_, kNullAddress,
250 SKIP_ICACHE_FLUSH);
251 } else {
252 Assembler::set_target_address_at(pc_, constant_pool_, kNullAddress);
253 }
254 }
255
256 // Operand constructors
Operand(Register rm)257 Operand::Operand(Register rm) : rm_(rm), rmode_(RelocInfo::NONE) {}
258
259 // Fetch the 32bit value from the FIXED_SEQUENCE IIHF / IILF
target_address_at(Address pc,Address constant_pool)260 Address Assembler::target_address_at(Address pc, Address constant_pool) {
261 // S390 Instruction!
262 // We want to check for instructions generated by Asm::mov()
263 Opcode op1 = Instruction::S390OpcodeValue(reinterpret_cast<const byte*>(pc));
264 SixByteInstr instr_1 =
265 Instruction::InstructionBits(reinterpret_cast<const byte*>(pc));
266
267 if (BRASL == op1 || BRCL == op1) {
268 int32_t dis = static_cast<int32_t>(instr_1 & 0xFFFFFFFF) * 2;
269 return pc + dis;
270 }
271
272 #if V8_TARGET_ARCH_S390X
273 int instr1_length =
274 Instruction::InstructionLength(reinterpret_cast<const byte*>(pc));
275 Opcode op2 = Instruction::S390OpcodeValue(
276 reinterpret_cast<const byte*>(pc + instr1_length));
277 SixByteInstr instr_2 = Instruction::InstructionBits(
278 reinterpret_cast<const byte*>(pc + instr1_length));
279 // IIHF for hi_32, IILF for lo_32
280 if (IIHF == op1 && IILF == op2) {
281 return static_cast<Address>(((instr_1 & 0xFFFFFFFF) << 32) |
282 ((instr_2 & 0xFFFFFFFF)));
283 }
284 #else
285 // IILF loads 32-bits
286 if (IILF == op1 || CFI == op1) {
287 return static_cast<Address>((instr_1 & 0xFFFFFFFF));
288 }
289 #endif
290
291 UNIMPLEMENTED();
292 return 0;
293 }
294
295 // This sets the branch destination (which gets loaded at the call address).
296 // This is for calls and branches within generated code. The serializer
297 // has already deserialized the mov instructions etc.
298 // There is a FIXED_SEQUENCE assumption here
deserialization_set_special_target_at(Address instruction_payload,Code code,Address target)299 void Assembler::deserialization_set_special_target_at(
300 Address instruction_payload, Code code, Address target) {
301 set_target_address_at(instruction_payload,
302 !code.is_null() ? code.constant_pool() : kNullAddress,
303 target);
304 }
305
deserialization_special_target_size(Address instruction_payload)306 int Assembler::deserialization_special_target_size(
307 Address instruction_payload) {
308 return kSpecialTargetSize;
309 }
310
deserialization_set_target_internal_reference_at(Address pc,Address target,RelocInfo::Mode mode)311 void Assembler::deserialization_set_target_internal_reference_at(
312 Address pc, Address target, RelocInfo::Mode mode) {
313 if (RelocInfo::IsInternalReferenceEncoded(mode)) {
314 set_target_address_at(pc, kNullAddress, target, SKIP_ICACHE_FLUSH);
315 } else {
316 Memory<Address>(pc) = target;
317 }
318 }
319
320 // This code assumes the FIXED_SEQUENCE of IIHF/IILF
set_target_address_at(Address pc,Address constant_pool,Address target,ICacheFlushMode icache_flush_mode)321 void Assembler::set_target_address_at(Address pc, Address constant_pool,
322 Address target,
323 ICacheFlushMode icache_flush_mode) {
324 // Check for instructions generated by Asm::mov()
325 Opcode op1 = Instruction::S390OpcodeValue(reinterpret_cast<const byte*>(pc));
326 SixByteInstr instr_1 =
327 Instruction::InstructionBits(reinterpret_cast<const byte*>(pc));
328 bool patched = false;
329
330 if (BRASL == op1 || BRCL == op1) {
331 instr_1 >>= 32; // Zero out the lower 32-bits
332 instr_1 <<= 32;
333 int32_t halfwords = (target - pc) / 2; // number of halfwords
334 instr_1 |= static_cast<uint32_t>(halfwords);
335 Instruction::SetInstructionBits<SixByteInstr>(reinterpret_cast<byte*>(pc),
336 instr_1);
337 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
338 FlushInstructionCache(pc, 6);
339 }
340 patched = true;
341 } else {
342 #if V8_TARGET_ARCH_S390X
343 int instr1_length =
344 Instruction::InstructionLength(reinterpret_cast<const byte*>(pc));
345 Opcode op2 = Instruction::S390OpcodeValue(
346 reinterpret_cast<const byte*>(pc + instr1_length));
347 SixByteInstr instr_2 = Instruction::InstructionBits(
348 reinterpret_cast<const byte*>(pc + instr1_length));
349 // IIHF for hi_32, IILF for lo_32
350 if (IIHF == op1 && IILF == op2) {
351 // IIHF
352 instr_1 >>= 32; // Zero out the lower 32-bits
353 instr_1 <<= 32;
354 instr_1 |= reinterpret_cast<uint64_t>(target) >> 32;
355
356 Instruction::SetInstructionBits<SixByteInstr>(reinterpret_cast<byte*>(pc),
357 instr_1);
358
359 // IILF
360 instr_2 >>= 32;
361 instr_2 <<= 32;
362 instr_2 |= reinterpret_cast<uint64_t>(target) & 0xFFFFFFFF;
363
364 Instruction::SetInstructionBits<SixByteInstr>(
365 reinterpret_cast<byte*>(pc + instr1_length), instr_2);
366 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
367 FlushInstructionCache(pc, 12);
368 }
369 patched = true;
370 }
371 #else
372 // IILF loads 32-bits
373 if (IILF == op1 || CFI == op1) {
374 instr_1 >>= 32; // Zero out the lower 32-bits
375 instr_1 <<= 32;
376 instr_1 |= reinterpret_cast<uint32_t>(target);
377
378 Instruction::SetInstructionBits<SixByteInstr>(reinterpret_cast<byte*>(pc),
379 instr_1);
380 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
381 FlushInstructionCache(pc, 6);
382 }
383 patched = true;
384 }
385 #endif
386 }
387 if (!patched) UNREACHABLE();
388 }
389
390 } // namespace internal
391 } // namespace v8
392
393 #endif // V8_CODEGEN_S390_ASSEMBLER_S390_INL_H_
394