1 /* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
2 * All rights reserved.
3 *
4 * This package is an SSL implementation written
5 * by Eric Young (eay@cryptsoft.com).
6 * The implementation was written so as to conform with Netscapes SSL.
7 *
8 * This library is free for commercial and non-commercial use as long as
9 * the following conditions are aheared to. The following conditions
10 * apply to all code found in this distribution, be it the RC4, RSA,
11 * lhash, DES, etc., code; not just the SSL code. The SSL documentation
12 * included with this distribution is covered by the same copyright terms
13 * except that the holder is Tim Hudson (tjh@cryptsoft.com).
14 *
15 * Copyright remains Eric Young's, and as such any Copyright notices in
16 * the code are not to be removed.
17 * If this package is used in a product, Eric Young should be given attribution
18 * as the author of the parts of the library used.
19 * This can be in the form of a textual message at program startup or
20 * in documentation (online or textual) provided with the package.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 * 1. Redistributions of source code must retain the copyright
26 * notice, this list of conditions and the following disclaimer.
27 * 2. Redistributions in binary form must reproduce the above copyright
28 * notice, this list of conditions and the following disclaimer in the
29 * documentation and/or other materials provided with the distribution.
30 * 3. All advertising materials mentioning features or use of this software
31 * must display the following acknowledgement:
32 * "This product includes cryptographic software written by
33 * Eric Young (eay@cryptsoft.com)"
34 * The word 'cryptographic' can be left out if the rouines from the library
35 * being used are not cryptographic related :-).
36 * 4. If you include any Windows specific code (or a derivative thereof) from
37 * the apps directory (application code) you must include an acknowledgement:
38 * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
39 *
40 * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
50 * SUCH DAMAGE.
51 *
52 * The licence and distribution terms for any publically available version or
53 * derivative of this code cannot be changed. i.e. this code cannot simply be
54 * copied and put under another distribution licence
55 * [including the GNU Public Licence.] */
56
57 #include <GFp/cpu.h>
58
59
60 #if !defined(OPENSSL_NO_ASM) && (defined(OPENSSL_X86) || defined(OPENSSL_X86_64))
61
62 #if defined(_MSC_VER) && !defined(__clang__)
63 #pragma warning(push, 3)
64 #include <immintrin.h>
65 #include <intrin.h>
66 #pragma warning(pop)
67 #endif
68
69 #include "internal.h"
70
71
72 // OPENSSL_cpuid runs the cpuid instruction. |leaf| is passed in as EAX and ECX
73 // is set to zero. It writes EAX, EBX, ECX, and EDX to |*out_eax| through
74 // |*out_edx|.
OPENSSL_cpuid(uint32_t * out_eax,uint32_t * out_ebx,uint32_t * out_ecx,uint32_t * out_edx,uint32_t leaf)75 static void OPENSSL_cpuid(uint32_t *out_eax, uint32_t *out_ebx,
76 uint32_t *out_ecx, uint32_t *out_edx, uint32_t leaf) {
77 #if defined(_MSC_VER) && !defined(__clang__)
78 int tmp[4];
79 __cpuid(tmp, (int)leaf);
80 *out_eax = (uint32_t)tmp[0];
81 *out_ebx = (uint32_t)tmp[1];
82 *out_ecx = (uint32_t)tmp[2];
83 *out_edx = (uint32_t)tmp[3];
84 #elif defined(__pic__) && defined(OPENSSL_32_BIT)
85 // Inline assembly may not clobber the PIC register. For 32-bit, this is EBX.
86 // See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=47602.
87 __asm__ volatile (
88 "xor %%ecx, %%ecx\n"
89 "mov %%ebx, %%edi\n"
90 "cpuid\n"
91 "xchg %%edi, %%ebx\n"
92 : "=a"(*out_eax), "=D"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
93 : "a"(leaf)
94 );
95 #else
96 __asm__ volatile (
97 "xor %%ecx, %%ecx\n"
98 "cpuid\n"
99 : "=a"(*out_eax), "=b"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
100 : "a"(leaf)
101 );
102 #endif
103 }
104
105 // OPENSSL_xgetbv returns the value of an Intel Extended Control Register (XCR).
106 // Currently only XCR0 is defined by Intel so |xcr| should always be zero.
107 //
108 // See https://software.intel.com/en-us/articles/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family
OPENSSL_xgetbv(uint32_t xcr)109 static uint64_t OPENSSL_xgetbv(uint32_t xcr) {
110 #if defined(_MSC_VER) && !defined(__clang__)
111 return (uint64_t)_xgetbv(xcr);
112 #else
113 uint32_t eax, edx;
114 __asm__ volatile ("xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
115 return (((uint64_t)edx) << 32) | eax;
116 #endif
117 }
118
GFp_cpuid_setup(void)119 void GFp_cpuid_setup(void) {
120 // Determine the vendor and maximum input value.
121 uint32_t eax, ebx, ecx, edx;
122 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0);
123
124 uint32_t num_ids = eax;
125
126 int is_intel = ebx == 0x756e6547 /* Genu */ &&
127 edx == 0x49656e69 /* ineI */ &&
128 ecx == 0x6c65746e /* ntel */;
129
130 uint32_t extended_features[2] = {0};
131 if (num_ids >= 7) {
132 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 7);
133 extended_features[0] = ebx;
134 extended_features[1] = ecx;
135 }
136
137 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 1);
138
139 // Force the hyper-threading bit so that the more conservative path is always
140 // chosen.
141 edx |= 1u << 28;
142
143 // Reserved bit #20 was historically repurposed to control the in-memory
144 // representation of RC4 state. Always set it to zero.
145 edx &= ~(1u << 20);
146
147 // Reserved bit #30 is repurposed to signal an Intel CPU.
148 if (is_intel) {
149 edx |= (1u << 30);
150
151 // Clear the XSAVE bit on Knights Landing to mimic Silvermont. This enables
152 // some Silvermont-specific codepaths which perform better. See OpenSSL
153 // commit 64d92d74985ebb3d0be58a9718f9e080a14a8e7f.
154 if ((eax & 0x0fff0ff0) == 0x00050670 /* Knights Landing */ ||
155 (eax & 0x0fff0ff0) == 0x00080650 /* Knights Mill (per SDE) */) {
156 ecx &= ~(1u << 26);
157 }
158 } else {
159 edx &= ~(1u << 30);
160 }
161
162 // The SDBG bit is repurposed to denote AMD XOP support. Don't ever use AMD
163 // XOP code paths.
164 ecx &= ~(1u << 11);
165
166 uint64_t xcr0 = 0;
167 if (ecx & (1u << 27)) {
168 // XCR0 may only be queried if the OSXSAVE bit is set.
169 xcr0 = OPENSSL_xgetbv(0);
170 }
171 // See Intel manual, volume 1, section 14.3.
172 if ((xcr0 & 6) != 6) {
173 // YMM registers cannot be used.
174 ecx &= ~(1u << 28); // AVX
175 ecx &= ~(1u << 12); // FMA
176 ecx &= ~(1u << 11); // AMD XOP
177 // Clear AVX2 and AVX512* bits.
178 //
179 // TODO(davidben): Should bits 17 and 26-28 also be cleared? Upstream
180 // doesn't clear those.
181 extended_features[0] &=
182 ~((1u << 5) | (1u << 16) | (1u << 21) | (1u << 30) | (1u << 31));
183 }
184 // See Intel manual, volume 1, section 15.2.
185 if ((xcr0 & 0xe6) != 0xe6) {
186 // Clear AVX512F. Note we don't touch other AVX512 extensions because they
187 // can be used with YMM.
188 extended_features[0] &= ~(1u << 16);
189 }
190
191 // Disable ADX instructions on Knights Landing. See OpenSSL commit
192 // 64d92d74985ebb3d0be58a9718f9e080a14a8e7f.
193 if ((ecx & (1u << 26)) == 0) {
194 extended_features[0] &= ~(1u << 19);
195 }
196
197 GFp_ia32cap_P[0] = edx;
198 GFp_ia32cap_P[1] = ecx;
199 GFp_ia32cap_P[2] = extended_features[0];
200 GFp_ia32cap_P[3] = extended_features[1];
201 }
202
203 #endif // !OPENSSL_NO_ASM && (OPENSSL_X86 || OPENSSL_X86_64)
204