1 /*
2 * Copyright 2010 NVIDIA Corporation
3 * Copyright 1996-1997 David J. McKay
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 /* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen
29 <jpaana@s2.org> */
30
31 #include "nv_include.h"
32
33 #include "xf86int10.h"
34 #include "vbeModes.h"
35
36 const OptionInfoRec * RivaAvailableOptions(int chipid, int busid);
37 Bool RivaGetScrnInfoRec(PciChipsets *chips, int chip);
38 Bool G80GetScrnInfoRec(PciChipsets *chips, int chip);
39
40 /*
41 * Forward definitions for the functions that make up the driver.
42 */
43 /* Mandatory functions */
44 static const OptionInfoRec * NVAvailableOptions(int chipid, int busid);
45 static void NVIdentify(int flags);
46 #if XSERVER_LIBPCIACCESS
47 static Bool NVPciProbe(DriverPtr, int entity, struct pci_device*, intptr_t data);
48 #else
49 static Bool NVProbe(DriverPtr drv, int flags);
50 #endif
51 static Bool NVPreInit(ScrnInfoPtr pScrn, int flags);
52 static Bool NVScreenInit(SCREEN_INIT_ARGS_DECL);
53 static Bool NVEnterVT(VT_FUNC_ARGS_DECL);
54 static Bool NVEnterVTFBDev(VT_FUNC_ARGS_DECL);
55 static void NVLeaveVT(VT_FUNC_ARGS_DECL);
56 static Bool NVCloseScreen(CLOSE_SCREEN_ARGS_DECL);
57 static Bool NVSaveScreen(ScreenPtr pScreen, int mode);
58
59 /* Optional functions */
60 static void NVFreeScreen(FREE_SCREEN_ARGS_DECL);
61 static ModeStatus NVValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode,
62 Bool verbose, int flags);
63 #ifdef RANDR
64 static Bool NVDriverFunc(ScrnInfoPtr pScrnInfo, xorgDriverFuncOp op,
65 pointer data);
66 #endif
67
68 /* Internally used functions */
69
70 static Bool NVMapMem(ScrnInfoPtr pScrn);
71 static Bool NVMapMemFBDev(ScrnInfoPtr pScrn);
72 static Bool NVUnmapMem(ScrnInfoPtr pScrn);
73 static void NVSave(ScrnInfoPtr pScrn);
74 static void NVSaveRestoreVBE(ScrnInfoPtr, vbeSaveRestoreFunction);
75 static void NVRestore(ScrnInfoPtr pScrn);
76 static Bool NVModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode);
77 static Bool NVSetModeVBE(ScrnInfoPtr pScrn, DisplayModePtr pMode);
78
79 #if XSERVER_LIBPCIACCESS
80 /* For now, just match any NVIDIA display device and sort through them in the
81 * probe routine */
82
83 /*
84 * libpciaccess's masks are shifted by 8 bits compared to the ones in xf86Pci.h.
85 */
86 #define LIBPCIACCESS_CLASS_SHIFT (PCI_CLASS_SHIFT - 8)
87 #define LIBPCIACCESS_CLASS_MASK (PCI_CLASS_MASK >> 8)
88
89 static const struct pci_id_match NVPciIdMatchList[] = {
90 { PCI_VENDOR_NVIDIA, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY,
91 PCI_CLASS_DISPLAY << LIBPCIACCESS_CLASS_SHIFT, LIBPCIACCESS_CLASS_MASK, 0 },
92
93 { PCI_VENDOR_NVIDIA_SGS, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY,
94 PCI_CLASS_DISPLAY << LIBPCIACCESS_CLASS_SHIFT, LIBPCIACCESS_CLASS_MASK, 0 },
95
96 { 0, 0, 0 }
97 };
98 #endif
99
100 /*
101 * This contains the functions needed by the server after loading the
102 * driver module. It must be supplied, and gets added the driver list by
103 * the Module Setup funtion in the dynamic case. In the static case a
104 * reference to this is compiled in, and this requires that the name of
105 * this DriverRec be an upper-case version of the driver name.
106 */
107
108 _X_EXPORT DriverRec NV = {
109 NV_VERSION,
110 NV_DRIVER_NAME,
111 NVIdentify,
112 #if XSERVER_LIBPCIACCESS
113 NULL,
114 #else
115 NVProbe,
116 #endif
117 NVAvailableOptions,
118 NULL,
119 0,
120 NULL,
121 #if XSERVER_LIBPCIACCESS
122 NVPciIdMatchList,
123 NVPciProbe,
124 #endif
125 };
126
127 /* Known cards as of 2010/07/19 */
128
129 static SymTabRec NVKnownChipsets[] =
130 {
131 { 0x12D20018, "RIVA 128" },
132
133 { 0x10DE0020, "RIVA TNT" },
134
135 { 0x10DE0028, "RIVA TNT2" },
136 { 0x10DE002A, "Unknown TNT2" },
137 { 0x10DE002C, "Vanta" },
138 { 0x10DE0029, "RIVA TNT2 Ultra" },
139 { 0x10DE002D, "RIVA TNT2 Model 64" },
140
141 { 0x10DE00A0, "Aladdin TNT2" },
142
143 { 0x10DE0100, "GeForce 256" },
144 { 0x10DE0101, "GeForce DDR" },
145 { 0x10DE0103, "Quadro" },
146
147 { 0x10DE0110, "GeForce2 MX/MX 400" },
148 { 0x10DE0111, "GeForce2 MX 100/200" },
149 { 0x10DE0112, "GeForce2 Go" },
150 { 0x10DE0113, "Quadro2 MXR/EX/Go" },
151
152 { 0x10DE01A0, "GeForce2 Integrated GPU" },
153
154 { 0x10DE0150, "GeForce2 GTS" },
155 { 0x10DE0151, "GeForce2 Ti" },
156 { 0x10DE0152, "GeForce2 Ultra" },
157 { 0x10DE0153, "Quadro2 Pro" },
158
159 { 0x10DE0170, "GeForce4 MX 460" },
160 { 0x10DE0171, "GeForce4 MX 440" },
161 { 0x10DE0172, "GeForce4 MX 420" },
162 { 0x10DE0173, "GeForce4 MX 440-SE" },
163 { 0x10DE0174, "GeForce4 440 Go" },
164 { 0x10DE0175, "GeForce4 420 Go" },
165 { 0x10DE0176, "GeForce4 420 Go 32M" },
166 { 0x10DE0177, "GeForce4 460 Go" },
167 { 0x10DE0178, "Quadro4 550 XGL" },
168 #if defined(__powerpc__)
169 { 0x10DE0179, "GeForce4 MX (Mac)" },
170 #else
171 { 0x10DE0179, "GeForce4 440 Go 64M" },
172 #endif
173 { 0x10DE017A, "Quadro NVS" },
174 { 0x10DE017C, "Quadro4 500 GoGL" },
175 { 0x10DE017D, "GeForce4 410 Go 16M" },
176
177 { 0x10DE0181, "GeForce4 MX 440 with AGP8X" },
178 { 0x10DE0182, "GeForce4 MX 440SE with AGP8X" },
179 { 0x10DE0183, "GeForce4 MX 420 with AGP8X" },
180 { 0x10DE0185, "GeForce4 MX 4000" },
181 { 0x10DE0186, "GeForce4 448 Go" },
182 { 0x10DE0187, "GeForce4 488 Go" },
183 { 0x10DE0188, "Quadro4 580 XGL" },
184 #if defined(__powerpc__)
185 { 0x10DE0189, "GeForce4 MX with AGP8X (Mac)" },
186 #endif
187 { 0x10DE018A, "Quadro4 NVS 280 SD" },
188 { 0x10DE018B, "Quadro4 380 XGL" },
189 { 0x10DE018C, "Quadro NVS 50 PCI" },
190 { 0x10DE018D, "GeForce4 448 Go" },
191
192 { 0x10DE01F0, "GeForce4 MX Integrated GPU" },
193
194 { 0x10DE0200, "GeForce3" },
195 { 0x10DE0201, "GeForce3 Ti 200" },
196 { 0x10DE0202, "GeForce3 Ti 500" },
197 { 0x10DE0203, "Quadro DCC" },
198
199 { 0x10DE0250, "GeForce4 Ti 4600" },
200 { 0x10DE0251, "GeForce4 Ti 4400" },
201 { 0x10DE0253, "GeForce4 Ti 4200" },
202 { 0x10DE0258, "Quadro4 900 XGL" },
203 { 0x10DE0259, "Quadro4 750 XGL" },
204 { 0x10DE025B, "Quadro4 700 XGL" },
205
206 { 0x10DE0280, "GeForce4 Ti 4800" },
207 { 0x10DE0281, "GeForce4 Ti 4200 with AGP8X" },
208 { 0x10DE0282, "GeForce4 Ti 4800 SE" },
209 { 0x10DE0286, "GeForce4 4200 Go" },
210 { 0x10DE028C, "Quadro4 700 GoGL" },
211 { 0x10DE0288, "Quadro4 980 XGL" },
212 { 0x10DE0289, "Quadro4 780 XGL" },
213
214 { 0x10DE0301, "GeForce FX 5800 Ultra" },
215 { 0x10DE0302, "GeForce FX 5800" },
216 { 0x10DE0308, "Quadro FX 2000" },
217 { 0x10DE0309, "Quadro FX 1000" },
218
219 { 0x10DE0311, "GeForce FX 5600 Ultra" },
220 { 0x10DE0312, "GeForce FX 5600" },
221 { 0x10DE0314, "GeForce FX 5600XT" },
222 { 0x10DE031A, "GeForce FX Go5600" },
223 { 0x10DE031B, "GeForce FX Go5650" },
224 { 0x10DE031C, "Quadro FX Go700" },
225
226 { 0x10DE0320, "GeForce FX 5200" },
227 { 0x10DE0321, "GeForce FX 5200 Ultra" },
228 { 0x10DE0322, "GeForce FX 5200" },
229 { 0x10DE0323, "GeForce FX 5200LE" },
230 { 0x10DE0324, "GeForce FX Go5200" },
231 { 0x10DE0325, "GeForce FX Go5250" },
232 { 0x10DE0326, "GeForce FX 5500" },
233 { 0x10DE0327, "GeForce FX 5100" },
234 { 0x10DE0328, "GeForce FX Go5200 32M/64M" },
235 #if defined(__powerpc__)
236 { 0x10DE0329, "GeForce FX 5200 (Mac)" },
237 #endif
238 { 0x10DE032A, "Quadro NVS 55/280 PCI" },
239 { 0x10DE032B, "Quadro FX 500/600 PCI" },
240 { 0x10DE032C, "GeForce FX Go53xx Series" },
241 { 0x10DE032D, "GeForce FX Go5100" },
242
243 { 0x10DE0330, "GeForce FX 5900 Ultra" },
244 { 0x10DE0331, "GeForce FX 5900" },
245 { 0x10DE0332, "GeForce FX 5900XT" },
246 { 0x10DE0333, "GeForce FX 5950 Ultra" },
247 { 0x10DE0334, "GeForce FX 5900ZT" },
248 { 0x10DE0338, "Quadro FX 3000" },
249 { 0x10DE033F, "Quadro FX 700" },
250
251 { 0x10DE0341, "GeForce FX 5700 Ultra" },
252 { 0x10DE0342, "GeForce FX 5700" },
253 { 0x10DE0343, "GeForce FX 5700LE" },
254 { 0x10DE0344, "GeForce FX 5700VE" },
255 { 0x10DE0347, "GeForce FX Go5700" },
256 { 0x10DE0348, "GeForce FX Go5700" },
257 { 0x10DE034C, "Quadro FX Go1000" },
258 { 0x10DE034E, "Quadro FX 1100" },
259
260 { 0x10DE0040, "GeForce 6800 Ultra" },
261 { 0x10DE0041, "GeForce 6800" },
262 { 0x10DE0042, "GeForce 6800 LE" },
263 { 0x10DE0043, "GeForce 6800 XE" },
264 { 0x10DE0044, "GeForce 6800 XT" },
265 { 0x10DE0045, "GeForce 6800 GT" },
266 { 0x10DE0046, "GeForce 6800 GT" },
267 { 0x10DE0047, "GeForce 6800 GS" },
268 { 0x10DE0048, "GeForce 6800 XT" },
269 { 0x10DE004E, "Quadro FX 4000" },
270
271 { 0x10DE00C0, "GeForce 6800 GS" },
272 { 0x10DE00C1, "GeForce 6800" },
273 { 0x10DE00C2, "GeForce 6800 LE" },
274 { 0x10DE00C3, "GeForce 6800 XT" },
275 { 0x10DE00C8, "GeForce Go 6800" },
276 { 0x10DE00C9, "GeForce Go 6800 Ultra" },
277 { 0x10DE00CC, "Quadro FX Go1400" },
278 { 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
279 { 0x10DE00CE, "Quadro FX 1400" },
280
281 { 0x10DE0140, "GeForce 6600 GT" },
282 { 0x10DE0141, "GeForce 6600" },
283 { 0x10DE0142, "GeForce 6600 LE" },
284 { 0x10DE0143, "GeForce 6600 VE" },
285 { 0x10DE0144, "GeForce Go 6600" },
286 { 0x10DE0145, "GeForce 6610 XL" },
287 { 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },
288 { 0x10DE0147, "GeForce 6700 XL" },
289 { 0x10DE0148, "GeForce Go 6600" },
290 { 0x10DE0149, "GeForce Go 6600 GT" },
291 { 0x10DE014A, "Quadro NVS 440" },
292 { 0x10DE014C, "Quadro FX 550" },
293 { 0x10DE014D, "Quadro FX 550" },
294 { 0x10DE014E, "Quadro FX 540" },
295 { 0x10DE014F, "GeForce 6200" },
296
297 { 0x10DE0160, "GeForce 6500" },
298 { 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
299 { 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
300 { 0x10DE0163, "GeForce 6200 LE" },
301 { 0x10DE0164, "GeForce Go 6200" },
302 { 0x10DE0165, "Quadro NVS 285" },
303 { 0x10DE0166, "GeForce Go 6400" },
304 { 0x10DE0167, "GeForce Go 6200" },
305 { 0x10DE0168, "GeForce Go 6400" },
306 { 0x10DE0169, "GeForce 6250" },
307 { 0x10DE016A, "GeForce 7100 GS" },
308
309 { 0x10DE0211, "GeForce 6800" },
310 { 0x10DE0212, "GeForce 6800 LE" },
311 { 0x10DE0215, "GeForce 6800 GT" },
312 { 0x10DE0218, "GeForce 6800 XT" },
313
314 { 0x10DE0221, "GeForce 6200" },
315 { 0x10DE0222, "GeForce 6200 A-LE" },
316
317 { 0x10DE0090, "GeForce 7800 GTX" },
318 { 0x10DE0091, "GeForce 7800 GTX" },
319 { 0x10DE0092, "GeForce 7800 GT" },
320 { 0x10DE0093, "GeForce 7800 GS" },
321 { 0x10DE0095, "GeForce 7800 SLI" },
322 { 0x10DE0098, "GeForce Go 7800" },
323 { 0x10DE0099, "GeForce Go 7800 GTX" },
324 { 0x10DE009D, "Quadro FX 4500" },
325
326 { 0x10DE01D0, "GeForce 7350 LE" },
327 { 0x10DE01D1, "GeForce 7300 LE" },
328 { 0x10DE01D3, "GeForce 7300 SE" },
329 { 0x10DE01D6, "GeForce Go 7200" },
330 { 0x10DE01D7, "GeForce Go 7300" },
331 { 0x10DE01D8, "GeForce Go 7400" },
332 { 0x10DE01D9, "GeForce Go 7400 GS" },
333 { 0x10DE01DA, "Quadro NVS 110M" },
334 { 0x10DE01DB, "Quadro NVS 120M" },
335 { 0x10DE01DC, "Quadro FX 350M" },
336 { 0x10DE01DD, "GeForce 7500 LE" },
337 { 0x10DE01DE, "Quadro FX 350" },
338 { 0x10DE01DF, "GeForce 7300 GS" },
339
340 { 0x10DE0390, "GeForce 7650 GS" },
341 { 0x10DE0391, "GeForce 7600 GT" },
342 { 0x10DE0392, "GeForce 7600 GS" },
343 { 0x10DE0393, "GeForce 7300 GT" },
344 { 0x10DE0394, "GeForce 7600 LE" },
345 { 0x10DE0395, "GeForce 7300 GT" },
346 { 0x10DE0397, "GeForce Go 7700" },
347 { 0x10DE0398, "GeForce Go 7600" },
348 { 0x10DE0399, "GeForce Go 7600 GT"},
349 { 0x10DE039A, "Quadro NVS 300M" },
350 { 0x10DE039B, "GeForce Go 7900 SE" },
351 { 0x10DE039C, "Quadro FX 550M" },
352 { 0x10DE039E, "Quadro FX 560" },
353
354 { 0x10DE0290, "GeForce 7900 GTX" },
355 { 0x10DE0291, "GeForce 7900 GT" },
356 { 0x10DE0292, "GeForce 7900 GS" },
357 { 0x10DE0293, "GeForce 7950 GX2" },
358 { 0x10DE0294, "GeForce 7950 GX2" },
359 { 0x10DE0295, "GeForce 7950 GT"},
360 { 0x10DE0297, "GeForce Go 7950 GTX" },
361 { 0x10DE0298, "GeForce Go 7900 GS" },
362 { 0x10DE0299, "GeForce Go 7900 GTX" },
363 { 0x10DE029A, "Quadro FX 2500M" },
364 { 0x10DE029B, "Quadro FX 1500M" },
365 { 0x10DE029C, "Quadro FX 5500" },
366 { 0x10DE029D, "Quadro FX 3500" },
367 { 0x10DE029E, "Quadro FX 1500" },
368 { 0x10DE029F, "Quadro FX 4500 X2" },
369
370 { 0x10DE0240, "GeForce 6150" },
371 { 0x10DE0241, "GeForce 6150 LE" },
372 { 0x10DE0242, "GeForce 6100" },
373 { 0x10DE0244, "GeForce Go 6150" },
374 { 0x10DE0245, "Quadro NVS 210S / NVIDIA GeForce 6150LE" },
375 { 0x10DE0247, "GeForce Go 6100" },
376
377 { 0x10DE03D0, "GeForce 6150SE" },
378 { 0x10DE03D1, "GeForce 6100 nForce 405" },
379 { 0x10DE03D2, "GeForce 6100 nForce 400" },
380 { 0x10DE03D5, "GeForce 6100 nForce 420" },
381
382 { 0x10DE0531, "GeForce 7150M / nForce 630M" },
383 { 0x10DE0533, "GeForce 7000M / nForce 610M" },
384 { 0x10DE053A, "GeForce 7050 PV / nForce 630a" },
385 { 0x10DE053B, "GeForce 7050 PV / nForce 630a" },
386 { 0x10DE053E, "GeForce 7025 / nForce 630a" },
387
388 /*************** G8x ***************/
389 { 0x10DE0191, "GeForce 8800 GTX" },
390 { 0x10DE0193, "GeForce 8800 GTS" },
391 { 0x10DE0194, "GeForce 8800 Ultra" },
392 { 0x10DE019D, "Quadro FX 5600" },
393 { 0x10DE019E, "Quadro FX 4600" },
394 { 0x10DE0400, "GeForce 8600 GTS" },
395 { 0x10DE0401, "GeForce 8600 GT" },
396 { 0x10DE0402, "GeForce 8600 GT" },
397 { 0x10DE0403, "GeForce 8600 GS" },
398 { 0x10DE0404, "GeForce 8400 GS" },
399 { 0x10DE0405, "GeForce 9500M GS" },
400 { 0x10DE0406, "GeForce 8300 GS" },
401 { 0x10DE0407, "GeForce 8600M GT" },
402 { 0x10DE0408, "GeForce 9650M GS" },
403 { 0x10DE0409, "GeForce 8700M GT" },
404 { 0x10DE040A, "Quadro FX 370" },
405 { 0x10DE040B, "Quadro NVS 320M" },
406 { 0x10DE040C, "Quadro FX 570M" },
407 { 0x10DE040D, "Quadro FX 1600M" },
408 { 0x10DE040E, "Quadro FX 570" },
409 { 0x10DE040F, "Quadro FX 1700" },
410 { 0x10DE0410, "GeForce GT 330" },
411 { 0x10DE0420, "GeForce 8400 SE" },
412 { 0x10DE0421, "GeForce 8500 GT" },
413 { 0x10DE0422, "GeForce 8400 GS" },
414 { 0x10DE0423, "GeForce 8300 GS" },
415 { 0x10DE0424, "GeForce 8400 GS" },
416 { 0x10DE0425, "GeForce 8600M GS" },
417 { 0x10DE0426, "GeForce 8400M GT" },
418 { 0x10DE0427, "GeForce 8400M GS" },
419 { 0x10DE0428, "GeForce 8400M G" },
420 { 0x10DE0429, "Quadro NVS 140M" },
421 { 0x10DE042A, "Quadro NVS 130M" },
422 { 0x10DE042B, "Quadro NVS 135M" },
423 { 0x10DE042C, "GeForce 9400 GT" },
424 { 0x10DE042D, "Quadro FX 360M" },
425 { 0x10DE042E, "GeForce 9300M G" },
426 { 0x10DE042F, "Quadro NVS 290" },
427 { 0x10DE05E0, "GeForce GTX 295" },
428 { 0x10DE05E1, "GeForce GTX 280" },
429 { 0x10DE05E2, "GeForce GTX 260" },
430 { 0x10DE05E3, "GeForce GTX 285" },
431 { 0x10DE05E6, "GeForce GTX 275" },
432 { 0x10DE05EA, "GeForce GTX 260" },
433 { 0x10DE05EB, "GeForce GTX 295" },
434 { 0x10DE05ED, "Quadroplex 2200 D2" },
435 { 0x10DE05F8, "Quadroplex 2200 S4" },
436 { 0x10DE05F9, "Quadro CX" },
437 { 0x10DE05FD, "Quadro FX 5800" },
438 { 0x10DE05FE, "Quadro FX 4800" },
439 { 0x10DE05FF, "Quadro FX 3800" },
440 { 0x10DE0600, "GeForce 8800 GTS 512" },
441 { 0x10DE0601, "GeForce 9800 GT" },
442 { 0x10DE0602, "GeForce 8800 GT" },
443 { 0x10DE0603, "GeForce GT 230" },
444 { 0x10DE0604, "GeForce 9800 GX2" },
445 { 0x10DE0605, "GeForce 9800 GT" },
446 { 0x10DE0606, "GeForce 8800 GS" },
447 { 0x10DE0607, "GeForce GTS 240" },
448 { 0x10DE0608, "GeForce 9800M GTX" },
449 { 0x10DE0609, "GeForce 8800M GTS" },
450 { 0x10DE060A, "GeForce GTX 280M" },
451 { 0x10DE060B, "GeForce 9800M GT" },
452 { 0x10DE060C, "GeForce 8800M GTX" },
453 { 0x10DE060D, "GeForce 8800 GS" },
454 { 0x10DE060F, "GeForce GTX 285M" },
455 { 0x10DE0610, "GeForce 9600 GSO" },
456 { 0x10DE0611, "GeForce 8800 GT" },
457 { 0x10DE0612, "GeForce 9800 GTX/9800 GTX+" },
458 { 0x10DE0613, "GeForce 9800 GTX+" },
459 { 0x10DE0614, "GeForce 9800 GT" },
460 { 0x10DE0615, "GeForce GTS 250" },
461 { 0x10DE0617, "GeForce 9800M GTX" },
462 { 0x10DE0618, "GeForce GTX 260M" },
463 { 0x10DE0619, "Quadro FX 4700 X2" },
464 { 0x10DE061A, "Quadro FX 3700" },
465 { 0x10DE061B, "Quadro VX 200" },
466 { 0x10DE061C, "Quadro FX 3600M" },
467 { 0x10DE061D, "Quadro FX 2800M" },
468 { 0x10DE061E, "Quadro FX 3700M" },
469 { 0x10DE061F, "Quadro FX 3800M" },
470 { 0x10DE0622, "GeForce 9600 GT" },
471 { 0x10DE0623, "GeForce 9600 GS" },
472 { 0x10DE0625, "GeForce 9600 GSO 512" },
473 { 0x10DE0626, "GeForce GT 130" },
474 { 0x10DE0627, "GeForce GT 140" },
475 { 0x10DE0628, "GeForce 9800M GTS" },
476 { 0x10DE062A, "GeForce 9700M GTS" },
477 { 0x10DE062B, "GeForce 9800M GS" },
478 { 0x10DE062C, "GeForce 9800M GTS" },
479 { 0x10DE062D, "GeForce 9600 GT" },
480 { 0x10DE062E, "GeForce 9600 GT" },
481 { 0x10DE0631, "GeForce GTS 160M" },
482 { 0x10DE0632, "GeForce GTS 150M" },
483 { 0x10DE0635, "GeForce 9600 GSO" },
484 { 0x10DE0637, "GeForce 9600 GT" },
485 { 0x10DE0638, "Quadro FX 1800" },
486 { 0x10DE063A, "Quadro FX 2700M" },
487 { 0x10DE0640, "GeForce 9500 GT" },
488 { 0x10DE0641, "GeForce 9400 GT" },
489 { 0x10DE0643, "GeForce 9500 GT" },
490 { 0x10DE0644, "GeForce 9500 GS" },
491 { 0x10DE0645, "GeForce 9500 GS" },
492 { 0x10DE0646, "GeForce GT 120" },
493 { 0x10DE0647, "GeForce 9600M GT" },
494 { 0x10DE0648, "GeForce 9600M GS" },
495 { 0x10DE0649, "GeForce 9600M GT" },
496 { 0x10DE064A, "GeForce 9700M GT" },
497 { 0x10DE064B, "GeForce 9500M G" },
498 { 0x10DE064C, "GeForce 9650M GT" },
499 { 0x10DE0651, "GeForce G 110M" },
500 { 0x10DE0652, "GeForce GT 130M" },
501 { 0x10DE0653, "GeForce GT 120M" },
502 { 0x10DE0654, "GeForce GT 220M" },
503 { 0x10DE0656, "GeForce 9650 S" },
504 { 0x10DE0658, "Quadro FX 380" },
505 { 0x10DE0659, "Quadro FX 580" },
506 { 0x10DE065A, "Quadro FX 1700M" },
507 { 0x10DE065B, "GeForce 9400 GT" },
508 { 0x10DE065C, "Quadro FX 770M" },
509 { 0x10DE06E0, "GeForce 9300 GE" },
510 { 0x10DE06E1, "GeForce 9300 GS" },
511 { 0x10DE06E2, "GeForce 8400" },
512 { 0x10DE06E3, "GeForce 8400 SE" },
513 { 0x10DE06E4, "GeForce 8400 GS" },
514 { 0x10DE06E5, "GeForce 9300M GS" },
515 { 0x10DE06E6, "GeForce G100" },
516 { 0x10DE06E7, "GeForce 9300 SE" },
517 { 0x10DE06E8, "GeForce 9200M GS" },
518 { 0x10DE06E9, "GeForce 9300M GS" },
519 { 0x10DE06EA, "Quadro NVS 150M" },
520 { 0x10DE06EB, "Quadro NVS 160M" },
521 { 0x10DE06EC, "GeForce G 105M" },
522 { 0x10DE06EF, "GeForce G 103M" },
523 { 0x10DE06F1, "GeForce G105M" },
524 { 0x10DE06F8, "Quadro NVS 420" },
525 { 0x10DE06F9, "Quadro FX 370 LP" },
526 { 0x10DE06FA, "Quadro NVS 450" },
527 { 0x10DE06FB, "Quadro FX 370M" },
528 { 0x10DE06FD, "Quadro NVS 295" },
529 { 0x10DE0844, "GeForce 9100M G" },
530 { 0x10DE0845, "GeForce 8200M G" },
531 { 0x10DE0846, "GeForce 9200" },
532 { 0x10DE0847, "GeForce 9100" },
533 { 0x10DE0848, "GeForce 8300" },
534 { 0x10DE0849, "GeForce 8200" },
535 { 0x10DE084A, "nForce 730a" },
536 { 0x10DE084B, "GeForce 9200" },
537 { 0x10DE084C, "nForce 980a/780a SLI" },
538 { 0x10DE084D, "nForce 750a SLI" },
539 { 0x10DE084F, "GeForce 8100 / nForce 720a" },
540 { 0x10DE0860, "GeForce 9400" },
541 { 0x10DE0861, "GeForce 9400" },
542 { 0x10DE0862, "GeForce 9400M G" },
543 { 0x10DE0863, "GeForce 9400M" },
544 { 0x10DE0864, "GeForce 9300" },
545 { 0x10DE0865, "ION" },
546 { 0x10DE0866, "GeForce 9400M G" },
547 { 0x10DE0867, "GeForce 9400" },
548 { 0x10DE0868, "nForce 760i SLI" },
549 { 0x10DE086A, "GeForce 9400" },
550 { 0x10DE086C, "GeForce 9300 / nForce 730i" },
551 { 0x10DE086D, "GeForce 9200" },
552 { 0x10DE086E, "GeForce 9100M G" },
553 { 0x10DE086F, "GeForce 8200M G" },
554 { 0x10DE0870, "GeForce 9400M" },
555 { 0x10DE0871, "GeForce 9200" },
556 { 0x10DE0872, "GeForce G102M" },
557 { 0x10DE0873, "GeForce G102M" },
558 { 0x10DE0874, "ION" },
559 { 0x10DE0876, "ION" },
560 { 0x10DE087A, "GeForce 9400" },
561 { 0x10DE087D, "ION" },
562 { 0x10DE087E, "ION LE" },
563 { 0x10DE087F, "ION LE" },
564 { 0x10DE0A20, "GeForce GT 220" },
565 { 0x10DE0A22, "GeForce 315" },
566 { 0x10DE0A23, "GeForce 210" },
567 { 0x10DE0A28, "GeForce GT 230M" },
568 { 0x10DE0A29, "GeForce GT 330M" },
569 { 0x10DE0A2A, "GeForce GT 230M" },
570 { 0x10DE0A2B, "GeForce GT 330M" },
571 { 0x10DE0A2C, "NVS 5100M" },
572 { 0x10DE0A2D, "GeForce GT 320M" },
573 { 0x10DE0A34, "GeForce GT 240M" },
574 { 0x10DE0A35, "GeForce GT 325M" },
575 { 0x10DE0A3C, "Quadro FX 880M" },
576 { 0x10DE0A60, "GeForce G210" },
577 { 0x10DE0A62, "GeForce 205" },
578 { 0x10DE0A63, "GeForce 310" },
579 { 0x10DE0A64, "ION" },
580 { 0x10DE0A65, "GeForce 210" },
581 { 0x10DE0A66, "GeForce 310" },
582 { 0x10DE0A67, "GeForce 315" },
583 { 0x10DE0A68, "GeForce G105M" },
584 { 0x10DE0A69, "GeForce G105M" },
585 { 0x10DE0A6A, "NVS 2100M" },
586 { 0x10DE0A6C, "NVS 3100M" },
587 { 0x10DE0A6E, "GeForce 305M" },
588 { 0x10DE0A6F, "ION" },
589 { 0x10DE0A70, "GeForce 310M" },
590 { 0x10DE0A71, "GeForce 305M" },
591 { 0x10DE0A72, "GeForce 310M" },
592 { 0x10DE0A73, "GeForce 305M" },
593 { 0x10DE0A74, "GeForce G210M" },
594 { 0x10DE0A75, "GeForce 310M" },
595 { 0x10DE0A78, "Quadro FX 380 LP" },
596 { 0x10DE0A7C, "Quadro FX 380M" },
597 { 0x10DE0CA0, "GeForce GT 330" },
598 { 0x10DE0CA2, "GeForce GT 320" },
599 { 0x10DE0CA3, "GeForce GT 240" },
600 { 0x10DE0CA4, "GeForce GT 340" },
601 { 0x10DE0CA7, "GeForce GT 330" },
602 { 0x10DE0CA8, "GeForce GTS 260M" },
603 { 0x10DE0CA9, "GeForce GTS 250M" },
604 { 0x10DE0CAC, "GeForce 315" },
605 { 0x10DE0CAF, "GeForce GT 335M" },
606 { 0x10DE0CB0, "GeForce GTS 350M" },
607 { 0x10DE0CB1, "GeForce GTS 360M" },
608 { 0x10DE0CBC, "Quadro FX 1800M" },
609
610 {-1, NULL}
611 };
612
613 #ifdef XFree86LOADER
614
615 static MODULESETUPPROTO(nvSetup);
616
617 static XF86ModuleVersionInfo nvVersRec =
618 {
619 "nv",
620 MODULEVENDORSTRING,
621 MODINFOSTRING1,
622 MODINFOSTRING2,
623 XORG_VERSION_CURRENT,
624 PACKAGE_VERSION_MAJOR, PACKAGE_VERSION_MINOR, PACKAGE_VERSION_PATCHLEVEL,
625 ABI_CLASS_VIDEODRV, /* This is a video driver */
626 ABI_VIDEODRV_VERSION,
627 MOD_CLASS_VIDEODRV,
628 {0,0,0,0}
629 };
630
631 _X_EXPORT XF86ModuleData nvModuleData = { &nvVersRec, nvSetup, NULL };
632 #endif
633
634
635 typedef enum {
636 OPTION_SW_CURSOR,
637 OPTION_HW_CURSOR,
638 OPTION_NOACCEL,
639 OPTION_SHADOW_FB,
640 OPTION_FBDEV,
641 OPTION_ROTATE,
642 OPTION_VIDEO_KEY,
643 OPTION_FLAT_PANEL,
644 OPTION_FP_DITHER,
645 OPTION_CRTC_NUMBER,
646 OPTION_FP_SCALE,
647 OPTION_FP_TWEAK,
648 OPTION_DUALHEAD,
649 } NVOpts;
650
651
652 static const OptionInfoRec NVOptions[] = {
653 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE },
654 { OPTION_HW_CURSOR, "HWcursor", OPTV_BOOLEAN, {0}, FALSE },
655 { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE },
656 { OPTION_SHADOW_FB, "ShadowFB", OPTV_BOOLEAN, {0}, FALSE },
657 { OPTION_FBDEV, "UseFBDev", OPTV_BOOLEAN, {0}, FALSE },
658 { OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE },
659 { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE },
660 { OPTION_FLAT_PANEL, "FlatPanel", OPTV_BOOLEAN, {0}, FALSE },
661 { OPTION_FP_DITHER, "FPDither", OPTV_BOOLEAN, {0}, FALSE },
662 { OPTION_CRTC_NUMBER, "CrtcNumber", OPTV_INTEGER, {0}, FALSE },
663 { OPTION_FP_SCALE, "FPScale", OPTV_BOOLEAN, {0}, FALSE },
664 { OPTION_FP_TWEAK, "FPTweak", OPTV_INTEGER, {0}, FALSE },
665 { OPTION_DUALHEAD, "DualHead", OPTV_BOOLEAN, {0}, FALSE },
666 { -1, NULL, OPTV_NONE, {0}, FALSE }
667 };
668
669 /*
670 * This is intentionally screen-independent. It indicates the binding
671 * choice made in the first PreInit.
672 */
673 static int pix24bpp = 0;
674
675
676 static Bool
NVGetRec(ScrnInfoPtr pScrn)677 NVGetRec(ScrnInfoPtr pScrn)
678 {
679 /*
680 * Allocate an NVRec, and hook it into pScrn->driverPrivate.
681 * pScrn->driverPrivate is initialised to NULL, so we can check if
682 * the allocation has already been done.
683 */
684 if (pScrn->driverPrivate != NULL)
685 return TRUE;
686
687 pScrn->driverPrivate = xnfcalloc(sizeof(NVRec), 1);
688 /* Initialise it */
689
690 return TRUE;
691 }
692
693 static void
NVFreeRec(ScrnInfoPtr pScrn)694 NVFreeRec(ScrnInfoPtr pScrn)
695 {
696 if (pScrn->driverPrivate == NULL)
697 return;
698 free(pScrn->driverPrivate);
699 pScrn->driverPrivate = NULL;
700 }
701
702
703 #ifdef XFree86LOADER
704
705 static pointer
nvSetup(pointer module,pointer opts,int * errmaj,int * errmin)706 nvSetup(pointer module, pointer opts, int *errmaj, int *errmin)
707 {
708 static Bool setupDone = FALSE;
709
710 /* This module should be loaded only once, but check to be sure. */
711
712 if (!setupDone) {
713 setupDone = TRUE;
714 xf86AddDriver(&NV, module,
715 #if XSERVER_LIBPCIACCESS
716 HaveDriverFuncs
717 #else
718 0
719 #endif
720 );
721
722 /*
723 * The return value must be non-NULL on success even though there
724 * is no TearDownProc.
725 */
726 return (pointer)1;
727 } else {
728 if (errmaj) *errmaj = LDR_ONCEONLY;
729 return NULL;
730 }
731 }
732
733
734 #endif /* XFree86LOADER */
735
736 static const OptionInfoRec *
NVAvailableOptions(int chipid,int busid)737 NVAvailableOptions(int chipid, int busid)
738 {
739 if(chipid == 0x12D20018) {
740 return RivaAvailableOptions(chipid, busid);
741 }
742
743 return NVOptions;
744 }
745
746 /* Mandatory */
747 static void
NVIdentify(int flags)748 NVIdentify(int flags)
749 {
750 xf86PrintChipsets(NV_NAME, "driver for NVIDIA chipsets", NVKnownChipsets);
751 }
752
753
754 static Bool
NVGetScrnInfoRec(PciChipsets * chips,int chip)755 NVGetScrnInfoRec(PciChipsets *chips, int chip)
756 {
757 ScrnInfoPtr pScrn;
758
759 pScrn = xf86ConfigPciEntity(NULL, 0, chip,
760 chips, NULL, NULL, NULL,
761 NULL, NULL);
762
763 if(!pScrn) return FALSE;
764
765 pScrn->driverVersion = NV_VERSION;
766 pScrn->driverName = NV_DRIVER_NAME;
767 pScrn->name = NV_NAME;
768
769 #if !XSERVER_LIBPCIACCESS
770 pScrn->Probe = NVProbe;
771 #endif
772 pScrn->PreInit = NVPreInit;
773 pScrn->ScreenInit = NVScreenInit;
774 pScrn->SwitchMode = NVSwitchMode;
775 pScrn->AdjustFrame = NVAdjustFrame;
776 pScrn->EnterVT = NVEnterVT;
777 pScrn->LeaveVT = NVLeaveVT;
778 pScrn->FreeScreen = NVFreeScreen;
779 pScrn->ValidMode = NVValidMode;
780
781 return TRUE;
782 }
783
784 #define MAX_CHIPS MAXSCREENS
785
786
787 static CARD32
788 #if XSERVER_LIBPCIACCESS
NVGetPCIXpressChip(struct pci_device * dev)789 NVGetPCIXpressChip (struct pci_device *dev)
790 #else
791 NVGetPCIXpressChip (pciVideoPtr pVideo)
792 #endif
793 {
794 volatile CARD32 *regs;
795 #if XSERVER_LIBPCIACCESS
796 uint32_t pciid, pcicmd;
797 void *tmp;
798
799 pci_device_cfg_read_u32(dev, &pcicmd, PCI_CMD_STAT_REG);
800 pci_device_cfg_write_u32(dev, pcicmd | PCI_CMD_MEM_ENABLE,
801 PCI_CMD_STAT_REG);
802
803 pci_device_map_range(dev, dev->regions[0].base_addr, 0x2000,
804 PCI_DEV_MAP_FLAG_WRITABLE, &tmp);
805 regs = tmp;
806 pciid = regs[0x1800/4];
807 pci_device_unmap_range(dev, tmp, 0x2000);
808
809 pci_device_cfg_write_u32(dev, pcicmd, PCI_CMD_STAT_REG);
810 #else
811 CARD32 pciid, pcicmd;
812 PCITAG Tag = ((pciConfigPtr)(pVideo->thisCard))->tag;
813
814 pcicmd = pciReadLong(Tag, PCI_CMD_STAT_REG);
815 pciWriteLong(Tag, PCI_CMD_STAT_REG, pcicmd | PCI_CMD_MEM_ENABLE);
816
817 regs = xf86MapPciMem(-1, VIDMEM_MMIO, Tag, pVideo->memBase[0], 0x2000);
818
819 pciid = regs[0x1800/4];
820
821 xf86UnMapVidMem(-1, (pointer)regs, 0x2000);
822
823 pciWriteLong(Tag, PCI_CMD_STAT_REG, pcicmd);
824 #endif
825
826 if((pciid & 0x0000ffff) == 0x000010DE)
827 pciid = 0x10DE0000 | (pciid >> 16);
828 else
829 if((pciid & 0xffff0000) == 0xDE100000) /* wrong endian */
830 pciid = 0x10DE0000 | ((pciid << 8) & 0x0000ff00) |
831 ((pciid >> 8) & 0x000000ff);
832
833 return pciid;
834 }
835
836 static Bool
NVIsG80(int chipType)837 NVIsG80(int chipType)
838 {
839 switch(chipType & 0xfff0) {
840 case 0x0190:
841 case 0x0400:
842 case 0x0420:
843 case 0x05e0:
844 case 0x05f0:
845 case 0x0600:
846 case 0x0610:
847 case 0x0620:
848 case 0x0630:
849 case 0x0640:
850 case 0x0650:
851 case 0x06e0:
852 case 0x06f0:
853 case 0x0840:
854 case 0x0850:
855 case 0x0860:
856 case 0x0870:
857 case 0x0a20:
858 case 0x0a30:
859 case 0x0a60:
860 case 0x0a70:
861 case 0x0ca0:
862 case 0x0cb0:
863 return TRUE;
864 }
865
866 return FALSE;
867 }
868
869 static Bool
NVIsSupported(CARD32 id)870 NVIsSupported(CARD32 id)
871 {
872 /* look for a compatible devices which may be newer than
873 the NVKnownChipsets list above. */
874 switch(id & 0xfff0) {
875 case 0x0040:
876 case 0x0090:
877 case 0x00C0:
878 case 0x0120:
879 case 0x0140:
880 case 0x0160:
881 case 0x0170:
882 case 0x0180:
883 case 0x01D0:
884 case 0x0210:
885 case 0x0220:
886 case 0x0240:
887 case 0x0250:
888 case 0x0280:
889 case 0x0290:
890 case 0x0300:
891 case 0x0310:
892 case 0x0320:
893 case 0x0330:
894 case 0x0340:
895 case 0x0390:
896 case 0x03D0:
897 case 0x0530:
898 return TRUE;
899 }
900
901 return FALSE;
902 }
903
904 /* Mandatory */
905 #if XSERVER_LIBPCIACCESS
906 static Bool
NVPciProbe(DriverPtr drv,int entity,struct pci_device * dev,intptr_t data)907 NVPciProbe(DriverPtr drv, int entity, struct pci_device *dev, intptr_t data)
908 {
909 const CARD32 id = ((dev->device_id & 0xfff0) == 0x00F0 ||
910 (dev->device_id & 0xfff0) == 0x02E0) ?
911 NVGetPCIXpressChip(dev) : dev->vendor_id << 16 | dev->device_id;
912 const char *name = xf86TokenToString(NVKnownChipsets, id);
913
914 if (pci_device_has_kernel_driver(dev)) {
915 xf86DrvMsg(0, X_ERROR,
916 NV_NAME ": The PCI device 0x%x (%s) at %2.2d@%2.2d:%2.2d:%1.1d has a kernel module claiming it.\n",
917 id, name, dev->bus, dev->domain, dev->dev, dev->func);
918 xf86DrvMsg(0, X_ERROR,
919 NV_NAME ": This driver cannot operate until it has been unloaded.\n");
920 return FALSE;
921 }
922
923 if(dev->vendor_id == PCI_VENDOR_NVIDIA && !name &&
924 !NVIsSupported(id) && !NVIsG80(id)) {
925 /* See if pci.ids knows what the heck this thing is */
926 name = pci_device_get_device_name(dev);
927 if(name)
928 xf86DrvMsg(0, X_WARNING,
929 NV_NAME ": Ignoring unsupported device 0x%x (%s) at %2.2d@%2.2d:%2.2d:%1.1d\n",
930 id, name, dev->bus, dev->domain, dev->dev, dev->func);
931 else
932 xf86DrvMsg(0, X_WARNING,
933 NV_NAME ": Ignoring unsupported device 0x%x at %2.2d@%2.2d:%2.2d:%1.1d\n",
934 id, dev->bus, dev->domain, dev->dev, dev->func);
935 return FALSE;
936 }
937
938 if(!name)
939 name = pci_device_get_device_name(dev);
940 if(!name)
941 name = "Unknown GPU";
942
943 xf86DrvMsg(0, X_PROBED,
944 NV_NAME ": Found NVIDIA %s at %2.2d@%2.2d:%2.2d:%1.1d\n",
945 name, dev->bus, dev->domain, dev->dev, dev->func);
946
947 if(NVIsG80(id))
948 return G80GetScrnInfoRec(NULL, entity);
949 else if(dev->vendor_id == PCI_VENDOR_NVIDIA_SGS)
950 return RivaGetScrnInfoRec(NULL, entity);
951 else
952 return NVGetScrnInfoRec(NULL, entity);
953 }
954 #else
955 static Bool
NVProbe(DriverPtr drv,int flags)956 NVProbe(DriverPtr drv, int flags)
957 {
958 int i;
959 GDevPtr *devSections;
960 int *usedChips;
961 SymTabRec NVChipsets[MAX_CHIPS + 1];
962 PciChipsets NVPciChipsets[MAX_CHIPS + 1];
963 pciVideoPtr *ppPci;
964 int numDevSections;
965 int numUsed;
966 Bool foundScreen = FALSE;
967
968
969 if ((numDevSections = xf86MatchDevice(NV_DRIVER_NAME, &devSections)) <= 0)
970 return FALSE; /* no matching device section */
971
972 if (!(ppPci = xf86GetPciVideoInfo()))
973 return FALSE; /* no PCI cards found */
974
975 numUsed = 0;
976
977 /* Create the NVChipsets and NVPciChipsets from found devices */
978 while (*ppPci && (numUsed < MAX_CHIPS)) {
979 if(((*ppPci)->vendor == PCI_VENDOR_NVIDIA_SGS) ||
980 ((*ppPci)->vendor == PCI_VENDOR_NVIDIA))
981 {
982 SymTabRec *nvchips = NVKnownChipsets;
983 int pciid = ((*ppPci)->vendor << 16) | (*ppPci)->chipType;
984 int token = pciid;
985
986 if(((token & 0xfff0) == 0x00F0) ||
987 ((token & 0xfff0) == 0x02E0))
988 {
989 token = NVGetPCIXpressChip(*ppPci);
990 }
991
992 while(nvchips->name) {
993 if(token == nvchips->token)
994 break;
995 nvchips++;
996 }
997
998 if(nvchips->name ||
999 ((*ppPci)->vendor == PCI_VENDOR_NVIDIA &&
1000 (NVIsSupported(token) || NVIsG80((*ppPci)->chipType)))) {
1001 NVChipsets[numUsed].token = pciid;
1002 NVChipsets[numUsed].name = nvchips->name ? nvchips->name : "Unknown NVIDIA chip";
1003 NVPciChipsets[numUsed].numChipset = pciid;
1004 NVPciChipsets[numUsed].PCIid = pciid;
1005 NVPciChipsets[numUsed].resList = RES_SHARED_VGA;
1006 numUsed++;
1007 }
1008 }
1009 ppPci++;
1010 }
1011
1012 /* terminate the list */
1013 NVChipsets[numUsed].token = -1;
1014 NVChipsets[numUsed].name = NULL;
1015 NVPciChipsets[numUsed].numChipset = -1;
1016 NVPciChipsets[numUsed].PCIid = -1;
1017 NVPciChipsets[numUsed].resList = RES_UNDEFINED;
1018
1019 numUsed = xf86MatchPciInstances(NV_NAME, 0, NVChipsets, NVPciChipsets,
1020 devSections, numDevSections, drv,
1021 &usedChips);
1022
1023 if (numUsed <= 0)
1024 return FALSE;
1025
1026 if (flags & PROBE_DETECT)
1027 foundScreen = TRUE;
1028 else for (i = 0; i < numUsed; i++) {
1029 pciVideoPtr pPci;
1030
1031 pPci = xf86GetPciInfoForEntity(usedChips[i]);
1032 if(pPci->vendor == PCI_VENDOR_NVIDIA_SGS) {
1033 if(RivaGetScrnInfoRec(NVPciChipsets, usedChips[i]))
1034 foundScreen = TRUE;
1035 } else if (NVIsG80(pPci->chipType)) {
1036 if(G80GetScrnInfoRec(NVPciChipsets, usedChips[i]))
1037 foundScreen = TRUE;
1038 } else {
1039 if(NVGetScrnInfoRec(NVPciChipsets, usedChips[i]))
1040 foundScreen = TRUE;
1041 }
1042 }
1043
1044 free(devSections);
1045 free(usedChips);
1046
1047 return foundScreen;
1048 }
1049 #endif /* XSERVER_LIBPCIACCESS */
1050
1051 /* Usually mandatory */
1052 Bool
NVSwitchMode(SWITCH_MODE_ARGS_DECL)1053 NVSwitchMode(SWITCH_MODE_ARGS_DECL)
1054 {
1055 SCRN_INFO_PTR(arg);
1056
1057 NVSync(pScrn);
1058 return NVModeInit(pScrn, mode);
1059 }
1060
1061 static Bool
NVSwitchModeVBE(SWITCH_MODE_ARGS_DECL)1062 NVSwitchModeVBE(SWITCH_MODE_ARGS_DECL)
1063 {
1064 SCRN_INFO_PTR(arg);
1065 NVPtr pNv = NVPTR(pScrn);
1066 const Bool disableAccess = pNv->accessEnabled;
1067
1068 if(disableAccess)
1069 pScrn->EnableDisableFBAccess(XF86_SCRN_ARG(pScrn), FALSE);
1070
1071 NVSync(pScrn);
1072 if (!NVSetModeVBE(pScrn, mode))
1073 return FALSE;
1074 NVAdjustFrame(ADJUST_FRAME_ARGS(pScrn, pScrn->frameX0, pScrn->frameY0));
1075
1076 if(disableAccess)
1077 pScrn->EnableDisableFBAccess(XF86_SCRN_ARG(pScrn), TRUE);
1078
1079 return TRUE;
1080 }
1081
1082 /*
1083 * This function is used to initialize the Start Address - the first
1084 * displayed location in the video memory.
1085 */
1086 /* Usually mandatory */
1087 void
NVAdjustFrame(ADJUST_FRAME_ARGS_DECL)1088 NVAdjustFrame(ADJUST_FRAME_ARGS_DECL)
1089 {
1090 SCRN_INFO_PTR(arg);
1091 int startAddr;
1092 NVPtr pNv = NVPTR(pScrn);
1093 NVFBLayout *pLayout = &pNv->CurrentLayout;
1094
1095 startAddr = (((y*pLayout->displayWidth)+x)*(pLayout->bitsPerPixel/8));
1096 NVSetStartAddress(pNv, startAddr);
1097 }
1098
1099
1100 /*
1101 * This is called when VT switching back to the X server. Its job is
1102 * to reinitialise the video mode.
1103 *
1104 * We may wish to unmap video/MMIO memory too.
1105 */
1106
1107 /* Mandatory */
1108 static Bool
NVEnterVT(VT_FUNC_ARGS_DECL)1109 NVEnterVT(VT_FUNC_ARGS_DECL)
1110 {
1111 SCRN_INFO_PTR(arg);
1112 NVPtr pNv = NVPTR(pScrn);
1113
1114 if (!NVModeInit(pScrn, pScrn->currentMode))
1115 return FALSE;
1116 NVAdjustFrame(ADJUST_FRAME_ARGS(pScrn, pScrn->frameX0, pScrn->frameY0));
1117
1118 if(pNv->overlayAdaptor)
1119 NVResetVideo(pScrn);
1120 return TRUE;
1121 }
1122
1123 static Bool
NVEnterVTFBDev(VT_FUNC_ARGS_DECL)1124 NVEnterVTFBDev(VT_FUNC_ARGS_DECL)
1125 {
1126 SCRN_INFO_PTR(arg);
1127 fbdevHWEnterVT(VT_FUNC_ARGS);
1128 return TRUE;
1129 }
1130
1131 static Bool
NVEnterVTVBE(VT_FUNC_ARGS_DECL)1132 NVEnterVTVBE(VT_FUNC_ARGS_DECL)
1133 {
1134 SCRN_INFO_PTR(arg);
1135
1136 if (!NVSetModeVBE(pScrn, pScrn->currentMode))
1137 return FALSE;
1138 NVAdjustFrame(ADJUST_FRAME_ARGS(pScrn, 0, 0));
1139 return TRUE;
1140 }
1141
1142 /*
1143 * This is called when VT switching away from the X server. Its job is
1144 * to restore the previous (text) mode.
1145 *
1146 * We may wish to remap video/MMIO memory too.
1147 */
1148
1149 /* Mandatory */
1150 static void
NVLeaveVT(VT_FUNC_ARGS_DECL)1151 NVLeaveVT(VT_FUNC_ARGS_DECL)
1152 {
1153 SCRN_INFO_PTR(arg);
1154 NVPtr pNv = NVPTR(pScrn);
1155
1156 NVSync(pScrn);
1157 NVRestore(pScrn);
1158 NVLockUnlock(pNv, 1);
1159 }
1160
1161 static void
NVLeaveVTVBE(VT_FUNC_ARGS_DECL)1162 NVLeaveVTVBE(VT_FUNC_ARGS_DECL)
1163 {
1164 SCRN_INFO_PTR(arg);
1165
1166 NVSync(pScrn);
1167 NVSaveRestoreVBE(pScrn, MODE_RESTORE);
1168 }
1169
1170 static void
NVBlockHandler(BLOCKHANDLER_ARGS_DECL)1171 NVBlockHandler (BLOCKHANDLER_ARGS_DECL)
1172 {
1173 SCREEN_PTR(arg);
1174 ScrnInfoPtr pScrnInfo = xf86ScreenToScrn(pScreen);
1175 NVPtr pNv = NVPTR(pScrnInfo);
1176
1177 if (pNv->DMAKickoffCallback)
1178 (*pNv->DMAKickoffCallback)(pScrnInfo);
1179
1180 pScreen->BlockHandler = pNv->BlockHandler;
1181 (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS);
1182 pScreen->BlockHandler = NVBlockHandler;
1183
1184 if (pNv->VideoTimerCallback)
1185 (*pNv->VideoTimerCallback)(pScrnInfo, currentTime.milliseconds);
1186
1187 }
1188
1189
1190 /*
1191 * This is called at the end of each server generation. It restores the
1192 * original (text) mode. It should also unmap the video memory, and free
1193 * any per-generation data allocated by the driver. It should finish
1194 * by unwrapping and calling the saved CloseScreen function.
1195 */
1196
1197 /* Mandatory */
1198 static Bool
NVCloseScreen(CLOSE_SCREEN_ARGS_DECL)1199 NVCloseScreen(CLOSE_SCREEN_ARGS_DECL)
1200 {
1201 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
1202 NVPtr pNv = NVPTR(pScrn);
1203
1204 if (pScrn->vtSema) {
1205 if (!pNv->NoAccel)
1206 NVSync(pScrn);
1207
1208 if (pNv->VBEDualhead) {
1209 NVSaveRestoreVBE(pScrn, MODE_RESTORE);
1210 } else {
1211 NVRestore(pScrn);
1212 NVLockUnlock(pNv, 1);
1213 }
1214 }
1215
1216 NVUnmapMem(pScrn);
1217 vgaHWUnmapMem(pScrn);
1218 #ifdef HAVE_XAA_H
1219 if (pNv->AccelInfoRec)
1220 XAADestroyInfoRec(pNv->AccelInfoRec);
1221 #endif
1222 if (pNv->CursorInfoRec)
1223 xf86DestroyCursorInfoRec(pNv->CursorInfoRec);
1224 if (pNv->ShadowPtr)
1225 free(pNv->ShadowPtr);
1226 if (pNv->DGAModes)
1227 free(pNv->DGAModes);
1228 if (pNv->overlayAdaptor)
1229 free(pNv->overlayAdaptor);
1230 if (pNv->blitAdaptor)
1231 free(pNv->blitAdaptor);
1232
1233 pScrn->vtSema = FALSE;
1234 pScreen->CloseScreen = pNv->CloseScreen;
1235 pScreen->BlockHandler = pNv->BlockHandler;
1236 return (*pScreen->CloseScreen)(CLOSE_SCREEN_ARGS);
1237 }
1238
1239 static void
NVEnableDisableFBAccess(SCRN_ARG_TYPE arg,Bool enable)1240 NVEnableDisableFBAccess(SCRN_ARG_TYPE arg, Bool enable)
1241 {
1242 SCRN_INFO_PTR(arg);
1243 NVPtr pNv = NVPTR(pScrn);
1244
1245 pNv->accessEnabled = enable;
1246 pNv->EnableDisableFBAccess(arg, enable);
1247 }
1248
1249
1250 /* Free up any persistent data structures */
1251
1252 /* Optional */
1253 static void
NVFreeScreen(FREE_SCREEN_ARGS_DECL)1254 NVFreeScreen(FREE_SCREEN_ARGS_DECL)
1255 {
1256 SCRN_INFO_PTR(arg);
1257 /*
1258 * This only gets called when a screen is being deleted. It does not
1259 * get called routinely at the end of a server generation.
1260 */
1261 if (xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
1262 vgaHWFreeHWRec(pScrn);
1263 NVFreeRec(pScrn);
1264 }
1265
1266
1267 /* Checks if a mode is suitable for the selected chipset. */
1268
1269 /* Optional */
1270 static ModeStatus
NVValidMode(SCRN_ARG_TYPE arg,DisplayModePtr mode,Bool verbose,int flags)1271 NVValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode, Bool verbose, int flags)
1272 {
1273 SCRN_INFO_PTR(arg);
1274 NVPtr pNv = NVPTR(pScrn);
1275
1276 if(pNv->fpWidth && pNv->fpHeight)
1277 if((pNv->fpWidth < mode->HDisplay) || (pNv->fpHeight < mode->VDisplay))
1278 return (MODE_PANEL);
1279
1280 return (MODE_OK);
1281 }
1282
1283 static void
nvProbeDDC(ScrnInfoPtr pScrn,int index)1284 nvProbeDDC(ScrnInfoPtr pScrn, int index)
1285 {
1286 vbeInfoPtr pVbe;
1287
1288 if (xf86LoadSubModule(pScrn, "vbe")) {
1289 pVbe = VBEInit(NULL,index);
1290 ConfiguredMonitor = vbeDoEDID(pVbe, NULL);
1291 vbeFree(pVbe);
1292 }
1293 }
1294
1295
NVI2CInit(ScrnInfoPtr pScrn)1296 Bool NVI2CInit(ScrnInfoPtr pScrn)
1297 {
1298 char *mod = "i2c";
1299
1300 if (xf86LoadSubModule(pScrn, mod)) {
1301
1302 mod = "ddc";
1303 if(xf86LoadSubModule(pScrn, mod)) {
1304 return NVDACi2cInit(pScrn);
1305 }
1306 }
1307
1308 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
1309 "Couldn't load %s module. DDC probing can't be done\n", mod);
1310
1311 return FALSE;
1312 }
1313
1314
1315 /* Copied from ddc/Property.c */
1316 static DisplayModePtr
NVModesAdd(DisplayModePtr Modes,DisplayModePtr Additions)1317 NVModesAdd(DisplayModePtr Modes, DisplayModePtr Additions)
1318 {
1319 if (!Modes) {
1320 if (Additions)
1321 return Additions;
1322 else
1323 return NULL;
1324 }
1325
1326 if (Additions) {
1327 DisplayModePtr Mode = Modes;
1328
1329 while (Mode->next)
1330 Mode = Mode->next;
1331
1332 Mode->next = Additions;
1333 Additions->prev = Mode;
1334 }
1335
1336 return Modes;
1337 }
1338
1339 /* Mandatory */
1340 static Bool
NVPreInit(ScrnInfoPtr pScrn,int flags)1341 NVPreInit(ScrnInfoPtr pScrn, int flags)
1342 {
1343 NVPtr pNv;
1344 MessageType from;
1345 int i, max_width, max_height;
1346 ClockRangePtr clockRanges;
1347 const char *s;
1348 Bool config_mon_rates;
1349
1350 if (flags & PROBE_DETECT) {
1351 EntityInfoPtr pEnt = xf86GetEntityInfo(pScrn->entityList[0]);
1352
1353 if (!pEnt)
1354 return FALSE;
1355
1356 i = pEnt->index;
1357 free(pEnt);
1358
1359 nvProbeDDC(pScrn, i);
1360 return TRUE;
1361 }
1362
1363 /*
1364 * Note: This function is only called once at server startup, and
1365 * not at the start of each server generation. This means that
1366 * only things that are persistent across server generations can
1367 * be initialised here. xf86Screens[] is (pScrn is a pointer to one
1368 * of these). Privates allocated using xf86AllocateScrnInfoPrivateIndex()
1369 * are too, and should be used for data that must persist across
1370 * server generations.
1371 *
1372 * Per-generation data should be allocated with
1373 * AllocateScreenPrivateIndex() from the ScreenInit() function.
1374 */
1375
1376 /* Check the number of entities, and fail if it isn't one. */
1377 if (pScrn->numEntities != 1)
1378 return FALSE;
1379
1380 /* Allocate the NVRec driverPrivate */
1381 if (!NVGetRec(pScrn)) {
1382 return FALSE;
1383 }
1384 pNv = NVPTR(pScrn);
1385
1386 /* Get the entity, and make sure it is PCI. */
1387 pNv->pEnt = xf86GetEntityInfo(pScrn->entityList[0]);
1388 if (pNv->pEnt->location.type != BUS_PCI)
1389 return FALSE;
1390
1391 /* Find the PCI info for this screen */
1392 pNv->PciInfo = xf86GetPciInfoForEntity(pNv->pEnt->index);
1393 #if !XSERVER_LIBPCIACCESS
1394 pNv->PciTag = pciTag(pNv->PciInfo->bus, pNv->PciInfo->device,
1395 pNv->PciInfo->func);
1396 #endif
1397
1398 pNv->Primary = xf86IsPrimaryPci(pNv->PciInfo);
1399
1400 /* Initialize the card through int10 interface if needed */
1401 if (xf86LoadSubModule(pScrn, "int10")) {
1402 #if !defined(__alpha__) && !defined(__powerpc__)
1403 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Initializing int10\n");
1404 pNv->pInt = xf86InitInt10(pNv->pEnt->index);
1405 #endif
1406 }
1407
1408 #ifndef XSERVER_LIBPCIACCESS
1409 xf86SetOperatingState(resVgaIo, pNv->pEnt->index, ResUnusedOpr);
1410 xf86SetOperatingState(resVgaMem, pNv->pEnt->index, ResDisableOpr);
1411 #endif
1412
1413 /* Set pScrn->monitor */
1414 pScrn->monitor = pScrn->confScreen->monitor;
1415
1416 /*
1417 * Set the Chipset and ChipRev, allowing config file entries to
1418 * override.
1419 */
1420 if (pNv->pEnt->device->chipset && *pNv->pEnt->device->chipset) {
1421 pScrn->chipset = pNv->pEnt->device->chipset;
1422 pNv->Chipset = xf86StringToToken(NVKnownChipsets, pScrn->chipset);
1423 from = X_CONFIG;
1424 } else if (pNv->pEnt->device->chipID >= 0) {
1425 pNv->Chipset = pNv->pEnt->device->chipID;
1426 pScrn->chipset = (char *)xf86TokenToString(NVKnownChipsets,
1427 pNv->Chipset);
1428 from = X_CONFIG;
1429 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipID override: 0x%04X\n",
1430 pNv->Chipset);
1431 } else {
1432 from = X_PROBED;
1433 pNv->Chipset = VENDOR_ID(pNv->PciInfo) << 16 | DEVICE_ID(pNv->PciInfo);
1434
1435 if(((pNv->Chipset & 0xfff0) == 0x00F0) ||
1436 ((pNv->Chipset & 0xfff0) == 0x02E0))
1437 {
1438 pNv->Chipset = NVGetPCIXpressChip(pNv->PciInfo);
1439 }
1440
1441 pScrn->chipset = (char *)xf86TokenToString(NVKnownChipsets,
1442 pNv->Chipset);
1443 if(!pScrn->chipset)
1444 pScrn->chipset = "Unknown NVIDIA chipset";
1445 }
1446
1447 if (pNv->pEnt->device->chipRev >= 0) {
1448 pNv->ChipRev = pNv->pEnt->device->chipRev;
1449 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipRev override: %d\n",
1450 pNv->ChipRev);
1451 } else {
1452 pNv->ChipRev = CHIP_REVISION(pNv->PciInfo);
1453 }
1454
1455 /*
1456 * This shouldn't happen because such problems should be caught in
1457 * NVProbe(), but check it just in case.
1458 */
1459 if (pScrn->chipset == NULL) {
1460 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1461 "ChipID 0x%04X is not recognised\n", pNv->Chipset);
1462 xf86FreeInt10(pNv->pInt);
1463 return FALSE;
1464 }
1465 if (pNv->Chipset < 0) {
1466 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1467 "Chipset \"%s\" is not recognised\n", pScrn->chipset);
1468 xf86FreeInt10(pNv->pInt);
1469 return FALSE;
1470 }
1471
1472 xf86DrvMsg(pScrn->scrnIndex, from, "Chipset: \"%s\"\n", pScrn->chipset);
1473
1474
1475 /*
1476 * The first thing we should figure out is the depth, bpp, etc.
1477 */
1478
1479 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) {
1480 xf86FreeInt10(pNv->pInt);
1481 return FALSE;
1482 } else {
1483 /* Check that the returned depth is one we support */
1484 switch (pScrn->depth) {
1485 case 8:
1486 case 15:
1487 case 16:
1488 case 24:
1489 /* OK */
1490 break;
1491 default:
1492 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1493 "Given depth (%d) is not supported by this driver\n",
1494 pScrn->depth);
1495 xf86FreeInt10(pNv->pInt);
1496 return FALSE;
1497 }
1498 }
1499 xf86PrintDepthBpp(pScrn);
1500
1501 /* Get the depth24 pixmap format */
1502 if (pScrn->depth == 24 && pix24bpp == 0)
1503 pix24bpp = xf86GetBppFromDepth(pScrn, 24);
1504
1505 /*
1506 * This must happen after pScrn->display has been set because
1507 * xf86SetWeight references it.
1508 */
1509 if (pScrn->depth > 8) {
1510 /* The defaults are OK for us */
1511 rgb zeros = {0, 0, 0};
1512
1513 if (!xf86SetWeight(pScrn, zeros, zeros)) {
1514 xf86FreeInt10(pNv->pInt);
1515 return FALSE;
1516 }
1517 }
1518
1519 if (!xf86SetDefaultVisual(pScrn, -1)) {
1520 xf86FreeInt10(pNv->pInt);
1521 return FALSE;
1522 } else {
1523 /* We don't currently support DirectColor at > 8bpp */
1524 if (pScrn->depth > 8 && (pScrn->defaultVisual != TrueColor)) {
1525 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Given default visual"
1526 " (%s) is not supported at depth %d\n",
1527 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth);
1528 xf86FreeInt10(pNv->pInt);
1529 return FALSE;
1530 }
1531 }
1532
1533 /* The vgahw module should be loaded here when needed */
1534 if (!xf86LoadSubModule(pScrn, "vgahw")) {
1535 xf86FreeInt10(pNv->pInt);
1536 return FALSE;
1537 }
1538
1539 /*
1540 * Allocate a vgaHWRec
1541 */
1542 if (!vgaHWGetHWRec(pScrn)) {
1543 xf86FreeInt10(pNv->pInt);
1544 return FALSE;
1545 }
1546 #ifdef __powerpc__ /* XXX probably MI */
1547 vgaHWSetMmioFuncs(VGAHWPTR(pScrn), pNv->IOAddress, 0);
1548 #else
1549 vgaHWSetStdFuncs(VGAHWPTR(pScrn));
1550 #endif
1551
1552 /* We use a programmable clock */
1553 pScrn->progClock = TRUE;
1554
1555 /* Collect all of the relevant option flags (fill in pScrn->options) */
1556 xf86CollectOptions(pScrn, NULL);
1557
1558 /* Process the options */
1559 if (!(pNv->Options = malloc(sizeof(NVOptions))))
1560 return FALSE;
1561 memcpy(pNv->Options, NVOptions, sizeof(NVOptions));
1562 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, pNv->Options);
1563
1564 /* Set the bits per RGB for 8bpp mode */
1565 if (pScrn->depth == 8)
1566 pScrn->rgbBits = 8;
1567
1568 from = X_DEFAULT;
1569 pNv->HWCursor = TRUE;
1570 /*
1571 * The preferred method is to use the "hw cursor" option as a tri-state
1572 * option, with the default set above.
1573 */
1574 if (xf86GetOptValBool(pNv->Options, OPTION_HW_CURSOR, &pNv->HWCursor)) {
1575 from = X_CONFIG;
1576 }
1577 /* For compatibility, accept this too (as an override) */
1578 if (xf86ReturnOptValBool(pNv->Options, OPTION_SW_CURSOR, FALSE)) {
1579 from = X_CONFIG;
1580 pNv->HWCursor = FALSE;
1581 }
1582 xf86DrvMsg(pScrn->scrnIndex, from, "Using %s cursor\n",
1583 pNv->HWCursor ? "HW" : "SW");
1584
1585 pNv->FpScale = TRUE;
1586 if (xf86GetOptValBool(pNv->Options, OPTION_FP_SCALE, &pNv->FpScale)) {
1587 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Flat panel scaling %s\n",
1588 pNv->FpScale ? "on" : "off");
1589 }
1590 if (xf86ReturnOptValBool(pNv->Options, OPTION_NOACCEL, FALSE)) {
1591 pNv->NoAccel = TRUE;
1592 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Acceleration disabled\n");
1593 }
1594 if (xf86ReturnOptValBool(pNv->Options, OPTION_SHADOW_FB, FALSE)) {
1595 pNv->ShadowFB = TRUE;
1596 pNv->NoAccel = TRUE;
1597 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
1598 "Using \"Shadow Framebuffer\" - acceleration disabled\n");
1599 }
1600 if (xf86ReturnOptValBool(pNv->Options, OPTION_FBDEV, FALSE)) {
1601 pNv->FBDev = TRUE;
1602 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
1603 "Using framebuffer device\n");
1604 }
1605 if (pNv->FBDev) {
1606 /* check for linux framebuffer device */
1607 if (!xf86LoadSubModule(pScrn, "fbdevhw")) {
1608 xf86FreeInt10(pNv->pInt);
1609 return FALSE;
1610 }
1611
1612 if (!fbdevHWInit(pScrn, pNv->PciInfo, NULL)) {
1613 xf86FreeInt10(pNv->pInt);
1614 return FALSE;
1615 }
1616 pScrn->SwitchMode = fbdevHWSwitchModeWeak();
1617 pScrn->AdjustFrame = fbdevHWAdjustFrameWeak();
1618 pScrn->EnterVT = NVEnterVTFBDev;
1619 pScrn->LeaveVT = fbdevHWLeaveVTWeak();
1620 pScrn->ValidMode = fbdevHWValidModeWeak();
1621 }
1622 pNv->Rotate = 0;
1623 pNv->RandRRotation = FALSE;
1624 if ((s = xf86GetOptValString(pNv->Options, OPTION_ROTATE))) {
1625 if(!xf86NameCmp(s, "CW")) {
1626 pNv->ShadowFB = TRUE;
1627 pNv->NoAccel = TRUE;
1628 pNv->HWCursor = FALSE;
1629 pNv->Rotate = 1;
1630 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
1631 "Rotating screen clockwise - acceleration disabled\n");
1632 } else
1633 if(!xf86NameCmp(s, "CCW")) {
1634 pNv->ShadowFB = TRUE;
1635 pNv->NoAccel = TRUE;
1636 pNv->HWCursor = FALSE;
1637 pNv->Rotate = -1;
1638 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
1639 "Rotating screen counter clockwise - acceleration disabled\n");
1640 } else
1641 if(!xf86NameCmp(s, "RandR")) {
1642 #ifdef RANDR
1643 pNv->ShadowFB = TRUE;
1644 pNv->NoAccel = TRUE;
1645 pNv->HWCursor = FALSE;
1646 pNv->RandRRotation = TRUE;
1647 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
1648 "Using RandR rotation - acceleration disabled\n");
1649 #else
1650 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
1651 "This driver was not compiled with support for the Resize and "
1652 "Rotate extension. Cannot honor 'Option \"Rotate\" "
1653 "\"RandR\"'.\n");
1654 #endif
1655 } else {
1656 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
1657 "\"%s\" is not a valid value for Option \"Rotate\"\n", s);
1658 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1659 "Valid options are \"CW\", \"CCW\", and \"RandR\"\n");
1660 }
1661 }
1662
1663 if(xf86GetOptValInteger(pNv->Options, OPTION_VIDEO_KEY, &(pNv->videoKey))) {
1664 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n",
1665 pNv->videoKey);
1666 } else {
1667 pNv->videoKey = (1 << pScrn->offset.red) |
1668 (1 << pScrn->offset.green) |
1669 (((pScrn->mask.blue >> pScrn->offset.blue) - 1) << pScrn->offset.blue);
1670 }
1671
1672 if (xf86GetOptValBool(pNv->Options, OPTION_FLAT_PANEL, &(pNv->FlatPanel))) {
1673 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "forcing %s usage\n",
1674 pNv->FlatPanel ? "DFP" : "CRTC");
1675 } else {
1676 pNv->FlatPanel = -1; /* autodetect later */
1677 }
1678
1679 pNv->FPDither = FALSE;
1680 if (xf86GetOptValBool(pNv->Options, OPTION_FP_DITHER, &(pNv->FPDither)))
1681 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "enabling flat panel dither\n");
1682
1683 if (xf86GetOptValInteger(pNv->Options, OPTION_CRTC_NUMBER,
1684 &pNv->CRTCnumber))
1685 {
1686 if((pNv->CRTCnumber < 0) || (pNv->CRTCnumber > 1)) {
1687 pNv->CRTCnumber = -1;
1688 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
1689 "Invalid CRTC number. Must be 0 or 1\n");
1690 }
1691 } else {
1692 pNv->CRTCnumber = -1; /* autodetect later */
1693 }
1694
1695
1696 if (xf86GetOptValInteger(pNv->Options, OPTION_FP_TWEAK,
1697 &pNv->PanelTweak))
1698 {
1699 pNv->usePanelTweak = TRUE;
1700 } else {
1701 pNv->usePanelTweak = FALSE;
1702 }
1703
1704 if (xf86ReturnOptValBool(pNv->Options, OPTION_DUALHEAD, FALSE)) {
1705 if (pNv->FBDev)
1706 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
1707 "FBDev and Dualhead are incompatible.\n");
1708 else
1709 pNv->VBEDualhead = TRUE;
1710 }
1711
1712 if (pNv->VBEDualhead) {
1713 if (!xf86LoadSubModule(pScrn, "vbe")) {
1714 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1715 "Couldn't load the VBE module and Dualhead is "
1716 "enabled.\n");
1717 return FALSE;
1718 }
1719 pNv->pVbe = VBEExtendedInit(NULL, pNv->pEnt->index,
1720 SET_BIOS_SCRATCH | RESTORE_BIOS_SCRATCH);
1721 if (!pNv->pVbe) return FALSE;
1722
1723 pNv->pVbeInfo = VBEGetVBEInfo(pNv->pVbe);
1724 if (!pNv->pVbeInfo) return FALSE;
1725
1726 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
1727 "Using VBE dual-head mode.\n");
1728
1729 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1730 "Using software cursor.\n");
1731 pNv->HWCursor = FALSE;
1732
1733 pScrn->SwitchMode = NVSwitchModeVBE;
1734 pScrn->EnterVT = NVEnterVTVBE;
1735 pScrn->LeaveVT = NVLeaveVTVBE;
1736 pScrn->ValidMode = NULL;
1737 }
1738
1739 if (pNv->pEnt->device->MemBase != 0) {
1740 /* Require that the config file value matches one of the PCI values. */
1741 if (!xf86CheckPciMemBase(pNv->PciInfo, pNv->pEnt->device->MemBase)) {
1742 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1743 "MemBase 0x%08lX doesn't match any PCI base register.\n",
1744 pNv->pEnt->device->MemBase);
1745 xf86FreeInt10(pNv->pInt);
1746 NVFreeRec(pScrn);
1747 return FALSE;
1748 }
1749 pNv->FbAddress = pNv->pEnt->device->MemBase;
1750 from = X_CONFIG;
1751 } else {
1752 if (MEMBASE(pNv->PciInfo, 1) != 0) {
1753 pNv->FbAddress = MEMBASE(pNv->PciInfo, 1) & 0xff800000;
1754 from = X_PROBED;
1755 } else {
1756 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1757 "No valid FB address in PCI config space\n");
1758 xf86FreeInt10(pNv->pInt);
1759 NVFreeRec(pScrn);
1760 return FALSE;
1761 }
1762 }
1763 xf86DrvMsg(pScrn->scrnIndex, from, "Linear framebuffer at 0x%lX\n",
1764 (unsigned long)pNv->FbAddress);
1765
1766 if (pNv->pEnt->device->IOBase != 0) {
1767 /* Require that the config file value matches one of the PCI values. */
1768 if (!xf86CheckPciMemBase(pNv->PciInfo, pNv->pEnt->device->IOBase)) {
1769 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1770 "IOBase 0x%08lX doesn't match any PCI base register.\n",
1771 pNv->pEnt->device->IOBase);
1772 xf86FreeInt10(pNv->pInt);
1773 NVFreeRec(pScrn);
1774 return FALSE;
1775 }
1776 pNv->IOAddress = pNv->pEnt->device->IOBase;
1777 from = X_CONFIG;
1778 } else {
1779 if (MEMBASE(pNv->PciInfo, 0) != 0) {
1780 pNv->IOAddress = MEMBASE(pNv->PciInfo, 0) & 0xffffc000;
1781 from = X_PROBED;
1782 } else {
1783 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1784 "No valid MMIO address in PCI config space\n");
1785 xf86FreeInt10(pNv->pInt);
1786 NVFreeRec(pScrn);
1787 return FALSE;
1788 }
1789 }
1790 xf86DrvMsg(pScrn->scrnIndex, from, "MMIO registers at 0x%lX\n",
1791 (unsigned long)pNv->IOAddress);
1792
1793 #ifndef XSERVER_LIBPCIACCESS
1794 if (xf86RegisterResources(pNv->pEnt->index, NULL, ResExclusive)) {
1795 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1796 "xf86RegisterResources() found resource conflicts\n");
1797 xf86FreeInt10(pNv->pInt);
1798 NVFreeRec(pScrn);
1799 return FALSE;
1800 }
1801 #endif
1802
1803 switch (pNv->Chipset & 0x0ff0) {
1804 case 0x0100: /* GeForce 256 */
1805 case 0x0110: /* GeForce2 MX */
1806 case 0x0150: /* GeForce2 */
1807 case 0x0170: /* GeForce4 MX */
1808 case 0x0180: /* GeForce4 MX (8x AGP) */
1809 case 0x01A0: /* nForce */
1810 case 0x01F0: /* nForce2 */
1811 pNv->Architecture = NV_ARCH_10;
1812 break;
1813 case 0x0200: /* GeForce3 */
1814 case 0x0250: /* GeForce4 Ti */
1815 case 0x0280: /* GeForce4 Ti (8x AGP) */
1816 pNv->Architecture = NV_ARCH_20;
1817 break;
1818 case 0x0300: /* GeForce FX 5800 */
1819 case 0x0310: /* GeForce FX 5600 */
1820 case 0x0320: /* GeForce FX 5200 */
1821 case 0x0330: /* GeForce FX 5900 */
1822 case 0x0340: /* GeForce FX 5700 */
1823 pNv->Architecture = NV_ARCH_30;
1824 break;
1825 case 0x0040: /* GeForce 6800 */
1826 case 0x00C0: /* GeForce 6800 */
1827 case 0x0120: /* GeForce 6800 */
1828 case 0x0140: /* GeForce 6600 */
1829 case 0x0160: /* GeForce 6200 */
1830 case 0x01D0: /* GeForce 7200, 7300, 7400 */
1831 case 0x0090: /* GeForce 7800 */
1832 case 0x0210: /* GeForce 6800 */
1833 case 0x0220: /* GeForce 6200 */
1834 case 0x0290: /* GeForce 7900 */
1835 case 0x0390: /* GeForce 7600 */
1836 case 0x0240: /* GeForce 6100 */
1837 case 0x0530: /* GeForce 7050, 7025 */
1838 case 0x03D0:
1839 pNv->Architecture = NV_ARCH_40;
1840 break;
1841 default:
1842 pNv->Architecture = NV_ARCH_04;
1843 break;
1844 }
1845
1846 pNv->alphaCursor = (pNv->Architecture >= NV_ARCH_10) &&
1847 ((pNv->Chipset & 0x0ff0) != 0x0100);
1848
1849 if ((pScrn->monitor->nHsync == 0) &&
1850 (pScrn->monitor->nVrefresh == 0))
1851 config_mon_rates = FALSE;
1852 else
1853 config_mon_rates = TRUE;
1854
1855 NVCommonSetup(pScrn);
1856
1857 if (pNv->FBDev) {
1858 pScrn->videoRam = fbdevHWGetVidmem(pScrn)/1024;
1859 } else {
1860 pScrn->videoRam = pNv->RamAmountKBytes;
1861 }
1862 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "VideoRAM: %d kBytes\n",
1863 pScrn->videoRam);
1864
1865 pNv->FbMapSize = pScrn->videoRam * 1024;
1866
1867 /*
1868 * If the driver can do gamma correction, it should call xf86SetGamma()
1869 * here.
1870 */
1871
1872 {
1873 Gamma zeros = {0.0, 0.0, 0.0};
1874
1875 if (!xf86SetGamma(pScrn, zeros)) {
1876 xf86FreeInt10(pNv->pInt);
1877 return FALSE;
1878 }
1879 }
1880
1881 if(pNv->Architecture >= NV_ARCH_40)
1882 pNv->FbUsableSize = pNv->FbMapSize - (560 * 1024);
1883 else
1884 pNv->FbUsableSize = pNv->FbMapSize - (128 * 1024);
1885 pNv->ScratchBufferSize = (pNv->Architecture < NV_ARCH_10) ? 8192 : 16384;
1886 pNv->ScratchBufferStart = pNv->FbUsableSize - pNv->ScratchBufferSize;
1887 pNv->CursorStart = pNv->FbUsableSize + (32 * 1024);
1888
1889 /*
1890 * Setup the ClockRanges, which describe what clock ranges are available,
1891 * and what sort of modes they can be used for.
1892 */
1893
1894 clockRanges = xnfcalloc(sizeof(ClockRange), 1);
1895 clockRanges->next = NULL;
1896 clockRanges->minClock = pNv->MinVClockFreqKHz;
1897 clockRanges->maxClock = pNv->MaxVClockFreqKHz;
1898 clockRanges->clockIndex = -1; /* programmable */
1899 clockRanges->doubleScanAllowed = TRUE;
1900 if((pNv->Architecture == NV_ARCH_20) ||
1901 ((pNv->Architecture == NV_ARCH_10) &&
1902 ((pNv->Chipset & 0x0ff0) != 0x0100) &&
1903 ((pNv->Chipset & 0x0ff0) != 0x0150)))
1904 {
1905 /* HW is broken */
1906 clockRanges->interlaceAllowed = FALSE;
1907 } else {
1908 clockRanges->interlaceAllowed = TRUE;
1909 }
1910
1911 if(pNv->FlatPanel == 1) {
1912 clockRanges->interlaceAllowed = FALSE;
1913 clockRanges->doubleScanAllowed = FALSE;
1914 }
1915
1916 if(pNv->Architecture < NV_ARCH_10) {
1917 max_width = (pScrn->bitsPerPixel > 16) ? 2032 : 2048;
1918 max_height = 2048;
1919 } else {
1920 max_width = (pScrn->bitsPerPixel > 16) ? 4080 : 4096;
1921 max_height = 4096;
1922 }
1923
1924 /* If DFP, add a modeline corresponding to its panel size */
1925 if (pNv->FlatPanel && !pNv->Television && pNv->fpWidth && pNv->fpHeight) {
1926 DisplayModePtr Mode;
1927
1928 Mode = xf86CVTMode(pNv->fpWidth, pNv->fpHeight, 60.00, TRUE, FALSE);
1929 Mode->type = M_T_DRIVER;
1930 pScrn->monitor->Modes = NVModesAdd(pScrn->monitor->Modes, Mode);
1931
1932 if (!config_mon_rates) {
1933 if (!Mode->HSync)
1934 Mode->HSync = ((float) Mode->Clock ) / ((float) Mode->HTotal);
1935 if (!Mode->VRefresh)
1936 Mode->VRefresh = (1000.0 * ((float) Mode->Clock)) /
1937 ((float) (Mode->HTotal * Mode->VTotal));
1938
1939 if (Mode->HSync < pScrn->monitor->hsync[0].lo)
1940 pScrn->monitor->hsync[0].lo = Mode->HSync;
1941 if (Mode->HSync > pScrn->monitor->hsync[0].hi)
1942 pScrn->monitor->hsync[0].hi = Mode->HSync;
1943 if (Mode->VRefresh < pScrn->monitor->vrefresh[0].lo)
1944 pScrn->monitor->vrefresh[0].lo = Mode->VRefresh;
1945 if (Mode->VRefresh > pScrn->monitor->vrefresh[0].hi)
1946 pScrn->monitor->vrefresh[0].hi = Mode->VRefresh;
1947
1948 pScrn->monitor->nHsync = 1;
1949 pScrn->monitor->nVrefresh = 1;
1950 }
1951 }
1952
1953 /*
1954 * xf86ValidateModes will check that the mode HTotal and VTotal values
1955 * don't exceed the chipset's limit if pScrn->maxHValue and
1956 * pScrn->maxVValue are set. Since our NVValidMode() already takes
1957 * care of this, we don't worry about setting them here.
1958 */
1959 if (pNv->VBEDualhead) {
1960 pScrn->modePool = VBEGetModePool(pScrn, pNv->pVbe, pNv->pVbeInfo,
1961 V_MODETYPE_VBE);
1962
1963 VBESetModeNames(pScrn->modePool);
1964 i = VBEValidateModes(pScrn, pScrn->monitor->Modes,
1965 pScrn->display->modes, clockRanges,
1966 NULL, 256, max_width,
1967 512, 128, max_height,
1968 pScrn->display->virtualX,
1969 pScrn->display->virtualY,
1970 pNv->ScratchBufferStart,
1971 LOOKUP_BEST_REFRESH);
1972 if (i > 0)
1973 VBESetModeParameters(pScrn, pNv->pVbe);
1974 } else {
1975 i = xf86ValidateModes(pScrn, pScrn->monitor->Modes,
1976 pScrn->display->modes, clockRanges,
1977 NULL, 256, max_width,
1978 512, 128, max_height,
1979 pScrn->display->virtualX,
1980 pScrn->display->virtualY,
1981 pNv->ScratchBufferStart,
1982 LOOKUP_BEST_REFRESH);
1983 }
1984
1985 if (i < 1 && pNv->FBDev) {
1986 fbdevHWUseBuildinMode(pScrn);
1987 pScrn->displayWidth = pScrn->virtualX; /* FIXME: might be wrong */
1988 i = 1;
1989 }
1990 if (i == -1) {
1991 xf86FreeInt10(pNv->pInt);
1992 NVFreeRec(pScrn);
1993 return FALSE;
1994 }
1995
1996 /* Prune the modes marked as invalid */
1997 xf86PruneDriverModes(pScrn);
1998
1999 if (i == 0 || pScrn->modes == NULL) {
2000 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes found\n");
2001 xf86FreeInt10(pNv->pInt);
2002 NVFreeRec(pScrn);
2003 return FALSE;
2004 }
2005
2006 /*
2007 * Set the CRTC parameters for all of the modes based on the type
2008 * of mode, and the chipset's interlace requirements.
2009 *
2010 * Calling this is required if the mode->Crtc* values are used by the
2011 * driver and if the driver doesn't provide code to set them. They
2012 * are not pre-initialised at all.
2013 */
2014 xf86SetCrtcForModes(pScrn, 0);
2015
2016 if (pNv->VBEDualhead) {
2017 DisplayModePtr p = pScrn->modes;
2018
2019 /*
2020 * Loop through modes and double their widths. Stash the real width in
2021 * CrtcHDisplay. Also adjust the screen dimensions.
2022 */
2023 do {
2024 p->CrtcHDisplay = p->HDisplay;
2025 p->HDisplay *= 2;
2026 } while ((p = p->next) != pScrn->modes);
2027
2028 pScrn->virtualX *= 2;
2029 pScrn->displayWidth *= 2;
2030 }
2031
2032 /* Set the current mode to the first in the list */
2033 pScrn->currentMode = pScrn->modes;
2034
2035 /* Print the list of modes being used */
2036 xf86PrintModes(pScrn);
2037
2038 /* Set display resolution */
2039 xf86SetDpi(pScrn, 0, 0);
2040
2041
2042 /*
2043 * XXX This should be taken into account in some way in the mode valdation
2044 * section.
2045 */
2046
2047 if (xf86LoadSubModule(pScrn, "fb") == NULL) {
2048 xf86FreeInt10(pNv->pInt);
2049 NVFreeRec(pScrn);
2050 return FALSE;
2051 }
2052
2053 /* Load XAA if needed */
2054 if (!pNv->NoAccel) {
2055 if (!xf86LoadSubModule(pScrn, "xaa")) {
2056 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Falling back to shadwwfb\n");
2057 pNv->NoAccel = 1;
2058 pNv->ShadowFB = 1;
2059 }
2060 }
2061
2062 /* Load ramdac if needed */
2063 if (pNv->HWCursor) {
2064 if (!xf86LoadSubModule(pScrn, "ramdac")) {
2065 xf86FreeInt10(pNv->pInt);
2066 NVFreeRec(pScrn);
2067 return FALSE;
2068 }
2069 }
2070
2071 /* Load shadowfb if needed */
2072 if (pNv->ShadowFB) {
2073 if (!xf86LoadSubModule(pScrn, "shadow")) {
2074 xf86FreeInt10(pNv->pInt);
2075 NVFreeRec(pScrn);
2076 return FALSE;
2077 }
2078 }
2079
2080 pNv->CurrentLayout.bitsPerPixel = pScrn->bitsPerPixel;
2081 pNv->CurrentLayout.depth = pScrn->depth;
2082 pNv->CurrentLayout.displayWidth = pScrn->displayWidth;
2083 pNv->CurrentLayout.weight.red = pScrn->weight.red;
2084 pNv->CurrentLayout.weight.green = pScrn->weight.green;
2085 pNv->CurrentLayout.weight.blue = pScrn->weight.blue;
2086 pNv->CurrentLayout.mode = pScrn->currentMode;
2087
2088 xf86FreeInt10(pNv->pInt);
2089
2090 pNv->pInt = NULL;
2091 return TRUE;
2092 }
2093
2094
2095 /*
2096 * Map the framebuffer and MMIO memory.
2097 */
2098
2099 static Bool
NVMapMem(ScrnInfoPtr pScrn)2100 NVMapMem(ScrnInfoPtr pScrn)
2101 {
2102 NVPtr pNv = NVPTR(pScrn);
2103
2104 #if XSERVER_LIBPCIACCESS
2105 void *tmp;
2106
2107 pci_device_map_range(pNv->PciInfo, pNv->FbAddress, pNv->FbMapSize,
2108 PCI_DEV_MAP_FLAG_WRITABLE |
2109 PCI_DEV_MAP_FLAG_WRITE_COMBINE, &tmp);
2110 pNv->FbBase = tmp;
2111 #else
2112 pNv->FbBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER,
2113 pNv->PciTag, pNv->FbAddress,
2114 pNv->FbMapSize);
2115 #endif
2116 if (pNv->FbBase == NULL)
2117 return FALSE;
2118
2119 pNv->FbStart = pNv->FbBase;
2120
2121 return TRUE;
2122 }
2123
2124 static Bool
NVMapMemFBDev(ScrnInfoPtr pScrn)2125 NVMapMemFBDev(ScrnInfoPtr pScrn)
2126 {
2127 NVPtr pNv;
2128
2129 pNv = NVPTR(pScrn);
2130
2131 pNv->FbBase = fbdevHWMapVidmem(pScrn);
2132 if (pNv->FbBase == NULL)
2133 return FALSE;
2134
2135 pNv->FbStart = pNv->FbBase;
2136
2137 return TRUE;
2138 }
2139
2140 /*
2141 * Unmap the framebuffer and MMIO memory.
2142 */
2143
2144 static Bool
NVUnmapMem(ScrnInfoPtr pScrn)2145 NVUnmapMem(ScrnInfoPtr pScrn)
2146 {
2147 NVPtr pNv;
2148
2149 pNv = NVPTR(pScrn);
2150
2151 #if XSERVER_LIBPCIACCESS
2152 pci_device_unmap_range(pNv->PciInfo, pNv->FbBase, pNv->FbMapSize);
2153 #else
2154 xf86UnMapVidMem(pScrn->scrnIndex, (pointer)pNv->FbBase, pNv->FbMapSize);
2155 #endif
2156 pNv->FbBase = NULL;
2157 pNv->FbStart = NULL;
2158
2159 return TRUE;
2160 }
2161
2162
2163 /*
2164 * Initialise a new mode.
2165 */
2166
2167 static Bool
NVModeInit(ScrnInfoPtr pScrn,DisplayModePtr mode)2168 NVModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
2169 {
2170 vgaHWPtr hwp = VGAHWPTR(pScrn);
2171 vgaRegPtr vgaReg;
2172 NVPtr pNv = NVPTR(pScrn);
2173 NVRegPtr nvReg;
2174
2175 /* Initialise the ModeReg values */
2176 if (!vgaHWInit(pScrn, mode))
2177 return FALSE;
2178 pScrn->vtSema = TRUE;
2179
2180 vgaReg = &hwp->ModeReg;
2181 nvReg = &pNv->ModeReg;
2182
2183 if(!NVDACInit(pScrn, mode))
2184 return FALSE;
2185
2186 NVLockUnlock(pNv, 0);
2187 if(pNv->twoHeads) {
2188 VGA_WR08(pNv->PCIO, 0x03D4, 0x44);
2189 VGA_WR08(pNv->PCIO, 0x03D5, nvReg->crtcOwner);
2190 NVLockUnlock(pNv, 0);
2191 }
2192
2193 /* Program the registers */
2194 vgaHWProtect(pScrn, TRUE);
2195
2196 NVDACRestore(pScrn, vgaReg, nvReg, FALSE);
2197
2198 #if X_BYTE_ORDER == X_BIG_ENDIAN
2199 /* turn on LFB swapping */
2200 {
2201 unsigned char tmp;
2202
2203 VGA_WR08(pNv->PCIO, 0x3d4, 0x46);
2204 tmp = VGA_RD08(pNv->PCIO, 0x3d5);
2205 tmp |= (1 << 7);
2206 VGA_WR08(pNv->PCIO, 0x3d5, tmp);
2207 }
2208 #endif
2209
2210 NVResetGraphics(pScrn);
2211
2212 vgaHWProtect(pScrn, FALSE);
2213
2214 pNv->CurrentLayout.mode = mode;
2215
2216 return TRUE;
2217 }
2218
2219 static Bool
NVSetModeVBE(ScrnInfoPtr pScrn,DisplayModePtr pMode)2220 NVSetModeVBE(ScrnInfoPtr pScrn, DisplayModePtr pMode)
2221 {
2222 NVPtr pNv = NVPTR(pScrn);
2223 VbeModeInfoData *data;
2224 int mode;
2225
2226 data = (VbeModeInfoData*)pMode->Private;
2227 mode = data->mode | 1 << 14;
2228
2229 if(!VBESetVBEMode(pNv->pVbe, mode, data->block))
2230 return FALSE;
2231 pNv->PCRTC0[0x820/4] = pNv->PCRTC0[0x2820/4] =
2232 pScrn->displayWidth * (pScrn->bitsPerPixel / 8);
2233 pNv->vbeCRTC1Offset = pMode->CrtcHDisplay * (pScrn->bitsPerPixel / 8);
2234
2235 pScrn->vtSema = TRUE;
2236
2237 NVLoadStateExt(pNv, NULL);
2238 NVResetGraphics(pScrn);
2239
2240 pNv->CurrentLayout.mode = pMode;
2241
2242 return TRUE;
2243 }
2244
2245 /*
2246 * Restore the initial (text) mode.
2247 */
2248 static void
NVRestore(ScrnInfoPtr pScrn)2249 NVRestore(ScrnInfoPtr pScrn)
2250 {
2251 vgaHWPtr hwp = VGAHWPTR(pScrn);
2252 vgaRegPtr vgaReg = &hwp->SavedReg;
2253 NVPtr pNv = NVPTR(pScrn);
2254 NVRegPtr nvReg = &pNv->SavedReg;
2255
2256 if(pNv->HWCursor) {
2257 NVShowHideCursor(pNv, 0);
2258 sleep(1);
2259 }
2260 NVLockUnlock(pNv, 0);
2261
2262 if(pNv->twoHeads) {
2263 VGA_WR08(pNv->PCIO, 0x03D4, 0x44);
2264 VGA_WR08(pNv->PCIO, 0x03D5, pNv->CRTCnumber * 0x3);
2265 NVLockUnlock(pNv, 0);
2266 }
2267
2268 /* Only restore text mode fonts/text for the primary card */
2269 vgaHWProtect(pScrn, TRUE);
2270 NVDACRestore(pScrn, vgaReg, nvReg, pNv->Primary);
2271 if(pNv->twoHeads) {
2272 VGA_WR08(pNv->PCIO, 0x03D4, 0x44);
2273 VGA_WR08(pNv->PCIO, 0x03D5, nvReg->crtcOwner);
2274 }
2275 vgaHWProtect(pScrn, FALSE);
2276 }
2277
NVBacklightEnable(NVPtr pNv,Bool on)2278 static void NVBacklightEnable(NVPtr pNv, Bool on)
2279 {
2280 /* This is done differently on each laptop. Here we
2281 define the ones we know for sure. */
2282
2283 #if defined(__powerpc__)
2284 if((pNv->Chipset == 0x10DE0179) ||
2285 (pNv->Chipset == 0x10DE0189) ||
2286 (pNv->Chipset == 0x10DE0329))
2287 {
2288 /* NV17,18,34 Apple iMac, iBook, PowerBook */
2289 CARD32 tmp_pmc, tmp_pcrt;
2290 tmp_pmc = pNv->PMC[0x10F0/4] & 0x7FFFFFFF;
2291 tmp_pcrt = pNv->PCRTC0[0x081C/4] & 0xFFFFFFFC;
2292 if(on) {
2293 tmp_pmc |= (1 << 31);
2294 tmp_pcrt |= 0x1;
2295 }
2296 pNv->PMC[0x10F0/4] = tmp_pmc;
2297 pNv->PCRTC0[0x081C/4] = tmp_pcrt;
2298 }
2299 #endif
2300
2301 if(pNv->LVDS) {
2302 if(pNv->twoHeads) {
2303 if((pNv->Chipset & 0x0ff0) != 0x0110) {
2304 pNv->PMC[0x130C/4] = on ? 3 : 7;
2305 } else if(SUBVENDOR_ID(pNv->PciInfo) == 0x1028 &&
2306 SUBDEVICE_ID(pNv->PciInfo) == 0xd4) {
2307 // Dell Inspiron 8200, GeForce2 Go
2308 CARD32 tmp_pcrt = pNv->PCRTC0[0x081C/4] & 0xFFFFFFFC;
2309 if(on)
2310 tmp_pcrt |= 0x1;
2311 pNv->PCRTC0[0x081C/4] = tmp_pcrt;
2312 }
2313 }
2314 } else {
2315 CARD32 fpcontrol;
2316
2317 fpcontrol = pNv->PRAMDAC[0x0848/4] & 0xCfffffCC;
2318
2319 /* cut the TMDS output */
2320 if(on) fpcontrol |= pNv->fpSyncs;
2321 else fpcontrol |= 0x20000022;
2322
2323 pNv->PRAMDAC[0x0848/4] = fpcontrol;
2324 }
2325 }
2326
2327 static void
NVDPMSSetLCD(ScrnInfoPtr pScrn,int PowerManagementMode,int flags)2328 NVDPMSSetLCD(ScrnInfoPtr pScrn, int PowerManagementMode, int flags)
2329 {
2330 NVPtr pNv = NVPTR(pScrn);
2331
2332 if (!pScrn->vtSema) return;
2333
2334 vgaHWDPMSSet(pScrn, PowerManagementMode, flags);
2335
2336 switch (PowerManagementMode) {
2337 case DPMSModeStandby: /* HSync: Off, VSync: On */
2338 case DPMSModeSuspend: /* HSync: On, VSync: Off */
2339 case DPMSModeOff: /* HSync: Off, VSync: Off */
2340 NVBacklightEnable(pNv, 0);
2341 break;
2342 case DPMSModeOn: /* HSync: On, VSync: On */
2343 NVBacklightEnable(pNv, 1);
2344 default:
2345 break;
2346 }
2347 }
2348
2349
2350 static void
NVDPMSSet(ScrnInfoPtr pScrn,int PowerManagementMode,int flags)2351 NVDPMSSet(ScrnInfoPtr pScrn, int PowerManagementMode, int flags)
2352 {
2353 unsigned char crtc1A;
2354 vgaHWPtr hwp = VGAHWPTR(pScrn);
2355
2356 if (!pScrn->vtSema) return;
2357
2358 crtc1A = hwp->readCrtc(hwp, 0x1A) & ~0xC0;
2359
2360 switch (PowerManagementMode) {
2361 case DPMSModeStandby: /* HSync: Off, VSync: On */
2362 crtc1A |= 0x80;
2363 break;
2364 case DPMSModeSuspend: /* HSync: On, VSync: Off */
2365 crtc1A |= 0x40;
2366 break;
2367 case DPMSModeOff: /* HSync: Off, VSync: Off */
2368 crtc1A |= 0xC0;
2369 break;
2370 case DPMSModeOn: /* HSync: On, VSync: On */
2371 default:
2372 break;
2373 }
2374
2375 /* vgaHWDPMSSet will merely cut the dac output */
2376 vgaHWDPMSSet(pScrn, PowerManagementMode, flags);
2377
2378 hwp->writeCrtc(hwp, 0x1A, crtc1A);
2379 }
2380
2381 static Bool
NVCreateScreenResources(ScreenPtr pScreen)2382 NVCreateScreenResources(ScreenPtr pScreen)
2383 {
2384 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
2385 NVPtr pNv = NVPTR(pScrn);
2386 PixmapPtr pPixmap;
2387 Bool ret;
2388
2389 pScreen->CreateScreenResources = pNv->CreateScreenResources;
2390 ret = pScreen->CreateScreenResources(pScreen);
2391 pScreen->CreateScreenResources = NVCreateScreenResources;
2392
2393 if (!ret)
2394 return FALSE;
2395
2396 pPixmap = pScreen->GetScreenPixmap(pScreen);
2397
2398 if (!shadowAdd(pScreen, pPixmap, NVShadowUpdate,
2399 NULL, 0, NULL)) {
2400 return FALSE;
2401 }
2402 return TRUE;
2403 }
2404
2405 static Bool
NVShadowInit(ScreenPtr pScreen)2406 NVShadowInit(ScreenPtr pScreen)
2407 {
2408 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
2409 NVPtr pNv = NVPTR(pScrn);
2410
2411 if (!shadowSetup(pScreen))
2412 return FALSE;
2413 pNv->CreateScreenResources = pScreen->CreateScreenResources;
2414 pScreen->CreateScreenResources = NVCreateScreenResources;
2415
2416 return TRUE;
2417 }
2418
2419
2420 /* Mandatory */
2421
2422 /* This gets called at the start of each server generation */
2423
2424 static Bool
NVScreenInit(SCREEN_INIT_ARGS_DECL)2425 NVScreenInit(SCREEN_INIT_ARGS_DECL)
2426 {
2427 ScrnInfoPtr pScrn;
2428 vgaHWPtr hwp;
2429 NVPtr pNv;
2430 int ret;
2431 VisualPtr visual;
2432 unsigned char *FBStart;
2433 int width, height, displayWidth, offscreenHeight, shadowHeight;
2434 BoxRec AvailFBArea;
2435
2436 /*
2437 * First get the ScrnInfoRec
2438 */
2439 pScrn = xf86ScreenToScrn(pScreen);
2440
2441 hwp = VGAHWPTR(pScrn);
2442 pNv = NVPTR(pScrn);
2443
2444 /* Map the NV memory and MMIO areas */
2445 if (pNv->FBDev) {
2446 if (!NVMapMemFBDev(pScrn)) {
2447 return FALSE;
2448 }
2449 } else {
2450 if (!NVMapMem(pScrn)) {
2451 return FALSE;
2452 }
2453 }
2454
2455 /* Map the VGA memory when the primary video */
2456 if (pNv->Primary && !pNv->FBDev) {
2457 hwp->MapSize = 0x10000;
2458 if (!vgaHWMapMem(pScrn))
2459 return FALSE;
2460 }
2461
2462 if (pNv->FBDev) {
2463 fbdevHWSave(pScrn);
2464 if (!fbdevHWModeInit(pScrn, pScrn->currentMode))
2465 return FALSE;
2466 } else if (pNv->VBEDualhead) {
2467 NVSaveRestoreVBE(pScrn, MODE_SAVE);
2468 if (!NVSetModeVBE(pScrn, pScrn->currentMode))
2469 return FALSE;
2470 } else {
2471 /* Save the current state */
2472 NVSave(pScrn);
2473 /* Initialise the first mode */
2474 if (!NVModeInit(pScrn, pScrn->currentMode))
2475 return FALSE;
2476 }
2477
2478 /* Darken the screen for aesthetic reasons and set the viewport */
2479 NVSaveScreen(pScreen, SCREEN_SAVER_ON);
2480 pScrn->AdjustFrame(ADJUST_FRAME_ARGS(pScrn, pScrn->frameX0, pScrn->frameY0));
2481
2482 /*
2483 * The next step is to setup the screen's visuals, and initialise the
2484 * framebuffer code. In cases where the framebuffer's default
2485 * choices for things like visual layouts and bits per RGB are OK,
2486 * this may be as simple as calling the framebuffer's ScreenInit()
2487 * function. If not, the visuals will need to be setup before calling
2488 * a fb ScreenInit() function and fixed up after.
2489 *
2490 * For most PC hardware at depths >= 8, the defaults that fb uses
2491 * are not appropriate. In this driver, we fixup the visuals after.
2492 */
2493
2494 /*
2495 * Reset the visual list.
2496 */
2497 miClearVisualTypes();
2498
2499 /* Setup the visuals we support. */
2500
2501 if (!miSetVisualTypes(pScrn->depth,
2502 miGetDefaultVisualMask(pScrn->depth), 8,
2503 pScrn->defaultVisual))
2504 return FALSE;
2505 if (!miSetPixmapDepths ()) return FALSE;
2506
2507 /*
2508 * Call the framebuffer layer's ScreenInit function, and fill in other
2509 * pScreen fields.
2510 */
2511
2512 width = pScrn->virtualX;
2513 height = pScrn->virtualY;
2514 displayWidth = pScrn->displayWidth;
2515
2516
2517 if(pNv->Rotate) {
2518 height = pScrn->virtualX;
2519 width = pScrn->virtualY;
2520 }
2521
2522 /* If RandR rotation is enabled, leave enough space in the
2523 * framebuffer for us to rotate the screen dimensions without
2524 * changing the pitch.
2525 */
2526 if(pNv->RandRRotation)
2527 shadowHeight = max(width, height);
2528 else
2529 shadowHeight = height;
2530
2531 if(pNv->ShadowFB) {
2532 pNv->ShadowPitch = BitmapBytePad(pScrn->bitsPerPixel * width);
2533 pNv->ShadowPtr = malloc(pNv->ShadowPitch * shadowHeight);
2534 displayWidth = pNv->ShadowPitch / (pScrn->bitsPerPixel >> 3);
2535 FBStart = pNv->ShadowPtr;
2536 } else {
2537 pNv->ShadowPtr = NULL;
2538 FBStart = pNv->FbStart;
2539 }
2540
2541 switch (pScrn->bitsPerPixel) {
2542 case 8:
2543 case 16:
2544 case 32:
2545 ret = fbScreenInit(pScreen, FBStart, width, height,
2546 pScrn->xDpi, pScrn->yDpi,
2547 displayWidth, pScrn->bitsPerPixel);
2548 break;
2549 default:
2550 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2551 "Internal error: invalid bpp (%d) in NVScreenInit\n",
2552 pScrn->bitsPerPixel);
2553 ret = FALSE;
2554 break;
2555 }
2556 if (!ret)
2557 return FALSE;
2558
2559 if (pScrn->bitsPerPixel > 8) {
2560 /* Fixup RGB ordering */
2561 visual = pScreen->visuals + pScreen->numVisuals;
2562 while (--visual >= pScreen->visuals) {
2563 if ((visual->class | DynamicClass) == DirectColor) {
2564 visual->offsetRed = pScrn->offset.red;
2565 visual->offsetGreen = pScrn->offset.green;
2566 visual->offsetBlue = pScrn->offset.blue;
2567 visual->redMask = pScrn->mask.red;
2568 visual->greenMask = pScrn->mask.green;
2569 visual->blueMask = pScrn->mask.blue;
2570 }
2571 }
2572 }
2573
2574 fbPictureInit (pScreen, 0, 0);
2575
2576 xf86SetBlackWhitePixels(pScreen);
2577
2578 if(!pNv->ShadowFB) /* hardware cursor needs to wrap this layer */
2579 NVDGAInit(pScreen);
2580
2581 offscreenHeight = pNv->ScratchBufferStart /
2582 (pScrn->displayWidth * pScrn->bitsPerPixel >> 3);
2583 if(offscreenHeight > 32767)
2584 offscreenHeight = 32767;
2585
2586 AvailFBArea.x1 = 0;
2587 AvailFBArea.y1 = 0;
2588 AvailFBArea.x2 = pScrn->displayWidth;
2589 AvailFBArea.y2 = offscreenHeight;
2590 xf86InitFBManager(pScreen, &AvailFBArea);
2591
2592 if (!pNv->NoAccel)
2593 NVAccelInit(pScreen);
2594
2595 xf86SetBackingStore(pScreen);
2596 xf86SetSilkenMouse(pScreen);
2597
2598 /* Initialize software cursor.
2599 Must precede creation of the default colormap */
2600 miDCInitialize(pScreen, xf86GetPointerScreenFuncs());
2601
2602 /* Initialize HW cursor layer.
2603 Must follow software cursor initialization*/
2604 if (pNv->HWCursor) {
2605 if(!NVCursorInit(pScreen))
2606 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2607 "Hardware cursor initialization failed\n");
2608 }
2609
2610 /* Initialise default colourmap */
2611 if (!miCreateDefColormap(pScreen))
2612 return FALSE;
2613
2614 /* Initialize colormap layer.
2615 Must follow initialization of the default colormap */
2616 if(!xf86HandleColormaps(pScreen, 256, 8,
2617 (pNv->FBDev ? fbdevHWLoadPaletteWeak() : NVDACLoadPalette),
2618 NULL, CMAP_RELOAD_ON_MODE_SWITCH | CMAP_PALETTED_TRUECOLOR))
2619 return FALSE;
2620
2621 if(pNv->ShadowFB) {
2622 RefreshAreaFuncPtr refreshArea = NVRefreshArea;
2623
2624 if(pNv->Rotate || pNv->RandRRotation) {
2625 pNv->PointerMoved = pScrn->PointerMoved;
2626 if(pNv->Rotate)
2627 pScrn->PointerMoved = NVPointerMoved;
2628
2629 switch(pScrn->bitsPerPixel) {
2630 case 8: refreshArea = NVRefreshArea8; break;
2631 case 16: refreshArea = NVRefreshArea16; break;
2632 case 32: refreshArea = NVRefreshArea32; break;
2633 }
2634 if(!pNv->RandRRotation) {
2635 xf86DisableRandR();
2636 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2637 "Driver rotation enabled, RandR disabled\n");
2638 }
2639 }
2640 pNv->refreshArea = refreshArea;
2641 NVShadowInit(pScreen);
2642 }
2643
2644 if(pNv->FlatPanel)
2645 xf86DPMSInit(pScreen, NVDPMSSetLCD, 0);
2646 else
2647 xf86DPMSInit(pScreen, NVDPMSSet, 0);
2648
2649 pScrn->memPhysBase = pNv->FbAddress;
2650 pScrn->fbOffset = 0;
2651
2652 if(pNv->Rotate == 0 && !pNv->RandRRotation)
2653 NVInitVideo(pScreen);
2654
2655 pScreen->SaveScreen = NVSaveScreen;
2656
2657 /* Wrap the current CloseScreen function */
2658 pNv->CloseScreen = pScreen->CloseScreen;
2659 pScreen->CloseScreen = NVCloseScreen;
2660
2661 pNv->BlockHandler = pScreen->BlockHandler;
2662 pScreen->BlockHandler = NVBlockHandler;
2663
2664 pNv->accessEnabled = TRUE;
2665 pNv->EnableDisableFBAccess = pScrn->EnableDisableFBAccess;
2666 pScrn->EnableDisableFBAccess = NVEnableDisableFBAccess;
2667
2668 #ifdef RANDR
2669 /* Install our DriverFunc. We have to do it this way instead of using the
2670 * HaveDriverFuncs argument to xf86AddDriver, because InitOutput clobbers
2671 * pScrn->DriverFunc */
2672 pScrn->DriverFunc = NVDriverFunc;
2673 #endif
2674
2675 /* Report any unused options (only for the first generation) */
2676 if (serverGeneration == 1) {
2677 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
2678 }
2679 return TRUE;
2680 }
2681
2682 static Bool
NVSaveScreen(ScreenPtr pScreen,int mode)2683 NVSaveScreen(ScreenPtr pScreen, int mode)
2684 {
2685 return vgaHWSaveScreen(pScreen, mode);
2686 }
2687
2688 static void
NVSave(ScrnInfoPtr pScrn)2689 NVSave(ScrnInfoPtr pScrn)
2690 {
2691 NVPtr pNv = NVPTR(pScrn);
2692 NVRegPtr nvReg = &pNv->SavedReg;
2693 vgaHWPtr pVga = VGAHWPTR(pScrn);
2694 vgaRegPtr vgaReg = &pVga->SavedReg;
2695
2696 NVLockUnlock(pNv, 0);
2697 if(pNv->twoHeads) {
2698 VGA_WR08(pNv->PCIO, 0x03D4, 0x44);
2699 VGA_WR08(pNv->PCIO, 0x03D5, pNv->CRTCnumber * 0x3);
2700 NVLockUnlock(pNv, 0);
2701 }
2702
2703 NVDACSave(pScrn, vgaReg, nvReg, pNv->Primary);
2704 }
2705
2706 static void
NVSaveRestoreVBE(ScrnInfoPtr pScrn,vbeSaveRestoreFunction function)2707 NVSaveRestoreVBE(ScrnInfoPtr pScrn, vbeSaveRestoreFunction function)
2708 {
2709 NVPtr pNv = NVPTR(pScrn);
2710
2711 if (function == MODE_SAVE) {
2712 VBEGetVBEMode(pNv->pVbe, &pNv->vbeMode);
2713 NVSave(pScrn);
2714 } else if (function == MODE_RESTORE) {
2715 NVRestore(pScrn);
2716 VBESetVBEMode(pNv->pVbe, pNv->vbeMode, NULL);
2717 }
2718 }
2719
2720 #ifdef RANDR
2721 static Bool
NVRandRGetInfo(ScrnInfoPtr pScrn,Rotation * rotations)2722 NVRandRGetInfo(ScrnInfoPtr pScrn, Rotation *rotations)
2723 {
2724 NVPtr pNv = NVPTR(pScrn);
2725
2726 if(pNv->RandRRotation)
2727 *rotations = RR_Rotate_0 | RR_Rotate_90 | RR_Rotate_270;
2728 else
2729 *rotations = RR_Rotate_0;
2730
2731 return TRUE;
2732 }
2733
2734 static Bool
NVRandRSetConfig(ScrnInfoPtr pScrn,xorgRRConfig * config)2735 NVRandRSetConfig(ScrnInfoPtr pScrn, xorgRRConfig *config)
2736 {
2737 NVPtr pNv = NVPTR(pScrn);
2738
2739 switch(config->rotation) {
2740 case RR_Rotate_0:
2741 pNv->Rotate = 0;
2742 pScrn->PointerMoved = pNv->PointerMoved;
2743 break;
2744
2745 case RR_Rotate_90:
2746 pNv->Rotate = -1;
2747 pScrn->PointerMoved = NVPointerMoved;
2748 break;
2749
2750 case RR_Rotate_270:
2751 pNv->Rotate = 1;
2752 pScrn->PointerMoved = NVPointerMoved;
2753 break;
2754
2755 default:
2756 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2757 "Unexpected rotation in NVRandRSetConfig!\n");
2758 pNv->Rotate = 0;
2759 pScrn->PointerMoved = pNv->PointerMoved;
2760 return FALSE;
2761 }
2762
2763 return TRUE;
2764 }
2765
2766 static Bool
NVDriverFunc(ScrnInfoPtr pScrn,xorgDriverFuncOp op,pointer data)2767 NVDriverFunc(ScrnInfoPtr pScrn, xorgDriverFuncOp op, pointer data)
2768 {
2769 switch(op) {
2770 case RR_GET_INFO:
2771 return NVRandRGetInfo(pScrn, (Rotation*)data);
2772 case RR_SET_CONFIG:
2773 return NVRandRSetConfig(pScrn, (xorgRRConfig*)data);
2774 default:
2775 return FALSE;
2776 }
2777
2778 return FALSE;
2779 }
2780 #endif /* RANDR */
2781