1 /*
2 * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
3 * Copyright (c) 2004-05 Vinod Kashyap.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/twa/tw_osl.h 232669 2012-03-07 18:53:56Z jhb $
28 */
29
30 /*
31 * AMCC'S 3ware driver for 9000 series storage controllers.
32 *
33 * Author: Vinod Kashyap
34 * Modifications by: Adam Radford
35 * Modifications by: Manjunath Ranganathaiah
36 */
37
38
39
40 #ifndef TW_OSL_H
41
42 #define TW_OSL_H
43
44
45 /*
46 * OS Layer internal macros, structures and functions.
47 */
48
49
50 #define TW_OSLI_DEVICE_NAME "3ware 9000 series Storage Controller"
51
52 #define TW_OSLI_MALLOC_CLASS M_TWA
53 #define TW_OSLI_MAX_NUM_REQUESTS TW_CL_MAX_SIMULTANEOUS_REQUESTS
54 /* Reserve two command packets. One for ioctls and one for AENs */
55 #define TW_OSLI_MAX_NUM_IOS (TW_OSLI_MAX_NUM_REQUESTS - 2)
56 #define TW_OSLI_MAX_NUM_AENS 0x100
57
58 #define TW_OSLI_DMA_BOUNDARY ((bus_size_t)((uint64_t)1 << 32))
59
60 /* Possible values of req->state. */
61 #define TW_OSLI_REQ_STATE_INIT 0x0 /* being initialized */
62 #define TW_OSLI_REQ_STATE_BUSY 0x1 /* submitted to CL */
63 #define TW_OSLI_REQ_STATE_PENDING 0x2 /* in pending queue */
64 #define TW_OSLI_REQ_STATE_COMPLETE 0x3 /* completed by CL */
65
66 /* Possible values of req->flags. */
67 #define TW_OSLI_REQ_FLAGS_DATA_IN (1<<0) /* read request */
68 #define TW_OSLI_REQ_FLAGS_DATA_OUT (1<<1) /* write request */
69 #define TW_OSLI_REQ_FLAGS_DATA_COPY_NEEDED (1<<2)/* data in ccb is misaligned,
70 have to copy to/from private buffer */
71 #define TW_OSLI_REQ_FLAGS_MAPPED (1<<3) /* request has been mapped */
72 #define TW_OSLI_REQ_FLAGS_IN_PROGRESS (1<<4) /* bus_dmamap_load returned
73 EINPROGRESS */
74 #define TW_OSLI_REQ_FLAGS_PASSTHRU (1<<5) /* pass through request */
75 #define TW_OSLI_REQ_FLAGS_SLEEPING (1<<6) /* owner sleeping on this cmd */
76 #define TW_OSLI_REQ_FLAGS_FAILED (1<<7) /* bus_dmamap_load() failed */
77
78
79 #ifdef TW_OSL_DEBUG
80 struct tw_osli_q_stats {
81 TW_UINT32 cur_len; /* current # of items in q */
82 TW_UINT32 max_len; /* max value reached by q_length */
83 };
84 #endif /* TW_OSL_DEBUG */
85
86
87 /* Queues of OSL internal request context packets. */
88 #define TW_OSLI_FREE_Q 0 /* free q */
89 #define TW_OSLI_BUSY_Q 1 /* q of reqs submitted to CL */
90 #define TW_OSLI_Q_COUNT 2 /* total number of queues */
91
92 /* Driver's request packet. */
93 struct tw_osli_req_context {
94 struct tw_cl_req_handle req_handle;/* tag to track req b/w OSL & CL */
95 struct lock ioctl_wake_timeout_lock_handle;/* non-spin lock used to detect ioctl timeout */
96 struct lock *ioctl_wake_timeout_lock;/* ptr to above lock */
97 struct twa_softc *ctlr; /* ptr to OSL's controller context */
98 TW_VOID *data; /* ptr to data being passed to CL */
99 TW_UINT32 length; /* length of buf being passed to CL */
100 TW_UINT64 deadline;/* request timeout (in absolute time) */
101
102 /*
103 * ptr to, and length of data passed to us from above, in case a buffer
104 * copy was done due to non-compliance to alignment requirements
105 */
106 TW_VOID *real_data;
107 TW_UINT32 real_length;
108
109 TW_UINT32 state; /* request state */
110 TW_UINT32 flags; /* request flags */
111
112 /* error encountered before request submission to CL */
113 TW_UINT32 error_code;
114
115 /* ptr to orig req for use during callback */
116 TW_VOID *orig_req;
117
118 struct tw_cl_link link; /* to link this request in a list */
119 bus_dmamap_t dma_map;/* DMA map for data */
120 struct tw_cl_req_packet req_pkt;/* req pkt understood by CL */
121 };
122
123
124 /* Per-controller structure. */
125 struct twa_softc {
126 struct tw_cl_ctlr_handle ctlr_handle;
127 struct tw_osli_req_context *req_ctx_buf;
128
129 /* Controller state. */
130 TW_UINT8 open;
131 TW_UINT32 flags;
132
133 TW_INT32 device_id;
134 TW_UINT32 alignment;
135 TW_UINT32 sg_size_factor;
136
137 TW_VOID *non_dma_mem;
138 TW_VOID *dma_mem;
139 TW_UINT64 dma_mem_phys;
140
141 /* Request queues and arrays. */
142 struct tw_cl_link req_q_head[TW_OSLI_Q_COUNT];
143
144 struct task deferred_intr_callback;/* taskqueue function */
145 struct spinlock io_lock_handle;/* general purpose lock */
146 struct spinlock *io_lock;/* ptr to general purpose lock */
147 struct spinlock q_lock_handle; /* queue manipulation lock */
148 struct spinlock *q_lock;/* ptr to queue manipulation lock */
149 struct lock sim_lock_handle;/* sim lock shared with cam */
150 struct lock *sim_lock;/* ptr to sim lock */
151
152 struct callout watchdog_callout[2]; /* For command timeout */
153 TW_UINT32 watchdog_index;
154
155 #ifdef TW_OSL_DEBUG
156 struct tw_osli_q_stats q_stats[TW_OSLI_Q_COUNT];/* queue statistics */
157 #endif /* TW_OSL_DEBUG */
158
159 device_t bus_dev; /* bus device */
160 struct cdev *ctrl_dev; /* control device */
161 struct resource *reg_res; /* register interface window */
162 TW_INT32 reg_res_id; /* register resource id */
163 bus_space_handle_t bus_handle; /* bus space handle */
164 bus_space_tag_t bus_tag; /* bus space tag */
165 bus_dma_tag_t parent_tag; /* parent DMA tag */
166 bus_dma_tag_t cmd_tag; /* DMA tag for CL's DMA'able mem */
167 bus_dma_tag_t dma_tag; /* data buffer DMA tag */
168 bus_dma_tag_t ioctl_tag; /* ioctl data buffer DMA tag */
169 bus_dmamap_t cmd_map; /* DMA map for CL's DMA'able mem */
170 bus_dmamap_t ioctl_map; /* DMA map for ioctl data buffers */
171 struct resource *irq_res; /* interrupt resource */
172 TW_INT32 irq_res_id; /* register resource id */
173 TW_INT32 irq_type; /* interrupt type */
174 TW_VOID *intr_handle; /* interrupt handle */
175
176 struct cam_sim *sim; /* sim for this controller */
177 struct cam_path *path; /* peripheral, path, tgt, lun
178 associated with this controller */
179 };
180
181
182
183 /*
184 * Queue primitives.
185 */
186
187 #ifdef TW_OSL_DEBUG
188
189 #define TW_OSLI_Q_INIT(sc, q_type) do { \
190 (sc)->q_stats[q_type].cur_len = 0; \
191 (sc)->q_stats[q_type].max_len = 0; \
192 } while(0)
193
194
195 #define TW_OSLI_Q_INSERT(sc, q_type) do { \
196 struct tw_osli_q_stats *q_stats = &((sc)->q_stats[q_type]); \
197 \
198 if (++(q_stats->cur_len) > q_stats->max_len) \
199 q_stats->max_len = q_stats->cur_len; \
200 } while(0)
201
202
203 #define TW_OSLI_Q_REMOVE(sc, q_type) \
204 (sc)->q_stats[q_type].cur_len--
205
206
207 #else /* TW_OSL_DEBUG */
208
209 #define TW_OSLI_Q_INIT(sc, q_index)
210 #define TW_OSLI_Q_INSERT(sc, q_index)
211 #define TW_OSLI_Q_REMOVE(sc, q_index)
212
213 #endif /* TW_OSL_DEBUG */
214
215
216
217 /* Initialize a queue of requests. */
218 static __inline TW_VOID
tw_osli_req_q_init(struct twa_softc * sc,TW_UINT8 q_type)219 tw_osli_req_q_init(struct twa_softc *sc, TW_UINT8 q_type)
220 {
221 TW_CL_Q_INIT(&(sc->req_q_head[q_type]));
222 TW_OSLI_Q_INIT(sc, q_type);
223 }
224
225
226
227 /* Insert the given request at the head of the given queue (q_type). */
228 static __inline TW_VOID
tw_osli_req_q_insert_head(struct tw_osli_req_context * req,TW_UINT8 q_type)229 tw_osli_req_q_insert_head(struct tw_osli_req_context *req, TW_UINT8 q_type)
230 {
231 spin_lock(req->ctlr->q_lock);
232 TW_CL_Q_INSERT_HEAD(&(req->ctlr->req_q_head[q_type]), &(req->link));
233 TW_OSLI_Q_INSERT(req->ctlr, q_type);
234 spin_unlock(req->ctlr->q_lock);
235 }
236
237
238
239 /* Insert the given request at the tail of the given queue (q_type). */
240 static __inline TW_VOID
tw_osli_req_q_insert_tail(struct tw_osli_req_context * req,TW_UINT8 q_type)241 tw_osli_req_q_insert_tail(struct tw_osli_req_context *req, TW_UINT8 q_type)
242 {
243 spin_lock(req->ctlr->q_lock);
244 TW_CL_Q_INSERT_TAIL(&(req->ctlr->req_q_head[q_type]), &(req->link));
245 TW_OSLI_Q_INSERT(req->ctlr, q_type);
246 spin_unlock(req->ctlr->q_lock);
247 }
248
249
250
251 /* Remove and return the request at the head of the given queue (q_type). */
252 static __inline struct tw_osli_req_context *
tw_osli_req_q_remove_head(struct twa_softc * sc,TW_UINT8 q_type)253 tw_osli_req_q_remove_head(struct twa_softc *sc, TW_UINT8 q_type)
254 {
255 struct tw_osli_req_context *req = NULL;
256 struct tw_cl_link *link;
257
258 spin_lock(sc->q_lock);
259 if ((link = TW_CL_Q_FIRST_ITEM(&(sc->req_q_head[q_type]))) !=
260 TW_CL_NULL) {
261 req = TW_CL_STRUCT_HEAD(link,
262 struct tw_osli_req_context, link);
263 TW_CL_Q_REMOVE_ITEM(&(sc->req_q_head[q_type]), &(req->link));
264 TW_OSLI_Q_REMOVE(sc, q_type);
265 }
266 spin_unlock(sc->q_lock);
267 return(req);
268 }
269
270
271
272 /* Remove the given request from the given queue (q_type). */
273 static __inline TW_VOID
tw_osli_req_q_remove_item(struct tw_osli_req_context * req,TW_UINT8 q_type)274 tw_osli_req_q_remove_item(struct tw_osli_req_context *req, TW_UINT8 q_type)
275 {
276 spin_lock(req->ctlr->q_lock);
277 TW_CL_Q_REMOVE_ITEM(&(req->ctlr->req_q_head[q_type]), &(req->link));
278 TW_OSLI_Q_REMOVE(req->ctlr, q_type);
279 spin_unlock(req->ctlr->q_lock);
280 }
281
282
283
284 #ifdef TW_OSL_DEBUG
285
286 extern TW_INT32 TW_DEBUG_LEVEL_FOR_OSL;
287
288 #define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) \
289 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
290 device_printf(sc->bus_dev, "%s: " fmt "\n", \
291 __func__, ##args)
292
293
294 #define tw_osli_dbg_printf(dbg_level, fmt, args...) \
295 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
296 kprintf("%s: " fmt "\n", __func__, ##args)
297
298 #else /* TW_OSL_DEBUG */
299
300 #define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) do { } while (0)
301 #define tw_osli_dbg_printf(dbg_level, fmt, args...) do { } while (0)
302
303 #endif /* TW_OSL_DEBUG */
304
305
306 /* For regular printing. */
307 #define twa_printf(sc, fmt, args...) \
308 device_printf(((struct twa_softc *)(sc))->bus_dev, fmt, ##args)
309
310 /* For printing in the "consistent error reporting" format. */
311 #define tw_osli_printf(sc, err_specific_desc, args...) \
312 device_printf((sc)->bus_dev, \
313 "%s: (0x%02X: 0x%04X): %s: " err_specific_desc "\n", ##args)
314
315
316
317 #endif /* TW_OSL_H */
318