1 /*-
2 * BSD LICENSE
3 *
4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33 #ifndef _ENA_ADMIN_H_
34 #define _ENA_ADMIN_H_
35
36 enum ena_admin_aq_opcode {
37 ENA_ADMIN_CREATE_SQ = 1,
38
39 ENA_ADMIN_DESTROY_SQ = 2,
40
41 ENA_ADMIN_CREATE_CQ = 3,
42
43 ENA_ADMIN_DESTROY_CQ = 4,
44
45 ENA_ADMIN_GET_FEATURE = 8,
46
47 ENA_ADMIN_SET_FEATURE = 9,
48
49 ENA_ADMIN_GET_STATS = 11,
50 };
51
52 enum ena_admin_aq_completion_status {
53 ENA_ADMIN_SUCCESS = 0,
54
55 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
56
57 ENA_ADMIN_BAD_OPCODE = 2,
58
59 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
60
61 ENA_ADMIN_MALFORMED_REQUEST = 4,
62
63 /* Additional status is provided in ACQ entry extended_status */
64 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
65
66 ENA_ADMIN_UNKNOWN_ERROR = 6,
67 };
68
69 enum ena_admin_aq_feature_id {
70 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
71
72 ENA_ADMIN_MAX_QUEUES_NUM = 2,
73
74 ENA_ADMIN_HW_HINTS = 3,
75
76 ENA_ADMIN_LLQ = 4,
77
78 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
79
80 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
81
82 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,
83
84 ENA_ADMIN_MTU = 14,
85
86 ENA_ADMIN_RSS_HASH_INPUT = 18,
87
88 ENA_ADMIN_INTERRUPT_MODERATION = 20,
89
90 ENA_ADMIN_AENQ_CONFIG = 26,
91
92 ENA_ADMIN_LINK_CONFIG = 27,
93
94 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
95
96 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
97 };
98
99 enum ena_admin_placement_policy_type {
100 /* descriptors and headers are in host memory */
101 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
102
103 /* descriptors and headers are in device memory (a.k.a Low Latency
104 * Queue)
105 */
106 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
107 };
108
109 enum ena_admin_link_types {
110 ENA_ADMIN_LINK_SPEED_1G = 0x1,
111
112 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
113
114 ENA_ADMIN_LINK_SPEED_5G = 0x4,
115
116 ENA_ADMIN_LINK_SPEED_10G = 0x8,
117
118 ENA_ADMIN_LINK_SPEED_25G = 0x10,
119
120 ENA_ADMIN_LINK_SPEED_40G = 0x20,
121
122 ENA_ADMIN_LINK_SPEED_50G = 0x40,
123
124 ENA_ADMIN_LINK_SPEED_100G = 0x80,
125
126 ENA_ADMIN_LINK_SPEED_200G = 0x100,
127
128 ENA_ADMIN_LINK_SPEED_400G = 0x200,
129 };
130
131 enum ena_admin_completion_policy_type {
132 /* completion queue entry for each sq descriptor */
133 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
134
135 /* completion queue entry upon request in sq descriptor */
136 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
137
138 /* current queue head pointer is updated in OS memory upon sq
139 * descriptor request
140 */
141 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
142
143 /* current queue head pointer is updated in OS memory for each sq
144 * descriptor
145 */
146 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
147 };
148
149 /* basic stats return ena_admin_basic_stats while extanded stats return a
150 * buffer (string format) with additional statistics per queue and per
151 * device id
152 */
153 enum ena_admin_get_stats_type {
154 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
155
156 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
157 };
158
159 enum ena_admin_get_stats_scope {
160 ENA_ADMIN_SPECIFIC_QUEUE = 0,
161
162 ENA_ADMIN_ETH_TRAFFIC = 1,
163 };
164
165 struct ena_admin_aq_common_desc {
166 /* 11:0 : command_id
167 * 15:12 : reserved12
168 */
169 uint16_t command_id;
170
171 /* as appears in ena_admin_aq_opcode */
172 uint8_t opcode;
173
174 /* 0 : phase
175 * 1 : ctrl_data - control buffer address valid
176 * 2 : ctrl_data_indirect - control buffer address
177 * points to list of pages with addresses of control
178 * buffers
179 * 7:3 : reserved3
180 */
181 uint8_t flags;
182 };
183
184 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
185 * page list chunk. Used also at the end of indirect mode page list chunks,
186 * for chaining.
187 */
188 struct ena_admin_ctrl_buff_info {
189 uint32_t length;
190
191 struct ena_common_mem_addr address;
192 };
193
194 struct ena_admin_sq {
195 uint16_t sq_idx;
196
197 /* 4:0 : reserved
198 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
199 */
200 uint8_t sq_identity;
201
202 uint8_t reserved1;
203 };
204
205 struct ena_admin_aq_entry {
206 struct ena_admin_aq_common_desc aq_common_descriptor;
207
208 union {
209 uint32_t inline_data_w1[3];
210
211 struct ena_admin_ctrl_buff_info control_buffer;
212 } u;
213
214 uint32_t inline_data_w4[12];
215 };
216
217 struct ena_admin_acq_common_desc {
218 /* command identifier to associate it with the aq descriptor
219 * 11:0 : command_id
220 * 15:12 : reserved12
221 */
222 uint16_t command;
223
224 uint8_t status;
225
226 /* 0 : phase
227 * 7:1 : reserved1
228 */
229 uint8_t flags;
230
231 uint16_t extended_status;
232
233 /* serves as a hint what AQ entries can be revoked */
234 uint16_t sq_head_indx;
235 };
236
237 struct ena_admin_acq_entry {
238 struct ena_admin_acq_common_desc acq_common_descriptor;
239
240 uint32_t response_specific_data[14];
241 };
242
243 struct ena_admin_aq_create_sq_cmd {
244 struct ena_admin_aq_common_desc aq_common_descriptor;
245
246 /* 4:0 : reserved0_w1
247 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
248 */
249 uint8_t sq_identity;
250
251 uint8_t reserved8_w1;
252
253 /* 3:0 : placement_policy - Describing where the SQ
254 * descriptor ring and the SQ packet headers reside:
255 * 0x1 - descriptors and headers are in OS memory,
256 * 0x3 - descriptors and headers in device memory
257 * (a.k.a Low Latency Queue)
258 * 6:4 : completion_policy - Describing what policy
259 * to use for generation completion entry (cqe) in
260 * the CQ associated with this SQ: 0x0 - cqe for each
261 * sq descriptor, 0x1 - cqe upon request in sq
262 * descriptor, 0x2 - current queue head pointer is
263 * updated in OS memory upon sq descriptor request
264 * 0x3 - current queue head pointer is updated in OS
265 * memory for each sq descriptor
266 * 7 : reserved15_w1
267 */
268 uint8_t sq_caps_2;
269
270 /* 0 : is_physically_contiguous - Described if the
271 * queue ring memory is allocated in physical
272 * contiguous pages or split.
273 * 7:1 : reserved17_w1
274 */
275 uint8_t sq_caps_3;
276
277 /* associated completion queue id. This CQ must be created prior to
278 * SQ creation
279 */
280 uint16_t cq_idx;
281
282 /* submission queue depth in entries */
283 uint16_t sq_depth;
284
285 /* SQ physical base address in OS memory. This field should not be
286 * used for Low Latency queues. Has to be page aligned.
287 */
288 struct ena_common_mem_addr sq_ba;
289
290 /* specifies queue head writeback location in OS memory. Valid if
291 * completion_policy is set to completion_policy_head_on_demand or
292 * completion_policy_head. Has to be cache aligned
293 */
294 struct ena_common_mem_addr sq_head_writeback;
295
296 uint32_t reserved0_w7;
297
298 uint32_t reserved0_w8;
299 };
300
301 enum ena_admin_sq_direction {
302 ENA_ADMIN_SQ_DIRECTION_TX = 1,
303
304 ENA_ADMIN_SQ_DIRECTION_RX = 2,
305 };
306
307 struct ena_admin_acq_create_sq_resp_desc {
308 struct ena_admin_acq_common_desc acq_common_desc;
309
310 uint16_t sq_idx;
311
312 uint16_t reserved;
313
314 /* queue doorbell address as an offset to PCIe MMIO REG BAR */
315 uint32_t sq_doorbell_offset;
316
317 /* low latency queue ring base address as an offset to PCIe MMIO
318 * LLQ_MEM BAR
319 */
320 uint32_t llq_descriptors_offset;
321
322 /* low latency queue headers' memory as an offset to PCIe MMIO
323 * LLQ_MEM BAR
324 */
325 uint32_t llq_headers_offset;
326 };
327
328 struct ena_admin_aq_destroy_sq_cmd {
329 struct ena_admin_aq_common_desc aq_common_descriptor;
330
331 struct ena_admin_sq sq;
332 };
333
334 struct ena_admin_acq_destroy_sq_resp_desc {
335 struct ena_admin_acq_common_desc acq_common_desc;
336 };
337
338 struct ena_admin_aq_create_cq_cmd {
339 struct ena_admin_aq_common_desc aq_common_descriptor;
340
341 /* 4:0 : reserved5
342 * 5 : interrupt_mode_enabled - if set, cq operates
343 * in interrupt mode, otherwise - polling
344 * 7:6 : reserved6
345 */
346 uint8_t cq_caps_1;
347
348 /* 4:0 : cq_entry_size_words - size of CQ entry in
349 * 32-bit words, valid values: 4, 8.
350 * 7:5 : reserved7
351 */
352 uint8_t cq_caps_2;
353
354 /* completion queue depth in # of entries. must be power of 2 */
355 uint16_t cq_depth;
356
357 /* msix vector assigned to this cq */
358 uint32_t msix_vector;
359
360 /* cq physical base address in OS memory. CQ must be physically
361 * contiguous
362 */
363 struct ena_common_mem_addr cq_ba;
364 };
365
366 struct ena_admin_acq_create_cq_resp_desc {
367 struct ena_admin_acq_common_desc acq_common_desc;
368
369 uint16_t cq_idx;
370
371 /* actual cq depth in number of entries */
372 uint16_t cq_actual_depth;
373
374 uint32_t numa_node_register_offset;
375
376 uint32_t cq_head_db_register_offset;
377
378 uint32_t cq_interrupt_unmask_register_offset;
379 };
380
381 struct ena_admin_aq_destroy_cq_cmd {
382 struct ena_admin_aq_common_desc aq_common_descriptor;
383
384 uint16_t cq_idx;
385
386 uint16_t reserved1;
387 };
388
389 struct ena_admin_acq_destroy_cq_resp_desc {
390 struct ena_admin_acq_common_desc acq_common_desc;
391 };
392
393 /* ENA AQ Get Statistics command. Extended statistics are placed in control
394 * buffer pointed by AQ entry
395 */
396 struct ena_admin_aq_get_stats_cmd {
397 struct ena_admin_aq_common_desc aq_common_descriptor;
398
399 union {
400 /* command specific inline data */
401 uint32_t inline_data_w1[3];
402
403 struct ena_admin_ctrl_buff_info control_buffer;
404 } u;
405
406 /* stats type as defined in enum ena_admin_get_stats_type */
407 uint8_t type;
408
409 /* stats scope defined in enum ena_admin_get_stats_scope */
410 uint8_t scope;
411
412 uint16_t reserved3;
413
414 /* queue id. used when scope is specific_queue */
415 uint16_t queue_idx;
416
417 /* device id, value 0xFFFF means mine. only privileged device can get
418 * stats of other device
419 */
420 uint16_t device_id;
421 };
422
423 /* Basic Statistics Command. */
424 struct ena_admin_basic_stats {
425 uint32_t tx_bytes_low;
426
427 uint32_t tx_bytes_high;
428
429 uint32_t tx_pkts_low;
430
431 uint32_t tx_pkts_high;
432
433 uint32_t rx_bytes_low;
434
435 uint32_t rx_bytes_high;
436
437 uint32_t rx_pkts_low;
438
439 uint32_t rx_pkts_high;
440
441 uint32_t rx_drops_low;
442
443 uint32_t rx_drops_high;
444 };
445
446 struct ena_admin_acq_get_stats_resp {
447 struct ena_admin_acq_common_desc acq_common_desc;
448
449 struct ena_admin_basic_stats basic_stats;
450 };
451
452 struct ena_admin_get_set_feature_common_desc {
453 /* 1:0 : select - 0x1 - current value; 0x3 - default
454 * value
455 * 7:3 : reserved3
456 */
457 uint8_t flags;
458
459 /* as appears in ena_admin_aq_feature_id */
460 uint8_t feature_id;
461
462 uint16_t reserved16;
463 };
464
465 struct ena_admin_device_attr_feature_desc {
466 uint32_t impl_id;
467
468 uint32_t device_version;
469
470 /* bitmap of ena_admin_aq_feature_id */
471 uint32_t supported_features;
472
473 uint32_t reserved3;
474
475 /* Indicates how many bits are used physical address access. */
476 uint32_t phys_addr_width;
477
478 /* Indicates how many bits are used virtual address access. */
479 uint32_t virt_addr_width;
480
481 /* unicast MAC address (in Network byte order) */
482 uint8_t mac_addr[6];
483
484 uint8_t reserved7[2];
485
486 uint32_t max_mtu;
487 };
488
489 enum ena_admin_llq_header_location {
490 /* header is in descriptor list */
491 ENA_ADMIN_INLINE_HEADER = 1,
492
493 /* header in a separate ring, implies 16B descriptor list entry */
494 ENA_ADMIN_HEADER_RING = 2,
495 };
496
497 enum ena_admin_llq_ring_entry_size {
498 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
499
500 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
501
502 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
503 };
504
505 enum ena_admin_llq_num_descs_before_header {
506 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
507
508 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
509
510 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
511
512 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
513
514 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
515 };
516
517 /* packet descriptor list entry always starts with one or more descriptors,
518 * followed by a header. The rest of the descriptors are located in the
519 * beginning of the subsequent entry. Stride refers to how the rest of the
520 * descriptors are placed. This field is relevant only for inline header
521 * mode
522 */
523 enum ena_admin_llq_stride_ctrl {
524 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
525
526 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
527 };
528
529 struct ena_admin_feature_llq_desc {
530 uint32_t max_llq_num;
531
532 uint32_t max_llq_depth;
533
534 /* use enum ena_admin_llq_header_location */
535 uint16_t header_location_ctrl;
536
537 /* if inline header is specified - this is the size of descriptor
538 * list entry. If header in a separate ring is specified - this is
539 * the size of header ring entry. use enum
540 * ena_admin_llq_ring_entry_size
541 */
542 uint16_t entry_size_ctrl;
543
544 /* valid only if inline header is specified. First entry associated
545 * with the packet includes descriptors and header. Rest of the
546 * entries occupied by descriptors. This parameter defines the max
547 * number of descriptors precedding the header in the first entry.
548 * Values: use enum llq_num_descs_before_header
549 */
550 uint16_t desc_num_before_header_ctrl;
551
552 /* valid, only if inline header is specified. Note, use enum
553 * ena_admin_llq_stide_ctrl
554 */
555 uint16_t descriptors_stride_ctrl;
556 };
557
558 struct ena_admin_queue_feature_desc {
559 /* including LLQs */
560 uint32_t max_sq_num;
561
562 uint32_t max_sq_depth;
563
564 uint32_t max_cq_num;
565
566 uint32_t max_cq_depth;
567
568 uint32_t max_legacy_llq_num;
569
570 uint32_t max_legacy_llq_depth;
571
572 uint32_t max_header_size;
573
574 /* Maximum Descriptors number, including meta descriptor, allowed for
575 * a single Tx packet
576 */
577 uint16_t max_packet_tx_descs;
578
579 /* Maximum Descriptors number allowed for a single Rx packet */
580 uint16_t max_packet_rx_descs;
581 };
582
583 struct ena_admin_set_feature_mtu_desc {
584 /* exclude L2 */
585 uint32_t mtu;
586 };
587
588 struct ena_admin_set_feature_host_attr_desc {
589 /* host OS info base address in OS memory. host info is 4KB of
590 * physically contiguous
591 */
592 struct ena_common_mem_addr os_info_ba;
593
594 /* host debug area base address in OS memory. debug area must be
595 * physically contiguous
596 */
597 struct ena_common_mem_addr debug_ba;
598
599 /* debug area size */
600 uint32_t debug_area_size;
601 };
602
603 struct ena_admin_feature_intr_moder_desc {
604 /* interrupt delay granularity in usec */
605 uint16_t intr_delay_resolution;
606
607 uint16_t reserved;
608 };
609
610 struct ena_admin_get_feature_link_desc {
611 /* Link speed in Mb */
612 uint32_t speed;
613
614 /* bit field of enum ena_admin_link types */
615 uint32_t supported;
616
617 /* 0 : autoneg
618 * 1 : duplex - Full Duplex
619 * 31:2 : reserved2
620 */
621 uint32_t flags;
622 };
623
624 struct ena_admin_feature_aenq_desc {
625 /* bitmask for AENQ groups the device can report */
626 uint32_t supported_groups;
627
628 /* bitmask for AENQ groups to report */
629 uint32_t enabled_groups;
630 };
631
632 struct ena_admin_feature_offload_desc {
633 /* 0 : TX_L3_csum_ipv4
634 * 1 : TX_L4_ipv4_csum_part - The checksum field
635 * should be initialized with pseudo header checksum
636 * 2 : TX_L4_ipv4_csum_full
637 * 3 : TX_L4_ipv6_csum_part - The checksum field
638 * should be initialized with pseudo header checksum
639 * 4 : TX_L4_ipv6_csum_full
640 * 5 : tso_ipv4
641 * 6 : tso_ipv6
642 * 7 : tso_ecn
643 */
644 uint32_t tx;
645
646 /* Receive side supported stateless offload
647 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
648 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
649 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
650 * 3 : RX_hash - Hash calculation
651 */
652 uint32_t rx_supported;
653
654 uint32_t rx_enabled;
655 };
656
657 enum ena_admin_hash_functions {
658 ENA_ADMIN_TOEPLITZ = 1,
659
660 ENA_ADMIN_CRC32 = 2,
661 };
662
663 struct ena_admin_feature_rss_flow_hash_control {
664 uint32_t keys_num;
665
666 uint32_t reserved;
667
668 uint32_t key[10];
669 };
670
671 struct ena_admin_feature_rss_flow_hash_function {
672 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
673 uint32_t supported_func;
674
675 /* 7:0 : selected_func - bitmask of
676 * ena_admin_hash_functions
677 */
678 uint32_t selected_func;
679
680 /* initial value */
681 uint32_t init_val;
682 };
683
684 /* RSS flow hash protocols */
685 enum ena_admin_flow_hash_proto {
686 ENA_ADMIN_RSS_TCP4 = 0,
687
688 ENA_ADMIN_RSS_UDP4 = 1,
689
690 ENA_ADMIN_RSS_TCP6 = 2,
691
692 ENA_ADMIN_RSS_UDP6 = 3,
693
694 ENA_ADMIN_RSS_IP4 = 4,
695
696 ENA_ADMIN_RSS_IP6 = 5,
697
698 ENA_ADMIN_RSS_IP4_FRAG = 6,
699
700 ENA_ADMIN_RSS_NOT_IP = 7,
701
702 /* TCPv6 with extension header */
703 ENA_ADMIN_RSS_TCP6_EX = 8,
704
705 /* IPv6 with extension header */
706 ENA_ADMIN_RSS_IP6_EX = 9,
707
708 ENA_ADMIN_RSS_PROTO_NUM = 16,
709 };
710
711 /* RSS flow hash fields */
712 enum ena_admin_flow_hash_fields {
713 /* Ethernet Dest Addr */
714 ENA_ADMIN_RSS_L2_DA = BIT(0),
715
716 /* Ethernet Src Addr */
717 ENA_ADMIN_RSS_L2_SA = BIT(1),
718
719 /* ipv4/6 Dest Addr */
720 ENA_ADMIN_RSS_L3_DA = BIT(2),
721
722 /* ipv4/6 Src Addr */
723 ENA_ADMIN_RSS_L3_SA = BIT(3),
724
725 /* tcp/udp Dest Port */
726 ENA_ADMIN_RSS_L4_DP = BIT(4),
727
728 /* tcp/udp Src Port */
729 ENA_ADMIN_RSS_L4_SP = BIT(5),
730 };
731
732 struct ena_admin_proto_input {
733 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
734 uint16_t fields;
735
736 uint16_t reserved2;
737 };
738
739 struct ena_admin_feature_rss_hash_control {
740 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
741
742 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
743
744 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
745
746 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
747 };
748
749 struct ena_admin_feature_rss_flow_hash_input {
750 /* supported hash input sorting
751 * 1 : L3_sort - support swap L3 addresses if DA is
752 * smaller than SA
753 * 2 : L4_sort - support swap L4 ports if DP smaller
754 * SP
755 */
756 uint16_t supported_input_sort;
757
758 /* enabled hash input sorting
759 * 1 : enable_L3_sort - enable swap L3 addresses if
760 * DA smaller than SA
761 * 2 : enable_L4_sort - enable swap L4 ports if DP
762 * smaller than SP
763 */
764 uint16_t enabled_input_sort;
765 };
766
767 enum ena_admin_os_type {
768 ENA_ADMIN_OS_LINUX = 1,
769
770 ENA_ADMIN_OS_WIN = 2,
771
772 ENA_ADMIN_OS_DPDK = 3,
773
774 ENA_ADMIN_OS_FREEBSD = 4,
775
776 ENA_ADMIN_OS_IPXE = 5,
777 };
778
779 struct ena_admin_host_info {
780 /* defined in enum ena_admin_os_type */
781 uint32_t os_type;
782
783 /* os distribution string format */
784 uint8_t os_dist_str[128];
785
786 /* OS distribution numeric format */
787 uint32_t os_dist;
788
789 /* kernel version string format */
790 uint8_t kernel_ver_str[32];
791
792 /* Kernel version numeric format */
793 uint32_t kernel_ver;
794
795 /* 7:0 : major
796 * 15:8 : minor
797 * 23:16 : sub_minor
798 */
799 uint32_t driver_version;
800
801 /* features bitmap */
802 uint32_t supported_network_features[4];
803 };
804
805 struct ena_admin_rss_ind_table_entry {
806 uint16_t cq_idx;
807
808 uint16_t reserved;
809 };
810
811 struct ena_admin_feature_rss_ind_table {
812 /* min supported table size (2^min_size) */
813 uint16_t min_size;
814
815 /* max supported table size (2^max_size) */
816 uint16_t max_size;
817
818 /* table size (2^size) */
819 uint16_t size;
820
821 uint16_t reserved;
822
823 /* index of the inline entry. 0xFFFFFFFF means invalid */
824 uint32_t inline_index;
825
826 /* used for updating single entry, ignored when setting the entire
827 * table through the control buffer.
828 */
829 struct ena_admin_rss_ind_table_entry inline_entry;
830 };
831
832 /* When hint value is 0, driver should use it's own predefined value */
833 struct ena_admin_ena_hw_hints {
834 /* value in ms */
835 uint16_t mmio_read_timeout;
836
837 /* value in ms */
838 uint16_t driver_watchdog_timeout;
839
840 /* Per packet tx completion timeout. value in ms */
841 uint16_t missing_tx_completion_timeout;
842
843 uint16_t missed_tx_completion_count_threshold_to_reset;
844
845 /* value in ms */
846 uint16_t admin_completion_tx_timeout;
847
848 uint16_t netdev_wd_timeout;
849
850 uint16_t max_tx_sgl_size;
851
852 uint16_t max_rx_sgl_size;
853
854 uint16_t reserved[8];
855 };
856
857 struct ena_admin_get_feat_cmd {
858 struct ena_admin_aq_common_desc aq_common_descriptor;
859
860 struct ena_admin_ctrl_buff_info control_buffer;
861
862 struct ena_admin_get_set_feature_common_desc feat_common;
863
864 uint32_t raw[11];
865 };
866
867 struct ena_admin_get_feat_resp {
868 struct ena_admin_acq_common_desc acq_common_desc;
869
870 union {
871 uint32_t raw[14];
872
873 struct ena_admin_device_attr_feature_desc dev_attr;
874
875 struct ena_admin_feature_llq_desc llq;
876
877 struct ena_admin_queue_feature_desc max_queue;
878
879 struct ena_admin_feature_aenq_desc aenq;
880
881 struct ena_admin_get_feature_link_desc link;
882
883 struct ena_admin_feature_offload_desc offload;
884
885 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
886
887 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
888
889 struct ena_admin_feature_rss_ind_table ind_table;
890
891 struct ena_admin_feature_intr_moder_desc intr_moderation;
892
893 struct ena_admin_ena_hw_hints hw_hints;
894 } u;
895 };
896
897 struct ena_admin_set_feat_cmd {
898 struct ena_admin_aq_common_desc aq_common_descriptor;
899
900 struct ena_admin_ctrl_buff_info control_buffer;
901
902 struct ena_admin_get_set_feature_common_desc feat_common;
903
904 union {
905 uint32_t raw[11];
906
907 /* mtu size */
908 struct ena_admin_set_feature_mtu_desc mtu;
909
910 /* host attributes */
911 struct ena_admin_set_feature_host_attr_desc host_attr;
912
913 /* AENQ configuration */
914 struct ena_admin_feature_aenq_desc aenq;
915
916 /* rss flow hash function */
917 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
918
919 /* rss flow hash input */
920 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
921
922 /* rss indirection table */
923 struct ena_admin_feature_rss_ind_table ind_table;
924 } u;
925 };
926
927 struct ena_admin_set_feat_resp {
928 struct ena_admin_acq_common_desc acq_common_desc;
929
930 union {
931 uint32_t raw[14];
932 } u;
933 };
934
935 struct ena_admin_aenq_common_desc {
936 uint16_t group;
937
938 uint16_t syndrom;
939
940 /* 0 : phase */
941 uint8_t flags;
942
943 uint8_t reserved1[3];
944
945 uint32_t timestamp_low;
946
947 uint32_t timestamp_high;
948 };
949
950 /* asynchronous event notification groups */
951 enum ena_admin_aenq_group {
952 ENA_ADMIN_LINK_CHANGE = 0,
953
954 ENA_ADMIN_FATAL_ERROR = 1,
955
956 ENA_ADMIN_WARNING = 2,
957
958 ENA_ADMIN_NOTIFICATION = 3,
959
960 ENA_ADMIN_KEEP_ALIVE = 4,
961
962 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
963 };
964
965 enum ena_admin_aenq_notification_syndrom {
966 ENA_ADMIN_SUSPEND = 0,
967
968 ENA_ADMIN_RESUME = 1,
969
970 ENA_ADMIN_UPDATE_HINTS = 2,
971 };
972
973 struct ena_admin_aenq_entry {
974 struct ena_admin_aenq_common_desc aenq_common_desc;
975
976 /* command specific inline data */
977 uint32_t inline_data_w4[12];
978 };
979
980 struct ena_admin_aenq_link_change_desc {
981 struct ena_admin_aenq_common_desc aenq_common_desc;
982
983 /* 0 : link_status */
984 uint32_t flags;
985 };
986
987 struct ena_admin_aenq_keep_alive_desc {
988 struct ena_admin_aenq_common_desc aenq_common_desc;
989
990 uint32_t rx_drops_low;
991
992 uint32_t rx_drops_high;
993 };
994
995 struct ena_admin_ena_mmio_req_read_less_resp {
996 uint16_t req_id;
997
998 uint16_t reg_off;
999
1000 /* value is valid when poll is cleared */
1001 uint32_t reg_val;
1002 };
1003
1004 /* aq_common_desc */
1005 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1006 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1007 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1008 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1009 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1010 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1011
1012 /* sq */
1013 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1014 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1015
1016 /* acq_common_desc */
1017 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1018 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1019
1020 /* aq_create_sq_cmd */
1021 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1022 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1023 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1024 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1025 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1026 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1027
1028 /* aq_create_cq_cmd */
1029 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1030 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1031 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1032
1033 /* get_set_feature_common_desc */
1034 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1035
1036 /* get_feature_link_desc */
1037 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1038 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1039 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1040
1041 /* feature_offload_desc */
1042 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1043 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1044 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1045 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1046 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1047 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1048 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1049 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1050 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1051 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1052 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1053 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1054 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1055 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1056 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1057 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1058 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1059 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1060 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1061 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1062 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1063 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1064
1065 /* feature_rss_flow_hash_function */
1066 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1067 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1068
1069 /* feature_rss_flow_hash_input */
1070 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1071 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1072 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1073 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1074 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1075 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1076 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1077 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1078
1079 /* host_info */
1080 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1081 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1082 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1083 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1084 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1085
1086 /* aenq_common_desc */
1087 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1088
1089 /* aenq_link_change_desc */
1090 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1091
1092 #if !defined(ENA_DEFS_LINUX_MAINLINE)
get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc * p)1093 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1094 {
1095 return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1096 }
1097
set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc * p,uint16_t val)1098 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1099 {
1100 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1101 }
1102
get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc * p)1103 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1104 {
1105 return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1106 }
1107
set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc * p,uint8_t val)1108 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1109 {
1110 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1111 }
1112
get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc * p)1113 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1114 {
1115 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1116 }
1117
set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc * p,uint8_t val)1118 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1119 {
1120 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1121 }
1122
get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc * p)1123 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1124 {
1125 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1126 }
1127
set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc * p,uint8_t val)1128 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1129 {
1130 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1131 }
1132
get_ena_admin_sq_sq_direction(const struct ena_admin_sq * p)1133 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1134 {
1135 return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1136 }
1137
set_ena_admin_sq_sq_direction(struct ena_admin_sq * p,uint8_t val)1138 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1139 {
1140 p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1141 }
1142
get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc * p)1143 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1144 {
1145 return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1146 }
1147
set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc * p,uint16_t val)1148 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1149 {
1150 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1151 }
1152
get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc * p)1153 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1154 {
1155 return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1156 }
1157
set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc * p,uint8_t val)1158 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1159 {
1160 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1161 }
1162
get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd * p)1163 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1164 {
1165 return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1166 }
1167
set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1168 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1169 {
1170 p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1171 }
1172
get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd * p)1173 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1174 {
1175 return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1176 }
1177
set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1178 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1179 {
1180 p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1181 }
1182
get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd * p)1183 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1184 {
1185 return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1186 }
1187
set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1188 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1189 {
1190 p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1191 }
1192
get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd * p)1193 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1194 {
1195 return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1196 }
1197
set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1198 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1199 {
1200 p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1201 }
1202
get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd * p)1203 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1204 {
1205 return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1206 }
1207
set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd * p,uint8_t val)1208 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1209 {
1210 p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1211 }
1212
get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd * p)1213 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1214 {
1215 return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1216 }
1217
set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd * p,uint8_t val)1218 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1219 {
1220 p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1221 }
1222
get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc * p)1223 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1224 {
1225 return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1226 }
1227
set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc * p,uint8_t val)1228 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1229 {
1230 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1231 }
1232
get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc * p)1233 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1234 {
1235 return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1236 }
1237
set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc * p,uint32_t val)1238 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1239 {
1240 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1241 }
1242
get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc * p)1243 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1244 {
1245 return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1246 }
1247
set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc * p,uint32_t val)1248 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1249 {
1250 p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1251 }
1252
get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc * p)1253 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1254 {
1255 return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1256 }
1257
set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc * p,uint32_t val)1258 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1259 {
1260 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1261 }
1262
get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc * p)1263 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1264 {
1265 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1266 }
1267
set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc * p,uint32_t val)1268 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1269 {
1270 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1271 }
1272
get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc * p)1273 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1274 {
1275 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1276 }
1277
set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc * p,uint32_t val)1278 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1279 {
1280 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1281 }
1282
get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc * p)1283 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1284 {
1285 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1286 }
1287
set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc * p,uint32_t val)1288 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1289 {
1290 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1291 }
1292
get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc * p)1293 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1294 {
1295 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1296 }
1297
set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc * p,uint32_t val)1298 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1299 {
1300 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1301 }
1302
get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc * p)1303 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1304 {
1305 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1306 }
1307
set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc * p,uint32_t val)1308 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1309 {
1310 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1311 }
1312
get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc * p)1313 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1314 {
1315 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1316 }
1317
set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc * p,uint32_t val)1318 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1319 {
1320 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1321 }
1322
get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc * p)1323 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1324 {
1325 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1326 }
1327
set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc * p,uint32_t val)1328 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1329 {
1330 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1331 }
1332
get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc * p)1333 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1334 {
1335 return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1336 }
1337
set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc * p,uint32_t val)1338 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1339 {
1340 p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1341 }
1342
get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc * p)1343 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1344 {
1345 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1346 }
1347
set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc * p,uint32_t val)1348 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1349 {
1350 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1351 }
1352
get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc * p)1353 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1354 {
1355 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1356 }
1357
set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc * p,uint32_t val)1358 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1359 {
1360 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1361 }
1362
get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc * p)1363 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1364 {
1365 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1366 }
1367
set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc * p,uint32_t val)1368 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1369 {
1370 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1371 }
1372
get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function * p)1373 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1374 {
1375 return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1376 }
1377
set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function * p,uint32_t val)1378 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1379 {
1380 p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1381 }
1382
get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function * p)1383 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1384 {
1385 return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1386 }
1387
set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function * p,uint32_t val)1388 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1389 {
1390 p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1391 }
1392
get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1393 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1394 {
1395 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1396 }
1397
set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1398 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1399 {
1400 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1401 }
1402
get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1403 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1404 {
1405 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1406 }
1407
set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1408 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1409 {
1410 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1411 }
1412
get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1413 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1414 {
1415 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1416 }
1417
set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1418 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1419 {
1420 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1421 }
1422
get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1423 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1424 {
1425 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1426 }
1427
set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1428 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1429 {
1430 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1431 }
1432
get_ena_admin_host_info_major(const struct ena_admin_host_info * p)1433 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1434 {
1435 return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1436 }
1437
set_ena_admin_host_info_major(struct ena_admin_host_info * p,uint32_t val)1438 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1439 {
1440 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1441 }
1442
get_ena_admin_host_info_minor(const struct ena_admin_host_info * p)1443 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1444 {
1445 return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1446 }
1447
set_ena_admin_host_info_minor(struct ena_admin_host_info * p,uint32_t val)1448 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1449 {
1450 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1451 }
1452
get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info * p)1453 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1454 {
1455 return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1456 }
1457
set_ena_admin_host_info_sub_minor(struct ena_admin_host_info * p,uint32_t val)1458 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1459 {
1460 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1461 }
1462
get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc * p)1463 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1464 {
1465 return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1466 }
1467
set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc * p,uint8_t val)1468 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1469 {
1470 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1471 }
1472
get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc * p)1473 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1474 {
1475 return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1476 }
1477
set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc * p,uint32_t val)1478 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1479 {
1480 p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1481 }
1482
1483 #endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
1484 #endif /*_ENA_ADMIN_H_ */
1485