1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/renesas,9series.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas 9-series I2C PCIe clock generators
8
9description: |
10  The Renesas 9-series are I2C PCIe clock generators providing
11  from 1 to 20 output clocks.
12
13  When referencing the provided clock in the DT using phandle
14  and clock specifier, the following mapping applies:
15
16  - 9FGV0241:
17    0 -- DIF0
18    1 -- DIF1
19  - 9FGV0441:
20    0 -- DIF0
21    1 -- DIF1
22    2 -- DIF2
23    3 -- DIF3
24  - 9FGV0841:
25    0 -- DIF0
26    1 -- DIF1
27    2 -- DIF2
28    3 -- DIF3
29    4 -- DIF4
30    5 -- DIF5
31    6 -- DIF6
32    7 -- DIF7
33
34maintainers:
35  - Marek Vasut <marex@denx.de>
36
37properties:
38  compatible:
39    enum:
40      - renesas,9fgv0241
41      - renesas,9fgv0441
42      - renesas,9fgv0841
43
44  reg:
45    description: I2C device address
46    enum: [ 0x68, 0x6a ]
47
48  '#clock-cells':
49    const: 1
50
51  clocks:
52    items:
53      - description: XTal input clock
54
55  renesas,out-amplitude-microvolt:
56    enum: [ 600000, 700000, 800000, 900000 ]
57    description: Output clock signal amplitude
58
59  renesas,out-spread-spectrum:
60    $ref: /schemas/types.yaml#/definitions/uint32
61    enum: [ 100000, 99750, 99500 ]
62    description: Output clock down spread in pcm (1/1000 of percent)
63
64patternProperties:
65  "^DIF[0-19]$":
66    type: object
67    description:
68      Description of one of the outputs (DIF0..DIF19).
69
70    properties:
71      renesas,slew-rate:
72        $ref: /schemas/types.yaml#/definitions/uint32
73        enum: [ 2000000, 3000000 ]
74        description: Output clock slew rate select in V/ns
75
76    additionalProperties: false
77
78required:
79  - compatible
80  - reg
81  - clocks
82  - '#clock-cells'
83
84additionalProperties: false
85
86examples:
87  - |
88    /* 25MHz reference crystal */
89    ref25: ref25m {
90        compatible = "fixed-clock";
91        #clock-cells = <0>;
92        clock-frequency = <25000000>;
93    };
94
95    i2c@0 {
96        reg = <0x0 0x100>;
97        #address-cells = <1>;
98        #size-cells = <0>;
99
100        rs9: clock-generator@6a {
101            compatible = "renesas,9fgv0241";
102            reg = <0x6a>;
103            #clock-cells = <1>;
104
105            clocks = <&ref25m>;
106
107            DIF0 {
108                renesas,slew-rate = <3000000>;
109            };
110        };
111    };
112
113...
114