1// SPDX-License-Identifier: GPL-2.0+
2/dts-v1/;
3
4#include "aspeed-g5.dtsi"
5#include <dt-bindings/gpio/aspeed-gpio.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7
8/ {
9	model = "Tyan S7106 BMC";
10	compatible = "tyan,s7106-bmc", "aspeed,ast2500";
11
12	chosen {
13		stdout-path = &uart5;
14		bootargs = "console=ttyS4,115200 earlycon";
15	};
16
17	memory@80000000 {
18		device_type = "memory";
19		reg = <0x80000000 0x20000000>;
20	};
21
22	reserved-memory {
23		#address-cells = <1>;
24		#size-cells = <1>;
25		ranges;
26
27		p2a_memory: region@987f0000 {
28			no-map;
29			reg = <0x987f0000 0x00010000>; /* 64KB */
30		};
31
32		vga_memory: framebuffer@9f000000 {
33			no-map;
34			reg = <0x9f000000 0x01000000>; /* 16M */
35		};
36
37		gfx_memory: framebuffer {
38			size = <0x01000000>; /* 16M */
39			alignment = <0x01000000>;
40			compatible = "shared-dma-pool";
41			reusable;
42		};
43	};
44
45	leds {
46		compatible = "gpio-leds";
47
48		identify {
49			gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
50		};
51
52		heartbeat {
53			gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;
54		};
55	};
56
57	iio-hwmon {
58		compatible = "iio-hwmon";
59		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
60			<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
61			<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
62			<&adc 12>, <&adc 13>, <&adc 14>;
63	};
64
65	iio-hwmon-battery {
66		compatible = "iio-hwmon";
67		io-channels = <&adc 15>;
68	};
69};
70
71&fmc {
72	status = "okay";
73	flash@0 {
74		label = "bmc";
75		status = "okay";
76		m25p,fast-read;
77#include "openbmc-flash-layout.dtsi"
78	};
79};
80
81&spi1 {
82	status = "okay";
83	pinctrl-names = "default";
84	pinctrl-0 = <&pinctrl_spi1_default>;
85
86	flash@0 {
87		status = "okay";
88		label = "pnor";
89		m25p,fast-read;
90	};
91};
92
93&uart1 {
94	/* Rear RS-232 connector */
95	status = "okay";
96	pinctrl-names = "default";
97	pinctrl-0 = <&pinctrl_txd1_default
98			&pinctrl_rxd1_default>;
99};
100
101&uart2 {
102	/* RS-232 connector on header */
103	status = "okay";
104	pinctrl-names = "default";
105	pinctrl-0 = <&pinctrl_txd2_default
106			&pinctrl_rxd2_default>;
107};
108
109&uart3 {
110	/* Alternative to vuart to internally connect (route) to uart1
111	 * when vuart cannot be used due to BIOS limitations.
112	 */
113	status = "okay";
114};
115
116&uart4 {
117	/* Alternative to vuart to internally connect (route) to the
118	 * external port usually used by uart1 when vuart cannot be
119	 * used due to BIOS limitations.
120	 */
121	status = "okay";
122};
123
124&uart5 {
125	/* BMC "debug" (console) UART; connected to RS-232 connector
126	 * on header; selectable via jumpers as alternative to uart2
127	 */
128	status = "okay";
129};
130
131&uart_routing {
132	status = "okay";
133};
134
135&vuart {
136	status = "okay";
137
138	/* We enable the VUART here, but leave it in a state that does
139	 * not interfere with the SuperIO. The goal is to have both the
140	 * VUART and the SuperIO available and decide at runtime whether
141	 * the VUART should actually be used. For that reason, configure
142	 * an "invalid" IO address and an IRQ that is not used by the
143	 * BMC.
144	 */
145
146	aspeed,lpc-io-reg = <0xffff>;
147	aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
148};
149
150&lpc_ctrl {
151	status = "okay";
152};
153
154&p2a {
155	status = "okay";
156	memory-region = <&p2a_memory>;
157};
158
159&lpc_snoop {
160	status = "okay";
161	snoop-ports = <0x80>;
162};
163
164&adc {
165	status = "okay";
166};
167
168&vhub {
169	status = "okay";
170};
171
172&pwm_tacho {
173	status = "okay";
174	pinctrl-names = "default";
175	pinctrl-0 = <&pinctrl_pwm0_default
176			&pinctrl_pwm1_default
177			&pinctrl_pwm3_default
178			&pinctrl_pwm4_default>;
179
180	/* CPU fan #0 */
181	fan@0 {
182		reg = <0x00>;
183		aspeed,fan-tach-ch = /bits/ 8 <0x00>;
184	};
185
186	/* CPU fan #1 */
187	fan@1 {
188		reg = <0x01>;
189		aspeed,fan-tach-ch = /bits/ 8 <0x01>;
190	};
191
192	/* PWM group for chassis fans #1, #2, #3 and #4  */
193	fan@2 {
194		reg = <0x03>;
195		aspeed,fan-tach-ch = /bits/ 8 <0x02>;
196	};
197
198	fan@3 {
199		reg = <0x03>;
200		aspeed,fan-tach-ch = /bits/ 8 <0x03>;
201	};
202
203	fan@4 {
204		reg = <0x03>;
205		aspeed,fan-tach-ch = /bits/ 8 <0x04>;
206	};
207
208	fan@5 {
209		reg = <0x03>;
210		aspeed,fan-tach-ch = /bits/ 8 <0x05>;
211	};
212
213	/* PWM group for chassis fans #5 and #6  */
214	fan@6 {
215		reg = <0x04>;
216		aspeed,fan-tach-ch = /bits/ 8 <0x06>;
217	};
218
219	fan@7 {
220		reg = <0x04>;
221		aspeed,fan-tach-ch = /bits/ 8 <0x07>;
222	};
223};
224
225&i2c0 {
226	status = "okay";
227
228	/* Hardware monitor with temperature sensors */
229	nct7802@28 {
230		compatible = "nuvoton,nct7802";
231		reg = <0x28>;
232
233		#address-cells = <1>;
234		#size-cells = <0>;
235
236		channel@0 { /* LTD */
237			reg = <0>;
238		};
239
240		channel@1 { /* RTD1 */
241			reg = <1>;
242			sensor-type = "temperature";
243			temperature-mode = "thermistor";
244		};
245
246		channel@2 { /* RTD2 */
247			reg = <2>;
248			sensor-type = "temperature";
249			temperature-mode = "thermistor";
250		};
251
252		channel@3 { /* RTD3 */
253			reg = <3>;
254			sensor-type = "temperature";
255		};
256	};
257
258	/* Also connected to:
259	 * - IPMB pin header
260	 * - CPU #0 memory error LED @ 0x3A
261	 * - CPU #1 memory error LED @ 0x3C
262	 */
263};
264
265&i2c1 {
266	/* Directly connected to PCH SMBUS #0 */
267	status = "okay";
268};
269
270&i2c2 {
271	status = "okay";
272
273	/* BMC EEPROM, incl. mainboard FRU */
274	eeprom@50 {
275		compatible = "atmel,24c256";
276		reg = <0x50>;
277	};
278
279	/* Also connected to:
280	 * - fan header
281	 * - mini-SAS HD connector
282	 * - SSATA SGPIO
283	 * - via switch (BMC_SMB3_PCH_IE_SML3_EN, active low)
284	 *   to PCH SMBUS #3
285	 */
286};
287
288&i2c3 {
289	status = "okay";
290
291	/* PSU1 FRU @ 0xA0 */
292	eeprom@50 {
293		compatible = "atmel,24c02";
294		reg = <0x50>;
295	};
296
297	/* PSU2 FRU @ 0xA2 */
298	eeprom@51 {
299		compatible = "atmel,24c02";
300		reg = <0x51>;
301	};
302
303	/* PSU1 @ 0xB0 */
304	power-supply@58 {
305		compatible = "pmbus";
306		reg = <0x58>;
307	};
308
309	/* PSU2 @ 0xB2 */
310	power-supply@59 {
311		compatible = "pmbus";
312		reg = <0x59>;
313	};
314
315	/* Also connected to:
316	 * - PCH SMBUS #1
317	 */
318};
319
320&i2c4 {
321	status = "okay";
322
323	/* Connected to:
324	 * - PCH SMBUS #2
325	 */
326
327	/* Connected via switch to:
328	 * - CPU #0 channels ABC VDDQ @ 0x80
329	 * - CPU #0 channels DEF VDDQ @ 0x81
330	 * - CPU #1 channels ABC VDDQ @ 0x82
331	 * - CPU #1 channels DEF VDDQ @ 0x83
332	 * - CPU #0 VCCIO & VMCP @ 0x52
333	 * - CPU #1 VCCIO & VMCP @ 0x53
334	 * - CPU #0 VCCIN @ 0xC0
335	 * - CPU #0 VSA @ 0xC2
336	 * - CPU #1 VCCIN @ 0xC4
337	 * - CPU #1 VSA @ 0xC6
338	 * - J110
339	 */
340};
341
342&i2c5 {
343	status = "okay";
344
345	/* Connected via switch (PCH_BMC_SMB_SW_P) to:
346	 * - mainboard FRU @ 0xAE
347	 * - XDP connector
348	 * - ME debug header
349	 * - clock buffer @ 0xD8
350	 * - i2c4 via switch (PCH_VR_SMBUS_SW_P; controlled by PCH)
351	 * - PCH SMBUS
352	 */
353};
354
355&i2c6 {
356	status = "okay";
357
358	/* Connected via switch (BMC_PE_SMB_EN_1_N) to
359	 * bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to:
360	 * - 0,0: PCIE slot 1, SMB #1
361	 * - 0,1: PCIE slot 1, SMB #2
362	 * - 1,0: PCIE slot 2, SMB #1
363	 * - 1,1: PCIE slot 2, SMB #2
364	 */
365
366	/* Connected via switch (BMC_PE_SMB_EN_2_N) to
367	 * bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to:
368	 * - 0,0: OCP0 (A) SMB
369	 * - 0,1: OCP0 (C) SMB
370	 * - 1,0: OCP1 (A) SMB
371	 * - 1,1: NC
372	 */
373};
374
375&i2c7 {
376	status = "okay";
377
378	/* Connected to:
379	 * - PCH SMBUS #4
380	 */
381};
382
383&i2c8 {
384	status = "okay";
385
386	/* Not connected */
387};
388
389&mac0 {
390	status = "okay";
391	use-ncsi;
392	pinctrl-names = "default";
393	pinctrl-0 = <&pinctrl_rmii1_default>;
394};
395
396&mac1 {
397	status = "okay";
398	pinctrl-names = "default";
399	pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
400};
401
402&ibt {
403	status = "okay";
404};
405
406&kcs1 {
407	status = "okay";
408	aspeed,lpc-io-reg = <0xca8>;
409};
410
411&kcs3 {
412	status = "okay";
413	aspeed,lpc-io-reg = <0xca2>;
414};
415
416/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */
417&gfx {
418	status = "okay";
419	memory-region = <&gfx_memory>;
420};
421
422/* We're following the GPIO naming as defined at
423 * https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md.
424 *
425 * Notes on led-identify and id-button:
426 * - A physical button is connected to id-button which
427 *   triggers the clock on a D flip-flop. The /Q output of the
428 *   flip-flop drives its D input.
429 * - The flip-flop's Q output drives led-identify which is
430 *   connected to LEDs.
431 * - With that, every button press toggles the LED between on and off.
432 *
433 * Notes on power-, reset- and nmi- button and control:
434 * - The -button signals can be used to monitor physical buttons.
435 * - The -control signals can be used to actuate the specific
436 *   operation.
437 * - In hardware, the -button signals are connected to the -control
438 *   signals through drivers with the -control signals being
439 *   protected through diodes.
440 */
441&gpio {
442	status = "okay";
443	gpio-line-names =
444	/*A0*/		"",
445	/*A1*/		"",
446	/*A2*/		"led-identify", /* in/out: BMC_IDLED_ON_N */
447	/*A3*/		"",
448	/*A4*/		"",
449	/*A5*/		"",
450	/*A6*/		"",
451	/*A7*/		"",
452	/*B0-B7*/	"","","","","","","","",
453	/*C0*/		"",
454	/*C1*/		"",
455	/*C2*/		"",
456	/*C3*/		"",
457	/*C4*/		"id-button", /* in/out: BMC_IDBTN_IN_OUT_N */
458	/*C5*/		"post-complete", /* in: FM_BIOS_POST_CMPLT_N */
459	/*C6*/		"",
460	/*C7*/		"",
461	/*D0*/		"",
462	/*D1*/		"",
463	/*D2*/		"power-chassis-good", /* in: SYS_PWROK_BUF */
464	/*D3*/		"platform-reset", /* in: SYS_PLTRST_N */
465	/*D4*/		"",
466	/*D5*/		"",
467	/*D6*/		"",
468	/*D7*/		"",
469	/*E0*/		"power-button", /* in: BMC_PWBTN_IN_N */
470	/*E1*/		"power-chassis-control", /* out: BMC_PWRBTN_OUT_N */
471	/*E2*/		"reset-button", /* in: BMC_RSTBTN_IN_N */
472	/*E3*/		"reset-control", /* out: BMC_RSTBTN_OUT_N */
473	/*E4*/		"nmi-button", /* in: BMC_NMIBTN_IN_N */
474	/*E5*/		"nmi-control", /* out: BMC_NMIBTN_OUT_N */
475	/*E6*/		"",
476	/*E7*/		"led-heartbeat", /* out: BMC_HEARTBRAT_LED_N */
477	/*F0*/		"",
478	/*F1*/		"clear-cmos-control", /* out: BMC_CLR_CMOS_N */
479	/*F2*/		"",
480	/*F3*/		"",
481	/*F4*/		"led-fault", /* out: AST_HW_FAULT_N */
482	/*F5*/		"",
483	/*F6*/		"",
484	/*F7*/		"",
485	/*G0*/		"BMC_PE_SMB_EN_1_N", /* out */
486	/*G1*/		"BMC_PE_SMB_EN_2_N", /* out */
487	/*G2*/		"",
488	/*G3*/		"",
489	/*G4*/		"",
490	/*G5*/		"",
491	/*G6*/		"",
492	/*G7*/		"",
493	/*H0-H7*/	"","","","","","","","",
494	/*I0-I7*/	"","","","","","","","",
495	/*J0-J7*/	"","","","","","","","",
496	/*K0-K7*/	"","","","","","","","",
497	/*L0-L7*/	"","","","","","","","",
498	/*M0-M7*/	"","","","","","","","",
499	/*N0-N7*/	"","","","","","","","",
500	/*O0-O7*/	"","","","","","","","",
501	/*P0-P7*/	"","","","","","","","",
502	/*Q0*/		"",
503	/*Q1*/		"",
504	/*Q2*/		"",
505	/*Q3*/		"",
506	/*Q4*/		"BMC_PE_SMB_SW_BIT0", /* out */
507	/*Q5*/		"BMC_PE_SMB_SW_BIT1", /* out */
508	/*Q6*/		"",
509	/*Q7*/		"",
510	/*R0-R7*/	"","","","","","","","",
511	/*S0-S7*/	"","","","","","","","",
512	/*T0-T7*/	"","","","","","","","",
513	/*U0-U7*/	"","","","","","","","",
514	/*V0-V7*/	"","","","","","","","",
515	/*W0-W7*/	"","","","","","","","",
516	/*X0-X7*/	"","","","","","","","",
517	/*Y0-Y7*/	"","","","","","","","",
518	/*Z0-Z7*/	"","","","","","","","",
519	/*AA0*/		"",
520	/*AA1*/		"",
521	/*AA2*/		"",
522	/*AA3*/		"BMC_SMB3_PCH_IE_SML3_EN", /* out */
523	/*AA4*/		"",
524	/*AA5*/		"",
525	/*AA6*/		"",
526	/*AA7*/		"",
527	/*AB0-AB7*/	"","","","","","","","";
528};
529