1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  comedi/drivers/ni_routing/ni_route_values/ni_eseries.c
4  *  Route information for NI_ESERIES boards.
5  *
6  *  COMEDI - Linux Control and Measurement Device Interface
7  *  Copyright (C) 2016 Spencer E. Olson <olsonse@umich.edu>
8  *
9  *  This program is free software; you can redistribute it and/or modify
10  *  it under the terms of the GNU General Public License as published by
11  *  the Free Software Foundation; either version 2 of the License, or
12  *  (at your option) any later version.
13  *
14  *  This program is distributed in the hope that it will be useful,
15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *  GNU General Public License for more details.
18  */
19 
20 /*
21  * This file includes a list of all the values of various signals routes
22  * available on NI 660x hardware.  In many cases, one does not explicitly make
23  * these routes, rather one might indicate that something is used as the source
24  * of one particular trigger or another (using *_src=TRIG_EXT).
25  *
26  * The contents of this file can be generated using the tools in
27  * comedi/drivers/ni_routing/tools.  This file also contains specific notes to
28  * this family of devices.
29  *
30  * Please use those tools to help maintain the contents of this file, but be
31  * mindful to not lose the notes already made in this file, since these notes
32  * are critical to a complete undertsanding of the register values of this
33  * family.
34  */
35 
36 #include "../ni_route_values.h"
37 #include "all.h"
38 
39 /*
40  * Note that for e-series devices, the backplane TRIGGER_LINE(6) is generally
41  * not connected to RTSI(6).
42  */
43 
44 const struct family_route_values ni_eseries_route_values = {
45 	.family = "ni_eseries",
46 	.register_values = {
47 		/*
48 		 * destination = {
49 		 *              source          = register value,
50 		 *              ...
51 		 * }
52 		 */
53 		[B(NI_PFI(0))] = {
54 			[B(NI_AI_StartTrigger)]	= I(NI_PFI_OUTPUT_AI_START1),
55 		},
56 		[B(NI_PFI(1))] = {
57 			[B(NI_AI_ReferenceTrigger)]	= I(NI_PFI_OUTPUT_AI_START2),
58 		},
59 		[B(NI_PFI(2))] = {
60 			[B(NI_AI_ConvertClock)]	= I(NI_PFI_OUTPUT_AI_CONVERT),
61 		},
62 		[B(NI_PFI(3))] = {
63 			[B(NI_CtrSource(1))]	= I(NI_PFI_OUTPUT_G_SRC1),
64 		},
65 		[B(NI_PFI(4))] = {
66 			[B(NI_CtrGate(1))]	= I(NI_PFI_OUTPUT_G_GATE1),
67 		},
68 		[B(NI_PFI(5))] = {
69 			[B(NI_AO_SampleClock)]	= I(NI_PFI_OUTPUT_AO_UPDATE_N),
70 		},
71 		[B(NI_PFI(6))] = {
72 			[B(NI_AO_StartTrigger)]	= I(NI_PFI_OUTPUT_AO_START1),
73 		},
74 		[B(NI_PFI(7))] = {
75 			[B(NI_AI_SampleClock)]	= I(NI_PFI_OUTPUT_AI_START_PULSE),
76 		},
77 		[B(NI_PFI(8))] = {
78 			[B(NI_CtrSource(0))]	= I(NI_PFI_OUTPUT_G_SRC0),
79 		},
80 		[B(NI_PFI(9))] = {
81 			[B(NI_CtrGate(0))]	= I(NI_PFI_OUTPUT_G_GATE0),
82 		},
83 		[B(TRIGGER_LINE(0))] = {
84 			[B(NI_RTSI_BRD(0))]	= I(8),
85 			[B(NI_RTSI_BRD(1))]	= I(9),
86 			[B(NI_RTSI_BRD(2))]	= I(10),
87 			[B(NI_RTSI_BRD(3))]	= I(11),
88 			[B(NI_CtrSource(0))]	= I(5),
89 			[B(NI_CtrGate(0))]	= I(6),
90 			[B(NI_AI_StartTrigger)]	= I(0),
91 			[B(NI_AI_ReferenceTrigger)]	= I(1),
92 			[B(NI_AI_ConvertClock)]	= I(2),
93 			[B(NI_AO_SampleClock)]	= I(3),
94 			[B(NI_AO_StartTrigger)]	= I(4),
95 			[B(NI_RGOUT0)]	= I(7),
96 		},
97 		[B(TRIGGER_LINE(1))] = {
98 			[B(NI_RTSI_BRD(0))]	= I(8),
99 			[B(NI_RTSI_BRD(1))]	= I(9),
100 			[B(NI_RTSI_BRD(2))]	= I(10),
101 			[B(NI_RTSI_BRD(3))]	= I(11),
102 			[B(NI_CtrSource(0))]	= I(5),
103 			[B(NI_CtrGate(0))]	= I(6),
104 			[B(NI_AI_StartTrigger)]	= I(0),
105 			[B(NI_AI_ReferenceTrigger)]	= I(1),
106 			[B(NI_AI_ConvertClock)]	= I(2),
107 			[B(NI_AO_SampleClock)]	= I(3),
108 			[B(NI_AO_StartTrigger)]	= I(4),
109 			[B(NI_RGOUT0)]	= I(7),
110 		},
111 		[B(TRIGGER_LINE(2))] = {
112 			[B(NI_RTSI_BRD(0))]	= I(8),
113 			[B(NI_RTSI_BRD(1))]	= I(9),
114 			[B(NI_RTSI_BRD(2))]	= I(10),
115 			[B(NI_RTSI_BRD(3))]	= I(11),
116 			[B(NI_CtrSource(0))]	= I(5),
117 			[B(NI_CtrGate(0))]	= I(6),
118 			[B(NI_AI_StartTrigger)]	= I(0),
119 			[B(NI_AI_ReferenceTrigger)]	= I(1),
120 			[B(NI_AI_ConvertClock)]	= I(2),
121 			[B(NI_AO_SampleClock)]	= I(3),
122 			[B(NI_AO_StartTrigger)]	= I(4),
123 			[B(NI_RGOUT0)]	= I(7),
124 		},
125 		[B(TRIGGER_LINE(3))] = {
126 			[B(NI_RTSI_BRD(0))]	= I(8),
127 			[B(NI_RTSI_BRD(1))]	= I(9),
128 			[B(NI_RTSI_BRD(2))]	= I(10),
129 			[B(NI_RTSI_BRD(3))]	= I(11),
130 			[B(NI_CtrSource(0))]	= I(5),
131 			[B(NI_CtrGate(0))]	= I(6),
132 			[B(NI_AI_StartTrigger)]	= I(0),
133 			[B(NI_AI_ReferenceTrigger)]	= I(1),
134 			[B(NI_AI_ConvertClock)]	= I(2),
135 			[B(NI_AO_SampleClock)]	= I(3),
136 			[B(NI_AO_StartTrigger)]	= I(4),
137 			[B(NI_RGOUT0)]	= I(7),
138 		},
139 		[B(TRIGGER_LINE(4))] = {
140 			[B(NI_RTSI_BRD(0))]	= I(8),
141 			[B(NI_RTSI_BRD(1))]	= I(9),
142 			[B(NI_RTSI_BRD(2))]	= I(10),
143 			[B(NI_RTSI_BRD(3))]	= I(11),
144 			[B(NI_CtrSource(0))]	= I(5),
145 			[B(NI_CtrGate(0))]	= I(6),
146 			[B(NI_AI_StartTrigger)]	= I(0),
147 			[B(NI_AI_ReferenceTrigger)]	= I(1),
148 			[B(NI_AI_ConvertClock)]	= I(2),
149 			[B(NI_AO_SampleClock)]	= I(3),
150 			[B(NI_AO_StartTrigger)]	= I(4),
151 			[B(NI_RGOUT0)]	= I(7),
152 		},
153 		[B(TRIGGER_LINE(5))] = {
154 			[B(NI_RTSI_BRD(0))]	= I(8),
155 			[B(NI_RTSI_BRD(1))]	= I(9),
156 			[B(NI_RTSI_BRD(2))]	= I(10),
157 			[B(NI_RTSI_BRD(3))]	= I(11),
158 			[B(NI_CtrSource(0))]	= I(5),
159 			[B(NI_CtrGate(0))]	= I(6),
160 			[B(NI_AI_StartTrigger)]	= I(0),
161 			[B(NI_AI_ReferenceTrigger)]	= I(1),
162 			[B(NI_AI_ConvertClock)]	= I(2),
163 			[B(NI_AO_SampleClock)]	= I(3),
164 			[B(NI_AO_StartTrigger)]	= I(4),
165 			[B(NI_RGOUT0)]	= I(7),
166 		},
167 		[B(TRIGGER_LINE(6))] = {
168 			[B(NI_RTSI_BRD(0))]	= I(8),
169 			[B(NI_RTSI_BRD(1))]	= I(9),
170 			[B(NI_RTSI_BRD(2))]	= I(10),
171 			[B(NI_RTSI_BRD(3))]	= I(11),
172 			[B(NI_CtrSource(0))]	= I(5),
173 			[B(NI_CtrGate(0))]	= I(6),
174 			[B(NI_AI_StartTrigger)]	= I(0),
175 			[B(NI_AI_ReferenceTrigger)]	= I(1),
176 			[B(NI_AI_ConvertClock)]	= I(2),
177 			[B(NI_AO_SampleClock)]	= I(3),
178 			[B(NI_AO_StartTrigger)]	= I(4),
179 			[B(NI_RGOUT0)]	= I(7),
180 		},
181 		[B(TRIGGER_LINE(7))] = {
182 			[B(NI_20MHzTimebase)]	= I(NI_RTSI_OUTPUT_RTSI_OSC),
183 		},
184 		[B(NI_RTSI_BRD(0))] = {
185 			[B(TRIGGER_LINE(0))]	= I(0),
186 			[B(TRIGGER_LINE(1))]	= I(1),
187 			[B(TRIGGER_LINE(2))]	= I(2),
188 			[B(TRIGGER_LINE(3))]	= I(3),
189 			[B(TRIGGER_LINE(4))]	= I(4),
190 			[B(TRIGGER_LINE(5))]	= I(5),
191 			[B(TRIGGER_LINE(6))]	= I(6),
192 			[B(PXI_Star)]	= I(6),
193 			[B(NI_AI_STOP)]	= I(7),
194 		},
195 		[B(NI_RTSI_BRD(1))] = {
196 			[B(TRIGGER_LINE(0))]	= I(0),
197 			[B(TRIGGER_LINE(1))]	= I(1),
198 			[B(TRIGGER_LINE(2))]	= I(2),
199 			[B(TRIGGER_LINE(3))]	= I(3),
200 			[B(TRIGGER_LINE(4))]	= I(4),
201 			[B(TRIGGER_LINE(5))]	= I(5),
202 			[B(TRIGGER_LINE(6))]	= I(6),
203 			[B(PXI_Star)]	= I(6),
204 			[B(NI_AI_STOP)]	= I(7),
205 		},
206 		[B(NI_RTSI_BRD(2))] = {
207 			[B(TRIGGER_LINE(0))]	= I(0),
208 			[B(TRIGGER_LINE(1))]	= I(1),
209 			[B(TRIGGER_LINE(2))]	= I(2),
210 			[B(TRIGGER_LINE(3))]	= I(3),
211 			[B(TRIGGER_LINE(4))]	= I(4),
212 			[B(TRIGGER_LINE(5))]	= I(5),
213 			[B(TRIGGER_LINE(6))]	= I(6),
214 			[B(PXI_Star)]	= I(6),
215 			[B(NI_AI_SampleClock)]	= I(7),
216 		},
217 		[B(NI_RTSI_BRD(3))] = {
218 			[B(TRIGGER_LINE(0))]	= I(0),
219 			[B(TRIGGER_LINE(1))]	= I(1),
220 			[B(TRIGGER_LINE(2))]	= I(2),
221 			[B(TRIGGER_LINE(3))]	= I(3),
222 			[B(TRIGGER_LINE(4))]	= I(4),
223 			[B(TRIGGER_LINE(5))]	= I(5),
224 			[B(TRIGGER_LINE(6))]	= I(6),
225 			[B(PXI_Star)]	= I(6),
226 			[B(NI_AI_SampleClock)]	= I(7),
227 		},
228 		[B(NI_CtrSource(0))] = {
229 			/* These are not currently implemented in ni modules */
230 			[B(NI_PFI(0))]	= U(1),
231 			[B(NI_PFI(1))]	= U(2),
232 			[B(NI_PFI(2))]	= U(3),
233 			[B(NI_PFI(3))]	= U(4),
234 			[B(NI_PFI(4))]	= U(5),
235 			[B(NI_PFI(5))]	= U(6),
236 			[B(NI_PFI(6))]	= U(7),
237 			[B(NI_PFI(7))]	= U(8),
238 			[B(NI_PFI(8))]	= U(9),
239 			[B(NI_PFI(9))]	= U(10),
240 			[B(TRIGGER_LINE(0))]	= U(11),
241 			[B(TRIGGER_LINE(1))]	= U(12),
242 			[B(TRIGGER_LINE(2))]	= U(13),
243 			[B(TRIGGER_LINE(3))]	= U(14),
244 			[B(TRIGGER_LINE(4))]	= U(15),
245 			[B(TRIGGER_LINE(5))]	= U(16),
246 			[B(TRIGGER_LINE(6))]	= U(17),
247 			[B(NI_CtrInternalOutput(1))]	= U(19),
248 			[B(PXI_Star)]	= U(17),
249 			[B(NI_20MHzTimebase)]	= U(0),
250 			[B(NI_100kHzTimebase)]	= U(18),
251 			[B(NI_LogicLow)]	= U(31),
252 		},
253 		[B(NI_CtrSource(1))] = {
254 			/* These are not currently implemented in ni modules */
255 			[B(NI_PFI(0))]	= U(1),
256 			[B(NI_PFI(1))]	= U(2),
257 			[B(NI_PFI(2))]	= U(3),
258 			[B(NI_PFI(3))]	= U(4),
259 			[B(NI_PFI(4))]	= U(5),
260 			[B(NI_PFI(5))]	= U(6),
261 			[B(NI_PFI(6))]	= U(7),
262 			[B(NI_PFI(7))]	= U(8),
263 			[B(NI_PFI(8))]	= U(9),
264 			[B(NI_PFI(9))]	= U(10),
265 			[B(TRIGGER_LINE(0))]	= U(11),
266 			[B(TRIGGER_LINE(1))]	= U(12),
267 			[B(TRIGGER_LINE(2))]	= U(13),
268 			[B(TRIGGER_LINE(3))]	= U(14),
269 			[B(TRIGGER_LINE(4))]	= U(15),
270 			[B(TRIGGER_LINE(5))]	= U(16),
271 			[B(TRIGGER_LINE(6))]	= U(17),
272 			[B(NI_CtrInternalOutput(0))]	= U(19),
273 			[B(PXI_Star)]	= U(17),
274 			[B(NI_20MHzTimebase)]	= U(0),
275 			[B(NI_100kHzTimebase)]	= U(18),
276 			[B(NI_LogicLow)]	= U(31),
277 		},
278 		[B(NI_CtrGate(0))] = {
279 			[B(NI_PFI(0))]	= I(1),
280 			[B(NI_PFI(1))]	= I(2),
281 			[B(NI_PFI(2))]	= I(3),
282 			[B(NI_PFI(3))]	= I(4),
283 			[B(NI_PFI(4))]	= I(5),
284 			[B(NI_PFI(5))]	= I(6),
285 			[B(NI_PFI(6))]	= I(7),
286 			[B(NI_PFI(7))]	= I(8),
287 			[B(NI_PFI(8))]	= I(9),
288 			[B(NI_PFI(9))]	= I(10),
289 			[B(TRIGGER_LINE(0))]	= I(11),
290 			[B(TRIGGER_LINE(1))]	= I(12),
291 			[B(TRIGGER_LINE(2))]	= I(13),
292 			[B(TRIGGER_LINE(3))]	= I(14),
293 			[B(TRIGGER_LINE(4))]	= I(15),
294 			[B(TRIGGER_LINE(5))]	= I(16),
295 			[B(TRIGGER_LINE(6))]	= I(17),
296 			[B(NI_CtrInternalOutput(1))]	= I(20),
297 			[B(PXI_Star)]	= I(17),
298 			[B(NI_AI_StartTrigger)]	= I(21),
299 			[B(NI_AI_ReferenceTrigger)]	= I(18),
300 			[B(NI_LogicLow)]	= I(31),
301 		},
302 		[B(NI_CtrGate(1))] = {
303 			[B(NI_PFI(0))]	= I(1),
304 			[B(NI_PFI(1))]	= I(2),
305 			[B(NI_PFI(2))]	= I(3),
306 			[B(NI_PFI(3))]	= I(4),
307 			[B(NI_PFI(4))]	= I(5),
308 			[B(NI_PFI(5))]	= I(6),
309 			[B(NI_PFI(6))]	= I(7),
310 			[B(NI_PFI(7))]	= I(8),
311 			[B(NI_PFI(8))]	= I(9),
312 			[B(NI_PFI(9))]	= I(10),
313 			[B(TRIGGER_LINE(0))]	= I(11),
314 			[B(TRIGGER_LINE(1))]	= I(12),
315 			[B(TRIGGER_LINE(2))]	= I(13),
316 			[B(TRIGGER_LINE(3))]	= I(14),
317 			[B(TRIGGER_LINE(4))]	= I(15),
318 			[B(TRIGGER_LINE(5))]	= I(16),
319 			[B(TRIGGER_LINE(6))]	= I(17),
320 			[B(NI_CtrInternalOutput(0))]	= I(20),
321 			[B(PXI_Star)]	= I(17),
322 			[B(NI_AI_StartTrigger)]	= I(21),
323 			[B(NI_AI_ReferenceTrigger)]	= I(18),
324 			[B(NI_LogicLow)]	= I(31),
325 		},
326 		[B(NI_CtrOut(0))] = {
327 			[B(TRIGGER_LINE(0))]	= I(1),
328 			[B(TRIGGER_LINE(1))]	= I(2),
329 			[B(TRIGGER_LINE(2))]	= I(3),
330 			[B(TRIGGER_LINE(3))]	= I(4),
331 			[B(TRIGGER_LINE(4))]	= I(5),
332 			[B(TRIGGER_LINE(5))]	= I(6),
333 			[B(TRIGGER_LINE(6))]	= I(7),
334 			[B(NI_CtrInternalOutput(0))]	= I(0),
335 			[B(PXI_Star)]	= I(7),
336 		},
337 		[B(NI_CtrOut(1))] = {
338 			[B(NI_CtrInternalOutput(1))]	= I(0),
339 		},
340 		[B(NI_AI_SampleClock)] = {
341 			[B(NI_PFI(0))]	= I(1),
342 			[B(NI_PFI(1))]	= I(2),
343 			[B(NI_PFI(2))]	= I(3),
344 			[B(NI_PFI(3))]	= I(4),
345 			[B(NI_PFI(4))]	= I(5),
346 			[B(NI_PFI(5))]	= I(6),
347 			[B(NI_PFI(6))]	= I(7),
348 			[B(NI_PFI(7))]	= I(8),
349 			[B(NI_PFI(8))]	= I(9),
350 			[B(NI_PFI(9))]	= I(10),
351 			[B(TRIGGER_LINE(0))]	= I(11),
352 			[B(TRIGGER_LINE(1))]	= I(12),
353 			[B(TRIGGER_LINE(2))]	= I(13),
354 			[B(TRIGGER_LINE(3))]	= I(14),
355 			[B(TRIGGER_LINE(4))]	= I(15),
356 			[B(TRIGGER_LINE(5))]	= I(16),
357 			[B(TRIGGER_LINE(6))]	= I(17),
358 			[B(NI_CtrInternalOutput(0))]	= I(19),
359 			[B(PXI_Star)]	= I(17),
360 			[B(NI_AI_SampleClockTimebase)]	= I(0),
361 			[B(NI_LogicLow)]	= I(31),
362 		},
363 		[B(NI_AI_SampleClockTimebase)] = {
364 			/* These are not currently implemented in ni modules */
365 			[B(NI_PFI(0))]	= U(1),
366 			[B(NI_PFI(1))]	= U(2),
367 			[B(NI_PFI(2))]	= U(3),
368 			[B(NI_PFI(3))]	= U(4),
369 			[B(NI_PFI(4))]	= U(5),
370 			[B(NI_PFI(5))]	= U(6),
371 			[B(NI_PFI(6))]	= U(7),
372 			[B(NI_PFI(7))]	= U(8),
373 			[B(NI_PFI(8))]	= U(9),
374 			[B(NI_PFI(9))]	= U(10),
375 			[B(TRIGGER_LINE(0))]	= U(11),
376 			[B(TRIGGER_LINE(1))]	= U(12),
377 			[B(TRIGGER_LINE(2))]	= U(13),
378 			[B(TRIGGER_LINE(3))]	= U(14),
379 			[B(TRIGGER_LINE(4))]	= U(15),
380 			[B(TRIGGER_LINE(5))]	= U(16),
381 			[B(TRIGGER_LINE(6))]	= U(17),
382 			[B(PXI_Star)]	= U(17),
383 			[B(NI_20MHzTimebase)]	= U(0),
384 			[B(NI_100kHzTimebase)]	= U(19),
385 			[B(NI_LogicLow)]	= U(31),
386 		},
387 		[B(NI_AI_StartTrigger)] = {
388 			[B(NI_PFI(0))]	= I(1),
389 			[B(NI_PFI(1))]	= I(2),
390 			[B(NI_PFI(2))]	= I(3),
391 			[B(NI_PFI(3))]	= I(4),
392 			[B(NI_PFI(4))]	= I(5),
393 			[B(NI_PFI(5))]	= I(6),
394 			[B(NI_PFI(6))]	= I(7),
395 			[B(NI_PFI(7))]	= I(8),
396 			[B(NI_PFI(8))]	= I(9),
397 			[B(NI_PFI(9))]	= I(10),
398 			[B(TRIGGER_LINE(0))]	= I(11),
399 			[B(TRIGGER_LINE(1))]	= I(12),
400 			[B(TRIGGER_LINE(2))]	= I(13),
401 			[B(TRIGGER_LINE(3))]	= I(14),
402 			[B(TRIGGER_LINE(4))]	= I(15),
403 			[B(TRIGGER_LINE(5))]	= I(16),
404 			[B(TRIGGER_LINE(6))]	= I(17),
405 			[B(NI_CtrInternalOutput(0))]	= I(18),
406 			[B(PXI_Star)]	= I(17),
407 			[B(NI_LogicLow)]	= I(31),
408 		},
409 		[B(NI_AI_ReferenceTrigger)] = {
410 			/* These are not currently implemented in ni modules */
411 			[B(NI_PFI(0))]	= U(1),
412 			[B(NI_PFI(1))]	= U(2),
413 			[B(NI_PFI(2))]	= U(3),
414 			[B(NI_PFI(3))]	= U(4),
415 			[B(NI_PFI(4))]	= U(5),
416 			[B(NI_PFI(5))]	= U(6),
417 			[B(NI_PFI(6))]	= U(7),
418 			[B(NI_PFI(7))]	= U(8),
419 			[B(NI_PFI(8))]	= U(9),
420 			[B(NI_PFI(9))]	= U(10),
421 			[B(TRIGGER_LINE(0))]	= U(11),
422 			[B(TRIGGER_LINE(1))]	= U(12),
423 			[B(TRIGGER_LINE(2))]	= U(13),
424 			[B(TRIGGER_LINE(3))]	= U(14),
425 			[B(TRIGGER_LINE(4))]	= U(15),
426 			[B(TRIGGER_LINE(5))]	= U(16),
427 			[B(TRIGGER_LINE(6))]	= U(17),
428 			[B(PXI_Star)]	= U(17),
429 			[B(NI_LogicLow)]	= U(31),
430 		},
431 		[B(NI_AI_ConvertClock)] = {
432 			[B(NI_PFI(0))]	= I(1),
433 			[B(NI_PFI(1))]	= I(2),
434 			[B(NI_PFI(2))]	= I(3),
435 			[B(NI_PFI(3))]	= I(4),
436 			[B(NI_PFI(4))]	= I(5),
437 			[B(NI_PFI(5))]	= I(6),
438 			[B(NI_PFI(6))]	= I(7),
439 			[B(NI_PFI(7))]	= I(8),
440 			[B(NI_PFI(8))]	= I(9),
441 			[B(NI_PFI(9))]	= I(10),
442 			[B(TRIGGER_LINE(0))]	= I(11),
443 			[B(TRIGGER_LINE(1))]	= I(12),
444 			[B(TRIGGER_LINE(2))]	= I(13),
445 			[B(TRIGGER_LINE(3))]	= I(14),
446 			[B(TRIGGER_LINE(4))]	= I(15),
447 			[B(TRIGGER_LINE(5))]	= I(16),
448 			[B(TRIGGER_LINE(6))]	= I(17),
449 			[B(NI_CtrInternalOutput(0))]	= I(19),
450 			[B(PXI_Star)]	= I(17),
451 			[B(NI_AI_ConvertClockTimebase)]	= I(0),
452 			[B(NI_LogicLow)]	= I(31),
453 		},
454 		[B(NI_AI_ConvertClockTimebase)] = {
455 			/* These are not currently implemented in ni modules */
456 			[B(NI_AI_SampleClockTimebase)]	= U(0),
457 			[B(NI_20MHzTimebase)]	= U(1),
458 		},
459 		[B(NI_AI_PauseTrigger)] = {
460 			/* These are not currently implemented in ni modules */
461 			[B(NI_PFI(0))]	= U(1),
462 			[B(NI_PFI(1))]	= U(2),
463 			[B(NI_PFI(2))]	= U(3),
464 			[B(NI_PFI(3))]	= U(4),
465 			[B(NI_PFI(4))]	= U(5),
466 			[B(NI_PFI(5))]	= U(6),
467 			[B(NI_PFI(6))]	= U(7),
468 			[B(NI_PFI(7))]	= U(8),
469 			[B(NI_PFI(8))]	= U(9),
470 			[B(NI_PFI(9))]	= U(10),
471 			[B(TRIGGER_LINE(0))]	= U(11),
472 			[B(TRIGGER_LINE(1))]	= U(12),
473 			[B(TRIGGER_LINE(2))]	= U(13),
474 			[B(TRIGGER_LINE(3))]	= U(14),
475 			[B(TRIGGER_LINE(4))]	= U(15),
476 			[B(TRIGGER_LINE(5))]	= U(16),
477 			[B(TRIGGER_LINE(6))]	= U(17),
478 			[B(PXI_Star)]	= U(17),
479 			[B(NI_LogicLow)]	= U(31),
480 		},
481 		[B(NI_AO_SampleClock)] = {
482 			[B(NI_PFI(0))]	= I(1),
483 			[B(NI_PFI(1))]	= I(2),
484 			[B(NI_PFI(2))]	= I(3),
485 			[B(NI_PFI(3))]	= I(4),
486 			[B(NI_PFI(4))]	= I(5),
487 			[B(NI_PFI(5))]	= I(6),
488 			[B(NI_PFI(6))]	= I(7),
489 			[B(NI_PFI(7))]	= I(8),
490 			[B(NI_PFI(8))]	= I(9),
491 			[B(NI_PFI(9))]	= I(10),
492 			[B(TRIGGER_LINE(0))]	= I(11),
493 			[B(TRIGGER_LINE(1))]	= I(12),
494 			[B(TRIGGER_LINE(2))]	= I(13),
495 			[B(TRIGGER_LINE(3))]	= I(14),
496 			[B(TRIGGER_LINE(4))]	= I(15),
497 			[B(TRIGGER_LINE(5))]	= I(16),
498 			[B(TRIGGER_LINE(6))]	= I(17),
499 			[B(NI_CtrInternalOutput(1))]	= I(19),
500 			[B(PXI_Star)]	= I(17),
501 			[B(NI_AO_SampleClockTimebase)]	= I(0),
502 			[B(NI_LogicLow)]	= I(31),
503 		},
504 		[B(NI_AO_SampleClockTimebase)] = {
505 			/* These are not currently implemented in ni modules */
506 			[B(NI_PFI(0))]	= U(1),
507 			[B(NI_PFI(1))]	= U(2),
508 			[B(NI_PFI(2))]	= U(3),
509 			[B(NI_PFI(3))]	= U(4),
510 			[B(NI_PFI(4))]	= U(5),
511 			[B(NI_PFI(5))]	= U(6),
512 			[B(NI_PFI(6))]	= U(7),
513 			[B(NI_PFI(7))]	= U(8),
514 			[B(NI_PFI(8))]	= U(9),
515 			[B(NI_PFI(9))]	= U(10),
516 			[B(TRIGGER_LINE(0))]	= U(11),
517 			[B(TRIGGER_LINE(1))]	= U(12),
518 			[B(TRIGGER_LINE(2))]	= U(13),
519 			[B(TRIGGER_LINE(3))]	= U(14),
520 			[B(TRIGGER_LINE(4))]	= U(15),
521 			[B(TRIGGER_LINE(5))]	= U(16),
522 			[B(TRIGGER_LINE(6))]	= U(17),
523 			[B(PXI_Star)]	= U(17),
524 			[B(NI_20MHzTimebase)]	= U(0),
525 			[B(NI_100kHzTimebase)]	= U(19),
526 			[B(NI_LogicLow)]	= U(31),
527 		},
528 		[B(NI_AO_StartTrigger)] = {
529 			[B(NI_PFI(0))]	= I(1),
530 			[B(NI_PFI(1))]	= I(2),
531 			[B(NI_PFI(2))]	= I(3),
532 			[B(NI_PFI(3))]	= I(4),
533 			[B(NI_PFI(4))]	= I(5),
534 			[B(NI_PFI(5))]	= I(6),
535 			[B(NI_PFI(6))]	= I(7),
536 			[B(NI_PFI(7))]	= I(8),
537 			[B(NI_PFI(8))]	= I(9),
538 			[B(NI_PFI(9))]	= I(10),
539 			[B(TRIGGER_LINE(0))]	= I(11),
540 			[B(TRIGGER_LINE(1))]	= I(12),
541 			[B(TRIGGER_LINE(2))]	= I(13),
542 			[B(TRIGGER_LINE(3))]	= I(14),
543 			[B(TRIGGER_LINE(4))]	= I(15),
544 			[B(TRIGGER_LINE(5))]	= I(16),
545 			[B(TRIGGER_LINE(6))]	= I(17),
546 			[B(PXI_Star)]	= I(17),
547 			/*
548 			 * for the signal route
549 			 * (NI_AI_StartTrigger->NI_AO_StartTrigger), MHDDK says
550 			 * used register value 18 and DAQ-STC says 19.
551 			 * Hoping that the MHDDK is correct--being a "working"
552 			 * example.
553 			 */
554 			[B(NI_AI_StartTrigger)]	= I(18),
555 			[B(NI_LogicLow)]	= I(31),
556 		},
557 		[B(NI_AO_PauseTrigger)] = {
558 			/* These are not currently implemented in ni modules */
559 			[B(NI_PFI(0))]	= U(1),
560 			[B(NI_PFI(1))]	= U(2),
561 			[B(NI_PFI(2))]	= U(3),
562 			[B(NI_PFI(3))]	= U(4),
563 			[B(NI_PFI(4))]	= U(5),
564 			[B(NI_PFI(5))]	= U(6),
565 			[B(NI_PFI(6))]	= U(7),
566 			[B(NI_PFI(7))]	= U(8),
567 			[B(NI_PFI(8))]	= U(9),
568 			[B(NI_PFI(9))]	= U(10),
569 			[B(TRIGGER_LINE(0))]	= U(11),
570 			[B(TRIGGER_LINE(1))]	= U(12),
571 			[B(TRIGGER_LINE(2))]	= U(13),
572 			[B(TRIGGER_LINE(3))]	= U(14),
573 			[B(TRIGGER_LINE(4))]	= U(15),
574 			[B(TRIGGER_LINE(5))]	= U(16),
575 			[B(TRIGGER_LINE(6))]	= U(17),
576 			[B(PXI_Star)]	= U(17),
577 			[B(NI_LogicLow)]	= U(31),
578 		},
579 		[B(NI_MasterTimebase)] = {
580 			/* These are not currently implemented in ni modules */
581 			[B(TRIGGER_LINE(7))]	= U(1),
582 			[B(PXI_Star)]	= U(2),
583 			[B(PXI_Clk10)]	= U(3),
584 			[B(NI_10MHzRefClock)]	= U(0),
585 		},
586 		/*
587 		 * This symbol is not defined and nothing for this is
588 		 * implemented--just including this because data was found in
589 		 * the NI-STC for it--can't remember where.
590 		 * [B(NI_FrequencyOutTimebase)] = {
591 		 *	** These are not currently implemented in ni modules **
592 		 *	[B(NI_20MHzTimebase)]	= U(0),
593 		 *	[B(NI_100kHzTimebase)]	= U(1),
594 		 * },
595 		 */
596 		[B(NI_RGOUT0)] = {
597 			[B(NI_CtrInternalOutput(0))]	= I(0),
598 			[B(NI_CtrOut(0))]	= I(1),
599 		},
600 	},
601 };
602