1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and 4 * synchronization devices. 5 * 6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 7 */ 8 #ifndef PTP_IDTCLOCKMATRIX_H 9 #define PTP_IDTCLOCKMATRIX_H 10 11 #include <linux/ktime.h> 12 #include <linux/mfd/idt8a340_reg.h> 13 #include <linux/ptp_clock.h> 14 #include <linux/regmap.h> 15 16 #define FW_FILENAME "idtcm.bin" 17 #define MAX_TOD (4) 18 #define MAX_PLL (8) 19 #define MAX_REF_CLK (16) 20 21 #define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL) 22 23 #define TOD_MASK_ADDR (0xFFA5) 24 #define DEFAULT_TOD_MASK (0x04) 25 26 #define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8)) 27 #define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8)) 28 29 #define TOD0_PTP_PLL_ADDR (0xFFA8) 30 #define TOD1_PTP_PLL_ADDR (0xFFA9) 31 #define TOD2_PTP_PLL_ADDR (0xFFAA) 32 #define TOD3_PTP_PLL_ADDR (0xFFAB) 33 34 #define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0) 35 #define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2) 36 #define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4) 37 #define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6) 38 39 #define DEFAULT_OUTPUT_MASK_PLL0 (0x003) 40 #define DEFAULT_OUTPUT_MASK_PLL1 (0x00c) 41 #define DEFAULT_OUTPUT_MASK_PLL2 (0x030) 42 #define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0) 43 44 #define DEFAULT_TOD0_PTP_PLL (0) 45 #define DEFAULT_TOD1_PTP_PLL (1) 46 #define DEFAULT_TOD2_PTP_PLL (2) 47 #define DEFAULT_TOD3_PTP_PLL (3) 48 49 #define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000) 50 #define PHASE_PULL_IN_THRESHOLD_NS (15000) 51 #define TOD_WRITE_OVERHEAD_COUNT_MAX (2) 52 #define TOD_BYTE_COUNT (11) 53 54 #define LOCK_TIMEOUT_MS (2000) 55 #define LOCK_POLL_INTERVAL_MS (10) 56 57 #define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef) 58 59 #define IDTCM_MAX_WRITE_COUNT (512) 60 61 #define PHASE_PULL_IN_MAX_PPB (144000) 62 #define PHASE_PULL_IN_MIN_THRESHOLD_NS (2) 63 64 /* 65 * Return register address based on passed in firmware version 66 */ 67 #define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER)) 68 enum fw_version { 69 V_DEFAULT = 0, 70 V487 = 1, 71 V520 = 2, 72 }; 73 74 /* PTP PLL Mode */ 75 enum ptp_pll_mode { 76 PTP_PLL_MODE_MIN = 0, 77 PTP_PLL_MODE_WRITE_FREQUENCY = PTP_PLL_MODE_MIN, 78 PTP_PLL_MODE_WRITE_PHASE, 79 PTP_PLL_MODE_UNSUPPORTED, 80 PTP_PLL_MODE_MAX = PTP_PLL_MODE_UNSUPPORTED, 81 }; 82 83 struct idtcm; 84 85 struct idtcm_channel { 86 struct ptp_clock_info caps; 87 struct ptp_clock *ptp_clock; 88 struct idtcm *idtcm; 89 u16 dpll_phase; 90 u16 dpll_freq; 91 u16 dpll_n; 92 u16 dpll_ctrl_n; 93 u16 dpll_phase_pull_in; 94 u16 tod_read_primary; 95 u16 tod_read_secondary; 96 u16 tod_write; 97 u16 tod_n; 98 u16 hw_dpll_n; 99 u8 sync_src; 100 enum ptp_pll_mode mode; 101 int (*configure_write_frequency)(struct idtcm_channel *channel); 102 int (*configure_write_phase)(struct idtcm_channel *channel); 103 int (*do_phase_pull_in)(struct idtcm_channel *channel, 104 s32 offset_ns, u32 max_ffo_ppb); 105 s32 current_freq_scaled_ppm; 106 bool phase_pull_in; 107 u32 dco_delay; 108 /* last input trigger for extts */ 109 u8 refn; 110 u8 pll; 111 u8 tod; 112 u16 output_mask; 113 }; 114 115 struct idtcm { 116 struct idtcm_channel channel[MAX_TOD]; 117 struct device *dev; 118 u8 tod_mask; 119 char version[16]; 120 enum fw_version fw_ver; 121 /* Polls for external time stamps */ 122 u8 extts_mask; 123 bool extts_single_shot; 124 struct delayed_work extts_work; 125 /* Remember the ptp channel to report extts */ 126 struct idtcm_channel *event_channel[MAX_TOD]; 127 /* Mutex to protect operations from being interrupted */ 128 struct mutex *lock; 129 struct device *mfd; 130 struct regmap *regmap; 131 /* Overhead calculation for adjtime */ 132 u8 calculate_overhead_flag; 133 s64 tod_write_overhead_ns; 134 ktime_t start_time; 135 }; 136 137 struct idtcm_fwrc { 138 u8 hiaddr; 139 u8 loaddr; 140 u8 value; 141 u8 reserved; 142 } __packed; 143 144 #endif /* PTP_IDTCLOCKMATRIX_H */ 145