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c066e74f |
| 12-Jun-2023 |
Rahul Rameshbabu <rrameshbabu@nvidia.com> |
ptp: ptp_clockmatrix: Add .getmaxphase ptp_clock_info callback
Advertise the maximum offset the .adjphase callback is capable of supporting in nanoseconds for IDT ClockMatrix devices. Depend on ptp_
ptp: ptp_clockmatrix: Add .getmaxphase ptp_clock_info callback
Advertise the maximum offset the .adjphase callback is capable of supporting in nanoseconds for IDT ClockMatrix devices. Depend on ptp_clock_adjtime for handling out-of-range offsets. ptp_clock_adjtime returns -ERANGE instead of clamping out-of-range offsets.
Cc: Richard Cochran <richardcochran@gmail.com> Cc: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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7c7dcd66 |
| 16-May-2022 |
Min Li <min.li.xe@renesas.com> |
ptp: ptp_clockmatrix: return -EBUSY if phase pull-in is in progress
Also removes PEROUT_ENABLE_OUTPUT_MASK
Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gm
ptp: ptp_clockmatrix: return -EBUSY if phase pull-in is in progress
Also removes PEROUT_ENABLE_OUTPUT_MASK
Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Link: https://lore.kernel.org/r/1652712427-14703-2-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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bec67592 |
| 16-May-2022 |
Min Li <min.li.xe@renesas.com> |
ptp: ptp_clockmatrix: Add PTP_CLK_REQ_EXTTS support
Use TOD_READ_SECONDARY for extts to keep TOD_READ_PRIMARY for gettime and settime exclusively. Before this change, TOD_READ_PRIMARY was used for b
ptp: ptp_clockmatrix: Add PTP_CLK_REQ_EXTTS support
Use TOD_READ_SECONDARY for extts to keep TOD_READ_PRIMARY for gettime and settime exclusively. Before this change, TOD_READ_PRIMARY was used for both extts and gettime/settime, which would result in changing TOD read/write triggers between operations. Using TOD_READ_SECONDARY would make extts independent of gettime/settime operation
Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Link: https://lore.kernel.org/r/1652712427-14703-1-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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930dfa56 |
| 24-Sep-2021 |
Min Li <min.li.xe@renesas.com> |
ptp: clockmatrix: use rsmu driver to access i2c/spi bus
rsmu (Renesas Synchronization Management Unit ) driver is located in drivers/mfd and responsible for creating multiple devices including clock
ptp: clockmatrix: use rsmu driver to access i2c/spi bus
rsmu (Renesas Synchronization Management Unit ) driver is located in drivers/mfd and responsible for creating multiple devices including clockmatrix phc, which will then use the exposed regmap and mutex handle to access i2c/spi bus.
Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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da9facf1 |
| 13-Sep-2021 |
Min Li <min.li.xe@renesas.com> |
ptp: ptp_clockmatrix: Add support for pll_mode=0 and manual ref switch of WF and WP
Also correct how initialize_dco_operating_mode is called
Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off
ptp: ptp_clockmatrix: Add support for pll_mode=0 and manual ref switch of WF and WP
Also correct how initialize_dco_operating_mode is called
Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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794c3dff |
| 13-Sep-2021 |
Min Li <min.li.xe@renesas.com> |
ptp: ptp_clockmatrix: Add support for FW 5.2 (8A34005)
So far we don't need to support new 5.2 functions but different register addresses
Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by
ptp: ptp_clockmatrix: Add support for FW 5.2 (8A34005)
So far we don't need to support new 5.2 functions but different register addresses
Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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10c270cf |
| 17-Feb-2021 |
Vincent Cheng <vincent.cheng.xh@renesas.com> |
ptp: ptp_clockmatrix: Remove unused header declarations.
Removed unused header declarations.
Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@daveml
ptp: ptp_clockmatrix: Remove unused header declarations.
Removed unused header declarations.
Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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797d3186 |
| 17-Feb-2021 |
Vincent Cheng <vincent.cheng.xh@renesas.com> |
ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock.
Part of the device initialization aligns the rising edge of the output clock to the internal 1 PPS clock. If the system APLL and DPLL is not lo
ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock.
Part of the device initialization aligns the rising edge of the output clock to the internal 1 PPS clock. If the system APLL and DPLL is not locked, then the alignment will fail and there will be a fixed offset between the internal 1 PPS clock and the output clock.
After loading the device firmware, poll the system APLL and DPLL for locked state prior to initialization, timing out after 2 seconds.
Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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da948233 |
| 08-Dec-2020 |
Min Li <min.li.xe@renesas.com> |
ptp: clockmatrix: deprecate firmware older than 4.8.7
Add deprecated flag to indicate < v4.8.7. Fix idtcm_enable_tod() call correct settime().
Signed-off-by: Min Li <min.li.xe@renesas.com> Link: ht
ptp: clockmatrix: deprecate firmware older than 4.8.7
Add deprecated flag to indicate < v4.8.7. Fix idtcm_enable_tod() call correct settime().
Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.kernel.org/r/1607442117-13661-4-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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7260d1c8 |
| 08-Dec-2020 |
Min Li <min.li.xe@renesas.com> |
ptp: clockmatrix: Fix non-zero phase_adj is lost after snap
Fix non-zero phase_adj is lost after snap. Use ktime_sub to do ktime_t subtraction.
Signed-off-by: Min Li <min.li.xe@renesas.com> Link: h
ptp: clockmatrix: Fix non-zero phase_adj is lost after snap
Fix non-zero phase_adj is lost after snap. Use ktime_sub to do ktime_t subtraction.
Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.kernel.org/r/1607442117-13661-3-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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fa439059 |
| 08-Dec-2020 |
Min Li <min.li.xe@renesas.com> |
ptp: clockmatrix: remove 5 second delay before entering write phase mode
Remove write phase mode 5 second setup delay, not needed.
Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.k
ptp: clockmatrix: remove 5 second delay before entering write phase mode
Remove write phase mode 5 second setup delay, not needed.
Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.kernel.org/r/1607442117-13661-2-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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251f4fe2 |
| 08-Dec-2020 |
Min Li <min.li.xe@renesas.com> |
ptp: clockmatrix: reset device and check BOOT_STATUS
SM_RESET device only when loading full configuration and check for BOOT_STATUS. Also remove polling for write trigger done in _idtcm_settime().
ptp: clockmatrix: reset device and check BOOT_STATUS
SM_RESET device only when loading full configuration and check for BOOT_STATUS. Also remove polling for write trigger done in _idtcm_settime().
Changes since v1: -Correct warnings from strict checkpatch
Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Link: https://lore.kernel.org/r/1607442117-13661-1-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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957ff427 |
| 18-Aug-2020 |
Min Li <min.li.xe@renesas.com> |
ptp: ptp_clockmatrix: use i2c_master_send for i2c write
The old code for i2c write would break on some controllers, which fails at handling Repeated Start Condition. So we will just use i2c_master_s
ptp: ptp_clockmatrix: use i2c_master_send for i2c write
The old code for i2c write would break on some controllers, which fails at handling Repeated Start Condition. So we will just use i2c_master_send to handle write in one transanction.
Changes since v1: - Remove indentation change
Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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7ea5fda2 |
| 28-Jul-2020 |
Min Li <min.li.xe@renesas.com> |
ptp: ptp_clockmatrix: update to support 4.8.7 firmware
With 4.8.7 firmware, adjtime can change delta instead of absolute time, which greately increases snap accuracy. PPS alignment doesn't have to b
ptp: ptp_clockmatrix: update to support 4.8.7 firmware
With 4.8.7 firmware, adjtime can change delta instead of absolute time, which greately increases snap accuracy. PPS alignment doesn't have to be set for every single TOD change. Other minor changes includes: adding more debug logs, increasing snap accuracy for pre 4.8.7 firmware and supporting new tcs2bin format.
Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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425d2b1c |
| 02-May-2020 |
Vincent Cheng <vincent.cheng.xh@renesas.com> |
ptp: ptp_clockmatrix: Add adjphase() to support PHC write phase mode.
Add idtcm_adjphase() to support PHC write phase mode.
Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Acked-by: Ric
ptp: ptp_clockmatrix: Add adjphase() to support PHC write phase mode.
Add idtcm_adjphase() to support PHC write phase mode.
Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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3a6ba7dc |
| 01-Nov-2019 |
Vincent Cheng <vincent.cheng.xh@renesas.com> |
ptp: Add a ptp clock driver for IDT ClockMatrix.
The IDT ClockMatrix (TM) family includes integrated devices that provide eight PLL channels. Each PLL channel can be independently configured as a f
ptp: Add a ptp clock driver for IDT ClockMatrix.
The IDT ClockMatrix (TM) family includes integrated devices that provide eight PLL channels. Each PLL channel can be independently configured as a frequency synthesizer, jitter attenuator, digitally controlled oscillator (DCO), or a digital phase lock loop (DPLL). Typically these devices are used as timing references and clock sources for PTP applications. This patch adds support for the device.
Co-developed-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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