1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and 4 * synchronization devices. 5 * 6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 7 */ 8 #ifndef PTP_IDTCLOCKMATRIX_H 9 #define PTP_IDTCLOCKMATRIX_H 10 11 #include <linux/ktime.h> 12 13 #include "idt8a340_reg.h" 14 15 #define FW_FILENAME "idtcm.bin" 16 #define MAX_TOD (4) 17 #define MAX_PLL (8) 18 19 #define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL) 20 21 #define TOD_MASK_ADDR (0xFFA5) 22 #define DEFAULT_TOD_MASK (0x04) 23 24 #define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8)) 25 #define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8)) 26 27 #define TOD0_PTP_PLL_ADDR (0xFFA8) 28 #define TOD1_PTP_PLL_ADDR (0xFFA9) 29 #define TOD2_PTP_PLL_ADDR (0xFFAA) 30 #define TOD3_PTP_PLL_ADDR (0xFFAB) 31 32 #define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0) 33 #define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2) 34 #define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4) 35 #define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6) 36 37 #define DEFAULT_OUTPUT_MASK_PLL0 (0x003) 38 #define DEFAULT_OUTPUT_MASK_PLL1 (0x00c) 39 #define DEFAULT_OUTPUT_MASK_PLL2 (0x030) 40 #define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0) 41 42 #define DEFAULT_TOD0_PTP_PLL (0) 43 #define DEFAULT_TOD1_PTP_PLL (1) 44 #define DEFAULT_TOD2_PTP_PLL (2) 45 #define DEFAULT_TOD3_PTP_PLL (3) 46 47 #define POST_SM_RESET_DELAY_MS (3000) 48 #define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000) 49 #define PHASE_PULL_IN_THRESHOLD_NS (15000) 50 #define TOD_WRITE_OVERHEAD_COUNT_MAX (2) 51 #define TOD_BYTE_COUNT (11) 52 53 #define LOCK_TIMEOUT_MS (2000) 54 #define LOCK_POLL_INTERVAL_MS (10) 55 56 #define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef) 57 58 #define IDTCM_MAX_WRITE_COUNT (512) 59 60 #define PHASE_PULL_IN_MAX_PPB (144000) 61 #define PHASE_PULL_IN_MIN_THRESHOLD_NS (2) 62 63 /* 64 * Return register address based on passed in firmware version 65 */ 66 #define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER)) 67 68 /* PTP PLL Mode */ 69 enum ptp_pll_mode { 70 PTP_PLL_MODE_MIN = 0, 71 PTP_PLL_MODE_WRITE_FREQUENCY = PTP_PLL_MODE_MIN, 72 PTP_PLL_MODE_WRITE_PHASE, 73 PTP_PLL_MODE_UNSUPPORTED, 74 PTP_PLL_MODE_MAX = PTP_PLL_MODE_UNSUPPORTED, 75 }; 76 77 /* Values of DPLL_N.DPLL_MODE.PLL_MODE */ 78 enum pll_mode { 79 PLL_MODE_MIN = 0, 80 PLL_MODE_PLL = PLL_MODE_MIN, 81 PLL_MODE_WRITE_PHASE = 1, 82 PLL_MODE_WRITE_FREQUENCY = 2, 83 PLL_MODE_GPIO_INC_DEC = 3, 84 PLL_MODE_SYNTHESIS = 4, 85 PLL_MODE_PHASE_MEASUREMENT = 5, 86 PLL_MODE_DISABLED = 6, 87 PLL_MODE_MAX = PLL_MODE_DISABLED, 88 }; 89 90 /* Values of DPLL_CTRL_n.DPLL_MANU_REF_CFG.MANUAL_REFERENCE */ 91 enum manual_reference { 92 MANU_REF_MIN = 0, 93 MANU_REF_CLK0 = MANU_REF_MIN, 94 MANU_REF_CLK1, 95 MANU_REF_CLK2, 96 MANU_REF_CLK3, 97 MANU_REF_CLK4, 98 MANU_REF_CLK5, 99 MANU_REF_CLK6, 100 MANU_REF_CLK7, 101 MANU_REF_CLK8, 102 MANU_REF_CLK9, 103 MANU_REF_CLK10, 104 MANU_REF_CLK11, 105 MANU_REF_CLK12, 106 MANU_REF_CLK13, 107 MANU_REF_CLK14, 108 MANU_REF_CLK15, 109 MANU_REF_WRITE_PHASE, 110 MANU_REF_WRITE_FREQUENCY, 111 MANU_REF_XO_DPLL, 112 MANU_REF_MAX = MANU_REF_XO_DPLL, 113 }; 114 115 enum hw_tod_write_trig_sel { 116 HW_TOD_WR_TRIG_SEL_MIN = 0, 117 HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN, 118 HW_TOD_WR_TRIG_SEL_RESERVED = 1, 119 HW_TOD_WR_TRIG_SEL_TOD_PPS = 2, 120 HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3, 121 HW_TOD_WR_TRIG_SEL_PWM_PPS = 4, 122 HW_TOD_WR_TRIG_SEL_GPIO = 5, 123 HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6, 124 WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC, 125 }; 126 127 /* 4.8.7 only */ 128 enum scsr_tod_write_trig_sel { 129 SCSR_TOD_WR_TRIG_SEL_DISABLE = 0, 130 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1, 131 SCSR_TOD_WR_TRIG_SEL_REFCLK = 2, 132 SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3, 133 SCSR_TOD_WR_TRIG_SEL_TODPPS = 4, 134 SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5, 135 SCSR_TOD_WR_TRIG_SEL_GPIO = 6, 136 SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO, 137 }; 138 139 /* 4.8.7 only */ 140 enum scsr_tod_write_type_sel { 141 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0, 142 SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1, 143 SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2, 144 SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS, 145 }; 146 147 /* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */ 148 enum dpll_state { 149 DPLL_STATE_MIN = 0, 150 DPLL_STATE_FREERUN = DPLL_STATE_MIN, 151 DPLL_STATE_LOCKACQ = 1, 152 DPLL_STATE_LOCKREC = 2, 153 DPLL_STATE_LOCKED = 3, 154 DPLL_STATE_HOLDOVER = 4, 155 DPLL_STATE_OPEN_LOOP = 5, 156 DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP, 157 }; 158 159 enum fw_version { 160 V_DEFAULT = 0, 161 V487 = 1, 162 V520 = 2, 163 }; 164 165 struct idtcm; 166 167 struct idtcm_channel { 168 struct ptp_clock_info caps; 169 struct ptp_clock *ptp_clock; 170 struct idtcm *idtcm; 171 u16 dpll_phase; 172 u16 dpll_freq; 173 u16 dpll_n; 174 u16 dpll_ctrl_n; 175 u16 dpll_phase_pull_in; 176 u16 tod_read_primary; 177 u16 tod_write; 178 u16 tod_n; 179 u16 hw_dpll_n; 180 u8 sync_src; 181 enum ptp_pll_mode mode; 182 int (*configure_write_frequency)(struct idtcm_channel *channel); 183 int (*configure_write_phase)(struct idtcm_channel *channel); 184 int (*do_phase_pull_in)(struct idtcm_channel *channel, 185 s32 offset_ns, u32 max_ffo_ppb); 186 s32 current_freq_scaled_ppm; 187 bool phase_pull_in; 188 u8 pll; 189 u16 output_mask; 190 }; 191 192 struct idtcm { 193 struct idtcm_channel channel[MAX_TOD]; 194 struct i2c_client *client; 195 u8 page_offset; 196 u8 tod_mask; 197 char version[16]; 198 enum fw_version fw_ver; 199 200 /* Overhead calculation for adjtime */ 201 u8 calculate_overhead_flag; 202 s64 tod_write_overhead_ns; 203 ktime_t start_time; 204 205 /* Protects I2C read/modify/write registers from concurrent access */ 206 struct mutex reg_lock; 207 }; 208 209 struct idtcm_fwrc { 210 u8 hiaddr; 211 u8 loaddr; 212 u8 value; 213 u8 reserved; 214 } __packed; 215 216 #endif /* PTP_IDTCLOCKMATRIX_H */ 217