1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
4 * All rights reserved.
5 *
6 * Author: Li Yang <leoli@freescale.com>
7 * Jiang Bo <tanya.jiang@freescale.com>
8 *
9 * Description:
10 * Freescale high-speed USB SOC DR module device controller driver.
11 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
12 * The driver is previously named as mpc_udc. Based on bare board
13 * code from Dave Liu and Shlomi Gridish.
14 */
15
16 #define pr_fmt(x) "udc: " x
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/interrupt.h>
28 #include <linux/proc_fs.h>
29 #include <linux/mm.h>
30 #include <linux/moduleparam.h>
31 #include <linux/device.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/platform_device.h>
37 #include <linux/fsl_devices.h>
38 #include <linux/dmapool.h>
39
40 #include <asm/byteorder.h>
41 #include <asm/io.h>
42 #include <linux/unaligned.h>
43 #include <asm/dma.h>
44
45 #include "fsl_usb2_udc.h"
46
47 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
48 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
49 #define DRIVER_VERSION "Apr 20, 2007"
50
51 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
52
53 static const char driver_name[] = "fsl-usb2-udc";
54
55 static struct usb_dr_device __iomem *dr_regs;
56
57 static struct usb_sys_interface __iomem *usb_sys_regs;
58
59 /* it is initialized in probe() */
60 static struct fsl_udc *udc_controller = NULL;
61
62 static const struct usb_endpoint_descriptor
63 fsl_ep0_desc = {
64 .bLength = USB_DT_ENDPOINT_SIZE,
65 .bDescriptorType = USB_DT_ENDPOINT,
66 .bEndpointAddress = 0,
67 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
68 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
69 };
70
71 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
72
73 #ifdef CONFIG_PPC32
74 /*
75 * On some SoCs, the USB controller registers can be big or little endian,
76 * depending on the version of the chip. In order to be able to run the
77 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
78 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
79 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
80 * call through those pointers. Platform code for SoCs that have BE USB
81 * registers should set pdata->big_endian_mmio flag.
82 *
83 * This also applies to controller-to-cpu accessors for the USB descriptors,
84 * since their endianness is also SoC dependant. Platform code for SoCs that
85 * have BE USB descriptors should set pdata->big_endian_desc flag.
86 */
_fsl_readl_be(const unsigned __iomem * p)87 static u32 _fsl_readl_be(const unsigned __iomem *p)
88 {
89 return in_be32(p);
90 }
91
_fsl_readl_le(const unsigned __iomem * p)92 static u32 _fsl_readl_le(const unsigned __iomem *p)
93 {
94 return in_le32(p);
95 }
96
_fsl_writel_be(u32 v,unsigned __iomem * p)97 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
98 {
99 out_be32(p, v);
100 }
101
_fsl_writel_le(u32 v,unsigned __iomem * p)102 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
103 {
104 out_le32(p, v);
105 }
106
107 static u32 (*_fsl_readl)(const unsigned __iomem *p);
108 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
109
110 #define fsl_readl(p) (*_fsl_readl)((p))
111 #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
112
fsl_set_accessors(struct fsl_usb2_platform_data * pdata)113 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
114 {
115 if (pdata->big_endian_mmio) {
116 _fsl_readl = _fsl_readl_be;
117 _fsl_writel = _fsl_writel_be;
118 } else {
119 _fsl_readl = _fsl_readl_le;
120 _fsl_writel = _fsl_writel_le;
121 }
122 }
123
cpu_to_hc32(const u32 x)124 static inline u32 cpu_to_hc32(const u32 x)
125 {
126 return udc_controller->pdata->big_endian_desc
127 ? (__force u32)cpu_to_be32(x)
128 : (__force u32)cpu_to_le32(x);
129 }
130
hc32_to_cpu(const u32 x)131 static inline u32 hc32_to_cpu(const u32 x)
132 {
133 return udc_controller->pdata->big_endian_desc
134 ? be32_to_cpu((__force __be32)x)
135 : le32_to_cpu((__force __le32)x);
136 }
137 #else /* !CONFIG_PPC32 */
fsl_set_accessors(struct fsl_usb2_platform_data * pdata)138 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
139
140 #define fsl_readl(addr) readl(addr)
141 #define fsl_writel(val32, addr) writel(val32, addr)
142 #define cpu_to_hc32(x) cpu_to_le32(x)
143 #define hc32_to_cpu(x) le32_to_cpu(x)
144 #endif /* CONFIG_PPC32 */
145
146 /********************************************************************
147 * Internal Used Function
148 ********************************************************************/
149 /*-----------------------------------------------------------------
150 * done() - retire a request; caller blocked irqs
151 * @status : request status to be set, only works when
152 * request is still in progress.
153 *--------------------------------------------------------------*/
done(struct fsl_ep * ep,struct fsl_req * req,int status)154 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
155 __releases(ep->udc->lock)
156 __acquires(ep->udc->lock)
157 {
158 struct fsl_udc *udc = NULL;
159 unsigned char stopped = ep->stopped;
160 struct ep_td_struct *curr_td, *next_td;
161 int j;
162
163 udc = (struct fsl_udc *)ep->udc;
164 /* Removed the req from fsl_ep->queue */
165 list_del_init(&req->queue);
166
167 /* req.status should be set as -EINPROGRESS in ep_queue() */
168 if (req->req.status == -EINPROGRESS)
169 req->req.status = status;
170 else
171 status = req->req.status;
172
173 /* Free dtd for the request */
174 next_td = req->head;
175 for (j = 0; j < req->dtd_count; j++) {
176 curr_td = next_td;
177 if (j != req->dtd_count - 1) {
178 next_td = curr_td->next_td_virt;
179 }
180 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
181 }
182
183 usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
184
185 if (status && (status != -ESHUTDOWN))
186 dev_vdbg(&udc->gadget.dev, "complete %s req %p stat %d len %u/%u\n",
187 ep->ep.name, &req->req, status,
188 req->req.actual, req->req.length);
189
190 ep->stopped = 1;
191
192 spin_unlock(&ep->udc->lock);
193
194 usb_gadget_giveback_request(&ep->ep, &req->req);
195
196 spin_lock(&ep->udc->lock);
197 ep->stopped = stopped;
198 }
199
200 /*-----------------------------------------------------------------
201 * nuke(): delete all requests related to this ep
202 * called with spinlock held
203 *--------------------------------------------------------------*/
nuke(struct fsl_ep * ep,int status)204 static void nuke(struct fsl_ep *ep, int status)
205 {
206 ep->stopped = 1;
207
208 /* Flush fifo */
209 fsl_ep_fifo_flush(&ep->ep);
210
211 /* Whether this eq has request linked */
212 while (!list_empty(&ep->queue)) {
213 struct fsl_req *req = NULL;
214
215 req = list_entry(ep->queue.next, struct fsl_req, queue);
216 done(ep, req, status);
217 }
218 }
219
220 /*------------------------------------------------------------------
221 Internal Hardware related function
222 ------------------------------------------------------------------*/
223
dr_controller_setup(struct fsl_udc * udc)224 static int dr_controller_setup(struct fsl_udc *udc)
225 {
226 unsigned int tmp, portctrl, ep_num;
227 unsigned int max_no_of_ep;
228 unsigned int ctrl;
229 unsigned long timeout;
230
231 #define FSL_UDC_RESET_TIMEOUT 1000
232
233 /* Config PHY interface */
234 portctrl = fsl_readl(&dr_regs->portsc1);
235 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
236 switch (udc->phy_mode) {
237 case FSL_USB2_PHY_ULPI:
238 if (udc->pdata->have_sysif_regs) {
239 if (udc->pdata->controller_ver) {
240 /* controller version 1.6 or above */
241 ctrl = __raw_readl(&usb_sys_regs->control);
242 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
243 ctrl |= USB_CTRL_USB_EN;
244 __raw_writel(ctrl, &usb_sys_regs->control);
245 }
246 }
247 portctrl |= PORTSCX_PTS_ULPI;
248 break;
249 case FSL_USB2_PHY_UTMI_WIDE:
250 portctrl |= PORTSCX_PTW_16BIT;
251 fallthrough;
252 case FSL_USB2_PHY_UTMI:
253 case FSL_USB2_PHY_UTMI_DUAL:
254 if (udc->pdata->have_sysif_regs) {
255 if (udc->pdata->controller_ver) {
256 /* controller version 1.6 or above */
257 ctrl = __raw_readl(&usb_sys_regs->control);
258 ctrl |= (USB_CTRL_UTMI_PHY_EN |
259 USB_CTRL_USB_EN);
260 __raw_writel(ctrl, &usb_sys_regs->control);
261 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
262 PHY CLK to become stable - 10ms*/
263 }
264 }
265 portctrl |= PORTSCX_PTS_UTMI;
266 break;
267 case FSL_USB2_PHY_SERIAL:
268 portctrl |= PORTSCX_PTS_FSLS;
269 break;
270 default:
271 return -EINVAL;
272 }
273 fsl_writel(portctrl, &dr_regs->portsc1);
274
275 /* Stop and reset the usb controller */
276 tmp = fsl_readl(&dr_regs->usbcmd);
277 tmp &= ~USB_CMD_RUN_STOP;
278 fsl_writel(tmp, &dr_regs->usbcmd);
279
280 tmp = fsl_readl(&dr_regs->usbcmd);
281 tmp |= USB_CMD_CTRL_RESET;
282 fsl_writel(tmp, &dr_regs->usbcmd);
283
284 /* Wait for reset to complete */
285 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
286 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
287 if (time_after(jiffies, timeout)) {
288 dev_err(&udc->gadget.dev, "udc reset timeout!\n");
289 return -ETIMEDOUT;
290 }
291 cpu_relax();
292 }
293
294 /* Set the controller as device mode */
295 tmp = fsl_readl(&dr_regs->usbmode);
296 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
297 tmp |= USB_MODE_CTRL_MODE_DEVICE;
298 /* Disable Setup Lockout */
299 tmp |= USB_MODE_SETUP_LOCK_OFF;
300 if (udc->pdata->es)
301 tmp |= USB_MODE_ES;
302 fsl_writel(tmp, &dr_regs->usbmode);
303
304 /* Clear the setup status */
305 fsl_writel(0, &dr_regs->usbsts);
306
307 tmp = udc->ep_qh_dma;
308 tmp &= USB_EP_LIST_ADDRESS_MASK;
309 fsl_writel(tmp, &dr_regs->endpointlistaddr);
310
311 dev_vdbg(&udc->gadget.dev,
312 "vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x\n",
313 udc->ep_qh, (int)tmp,
314 fsl_readl(&dr_regs->endpointlistaddr));
315
316 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
317 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
318 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
319 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
320 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
321 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
322 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
323 }
324 /* Config control enable i/o output, cpu endian register */
325 if (udc->pdata->have_sysif_regs) {
326 ctrl = __raw_readl(&usb_sys_regs->control);
327 ctrl |= USB_CTRL_IOENB;
328 __raw_writel(ctrl, &usb_sys_regs->control);
329 }
330
331 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
332 /* Turn on cache snooping hardware, since some PowerPC platforms
333 * wholly rely on hardware to deal with cache coherent. */
334
335 if (udc->pdata->have_sysif_regs) {
336 /* Setup Snooping for all the 4GB space */
337 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
338 __raw_writel(tmp, &usb_sys_regs->snoop1);
339 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
340 __raw_writel(tmp, &usb_sys_regs->snoop2);
341 }
342 #endif
343
344 return 0;
345 }
346
347 /* Enable DR irq and set controller to run state */
dr_controller_run(struct fsl_udc * udc)348 static void dr_controller_run(struct fsl_udc *udc)
349 {
350 u32 temp;
351
352 /* Enable DR irq reg */
353 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
354 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
355 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
356
357 fsl_writel(temp, &dr_regs->usbintr);
358
359 /* Clear stopped bit */
360 udc->stopped = 0;
361
362 /* Set the controller as device mode */
363 temp = fsl_readl(&dr_regs->usbmode);
364 temp |= USB_MODE_CTRL_MODE_DEVICE;
365 fsl_writel(temp, &dr_regs->usbmode);
366
367 /* Set controller to Run */
368 temp = fsl_readl(&dr_regs->usbcmd);
369 temp |= USB_CMD_RUN_STOP;
370 fsl_writel(temp, &dr_regs->usbcmd);
371 }
372
dr_controller_stop(struct fsl_udc * udc)373 static void dr_controller_stop(struct fsl_udc *udc)
374 {
375 unsigned int tmp;
376
377 pr_debug("%s\n", __func__);
378
379 /* if we're in OTG mode, and the Host is currently using the port,
380 * stop now and don't rip the controller out from under the
381 * ehci driver
382 */
383 if (udc->gadget.is_otg) {
384 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
385 pr_debug("udc: Leaving early\n");
386 return;
387 }
388 }
389
390 /* disable all INTR */
391 fsl_writel(0, &dr_regs->usbintr);
392
393 /* Set stopped bit for isr */
394 udc->stopped = 1;
395
396 /* disable IO output */
397 /* usb_sys_regs->control = 0; */
398
399 /* set controller to Stop */
400 tmp = fsl_readl(&dr_regs->usbcmd);
401 tmp &= ~USB_CMD_RUN_STOP;
402 fsl_writel(tmp, &dr_regs->usbcmd);
403 }
404
dr_ep_setup(unsigned char ep_num,unsigned char dir,unsigned char ep_type)405 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
406 unsigned char ep_type)
407 {
408 unsigned int tmp_epctrl = 0;
409
410 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
411 if (dir) {
412 if (ep_num)
413 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
414 tmp_epctrl |= EPCTRL_TX_ENABLE;
415 tmp_epctrl &= ~EPCTRL_TX_TYPE;
416 tmp_epctrl |= ((unsigned int)(ep_type)
417 << EPCTRL_TX_EP_TYPE_SHIFT);
418 } else {
419 if (ep_num)
420 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
421 tmp_epctrl |= EPCTRL_RX_ENABLE;
422 tmp_epctrl &= ~EPCTRL_RX_TYPE;
423 tmp_epctrl |= ((unsigned int)(ep_type)
424 << EPCTRL_RX_EP_TYPE_SHIFT);
425 }
426
427 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
428 }
429
430 static void
dr_ep_change_stall(unsigned char ep_num,unsigned char dir,int value)431 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
432 {
433 u32 tmp_epctrl = 0;
434
435 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
436
437 if (value) {
438 /* set the stall bit */
439 if (dir)
440 tmp_epctrl |= EPCTRL_TX_EP_STALL;
441 else
442 tmp_epctrl |= EPCTRL_RX_EP_STALL;
443 } else {
444 /* clear the stall bit and reset data toggle */
445 if (dir) {
446 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
447 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
448 } else {
449 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
450 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
451 }
452 }
453 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
454 }
455
456 /* Get stall status of a specific ep
457 Return: 0: not stalled; 1:stalled */
dr_ep_get_stall(unsigned char ep_num,unsigned char dir)458 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
459 {
460 u32 epctrl;
461
462 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
463 if (dir)
464 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
465 else
466 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
467 }
468
469 /********************************************************************
470 Internal Structure Build up functions
471 ********************************************************************/
472
473 /*------------------------------------------------------------------
474 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
475 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
476 * @mult: Mult field
477 ------------------------------------------------------------------*/
struct_ep_qh_setup(struct fsl_udc * udc,unsigned char ep_num,unsigned char dir,unsigned char ep_type,unsigned int max_pkt_len,unsigned int zlt,unsigned char mult)478 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
479 unsigned char dir, unsigned char ep_type,
480 unsigned int max_pkt_len,
481 unsigned int zlt, unsigned char mult)
482 {
483 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
484 unsigned int tmp = 0;
485
486 /* set the Endpoint Capabilites in QH */
487 switch (ep_type) {
488 case USB_ENDPOINT_XFER_CONTROL:
489 /* Interrupt On Setup (IOS). for control ep */
490 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
491 | EP_QUEUE_HEAD_IOS;
492 break;
493 case USB_ENDPOINT_XFER_ISOC:
494 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
495 | (mult << EP_QUEUE_HEAD_MULT_POS);
496 break;
497 case USB_ENDPOINT_XFER_BULK:
498 case USB_ENDPOINT_XFER_INT:
499 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
500 break;
501 default:
502 dev_vdbg(&udc->gadget.dev, "error ep type is %d\n", ep_type);
503 return;
504 }
505 if (zlt)
506 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
507
508 p_QH->max_pkt_length = cpu_to_hc32(tmp);
509 p_QH->next_dtd_ptr = 1;
510 p_QH->size_ioc_int_sts = 0;
511 }
512
513 /* Setup qh structure and ep register for ep0. */
ep0_setup(struct fsl_udc * udc)514 static void ep0_setup(struct fsl_udc *udc)
515 {
516 /* the initialization of an ep includes: fields in QH, Regs,
517 * fsl_ep struct */
518 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
519 USB_MAX_CTRL_PAYLOAD, 0, 0);
520 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
521 USB_MAX_CTRL_PAYLOAD, 0, 0);
522 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
523 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
524
525 return;
526
527 }
528
529 /***********************************************************************
530 Endpoint Management Functions
531 ***********************************************************************/
532
533 /*-------------------------------------------------------------------------
534 * when configurations are set, or when interface settings change
535 * for example the do_set_interface() in gadget layer,
536 * the driver will enable or disable the relevant endpoints
537 * ep0 doesn't use this routine. It is always enabled.
538 -------------------------------------------------------------------------*/
fsl_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)539 static int fsl_ep_enable(struct usb_ep *_ep,
540 const struct usb_endpoint_descriptor *desc)
541 {
542 struct fsl_udc *udc = NULL;
543 struct fsl_ep *ep = NULL;
544 unsigned short max = 0;
545 unsigned char mult = 0, zlt;
546 int retval = -EINVAL;
547 unsigned long flags;
548
549 ep = container_of(_ep, struct fsl_ep, ep);
550
551 /* catch various bogus parameters */
552 if (!_ep || !desc
553 || (desc->bDescriptorType != USB_DT_ENDPOINT))
554 return -EINVAL;
555
556 udc = ep->udc;
557
558 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
559 return -ESHUTDOWN;
560
561 max = usb_endpoint_maxp(desc);
562
563 /* Disable automatic zlp generation. Driver is responsible to indicate
564 * explicitly through req->req.zero. This is needed to enable multi-td
565 * request. */
566 zlt = 1;
567
568 /* Assume the max packet size from gadget is always correct */
569 switch (desc->bmAttributes & 0x03) {
570 case USB_ENDPOINT_XFER_CONTROL:
571 case USB_ENDPOINT_XFER_BULK:
572 case USB_ENDPOINT_XFER_INT:
573 /* mult = 0. Execute N Transactions as demonstrated by
574 * the USB variable length packet protocol where N is
575 * computed using the Maximum Packet Length (dQH) and
576 * the Total Bytes field (dTD) */
577 mult = 0;
578 break;
579 case USB_ENDPOINT_XFER_ISOC:
580 /* Calculate transactions needed for high bandwidth iso */
581 mult = usb_endpoint_maxp_mult(desc);
582 /* 3 transactions at most */
583 if (mult > 3)
584 goto en_done;
585 break;
586 default:
587 goto en_done;
588 }
589
590 spin_lock_irqsave(&udc->lock, flags);
591 ep->ep.maxpacket = max;
592 ep->ep.desc = desc;
593 ep->stopped = 0;
594
595 /* Controller related setup */
596 /* Init EPx Queue Head (Ep Capabilites field in QH
597 * according to max, zlt, mult) */
598 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
599 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
600 ? USB_SEND : USB_RECV),
601 (unsigned char) (desc->bmAttributes
602 & USB_ENDPOINT_XFERTYPE_MASK),
603 max, zlt, mult);
604
605 /* Init endpoint ctrl register */
606 dr_ep_setup((unsigned char) ep_index(ep),
607 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
608 ? USB_SEND : USB_RECV),
609 (unsigned char) (desc->bmAttributes
610 & USB_ENDPOINT_XFERTYPE_MASK));
611
612 spin_unlock_irqrestore(&udc->lock, flags);
613 retval = 0;
614
615 dev_vdbg(&udc->gadget.dev, "enabled %s (ep%d%s) maxpacket %d\n",
616 ep->ep.name, ep->ep.desc->bEndpointAddress & 0x0f,
617 (desc->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
618 max);
619 en_done:
620 return retval;
621 }
622
623 /*---------------------------------------------------------------------
624 * @ep : the ep being unconfigured. May not be ep0
625 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
626 *---------------------------------------------------------------------*/
fsl_ep_disable(struct usb_ep * _ep)627 static int fsl_ep_disable(struct usb_ep *_ep)
628 {
629 struct fsl_udc *udc = NULL;
630 struct fsl_ep *ep = NULL;
631 unsigned long flags;
632 u32 epctrl;
633 int ep_num;
634
635 ep = container_of(_ep, struct fsl_ep, ep);
636 if (!_ep || !ep->ep.desc) {
637 /*
638 * dev_vdbg(&udc->gadget.dev, "%s not enabled\n",
639 * _ep ? ep->ep.name : NULL);
640 */
641 return -EINVAL;
642 }
643
644 /* disable ep on controller */
645 ep_num = ep_index(ep);
646 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
647 if (ep_is_in(ep)) {
648 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
649 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
650 } else {
651 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
652 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
653 }
654 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
655
656 udc = (struct fsl_udc *)ep->udc;
657 spin_lock_irqsave(&udc->lock, flags);
658
659 /* nuke all pending requests (does flush) */
660 nuke(ep, -ESHUTDOWN);
661
662 ep->ep.desc = NULL;
663 ep->stopped = 1;
664 spin_unlock_irqrestore(&udc->lock, flags);
665
666 dev_vdbg(&udc->gadget.dev, "disabled %s OK\n", _ep->name);
667 return 0;
668 }
669
670 /*---------------------------------------------------------------------
671 * allocate a request object used by this endpoint
672 * the main operation is to insert the req->queue to the eq->queue
673 * Returns the request, or null if one could not be allocated
674 *---------------------------------------------------------------------*/
675 static struct usb_request *
fsl_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)676 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
677 {
678 struct fsl_req *req;
679
680 req = kzalloc(sizeof *req, gfp_flags);
681 if (!req)
682 return NULL;
683
684 req->req.dma = DMA_ADDR_INVALID;
685 INIT_LIST_HEAD(&req->queue);
686
687 return &req->req;
688 }
689
fsl_free_request(struct usb_ep * _ep,struct usb_request * _req)690 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
691 {
692 struct fsl_req *req = NULL;
693
694 req = container_of(_req, struct fsl_req, req);
695
696 if (_req)
697 kfree(req);
698 }
699
700 /* Actually add a dTD chain to an empty dQH and let go */
fsl_prime_ep(struct fsl_ep * ep,struct ep_td_struct * td)701 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
702 {
703 struct ep_queue_head *qh = get_qh_by_ep(ep);
704
705 /* Write dQH next pointer and terminate bit to 0 */
706 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
707 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
708
709 /* Clear active and halt bit */
710 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
711 | EP_QUEUE_HEAD_STATUS_HALT));
712
713 /* Ensure that updates to the QH will occur before priming. */
714 wmb();
715
716 /* Prime endpoint by writing correct bit to ENDPTPRIME */
717 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
718 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
719 }
720
721 /* Add dTD chain to the dQH of an EP */
fsl_queue_td(struct fsl_ep * ep,struct fsl_req * req)722 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
723 {
724 u32 temp, bitmask, tmp_stat;
725
726 /* dev_vdbg(&udc->gadget.dev, "QH addr Register 0x%8x\n", dr_regs->endpointlistaddr);
727 dev_vdbg(&udc->gadget.dev, "ep_qh[%d] addr is 0x%8x\n", i, (u32)&(ep->udc->ep_qh[i])); */
728
729 bitmask = ep_is_in(ep)
730 ? (1 << (ep_index(ep) + 16))
731 : (1 << (ep_index(ep)));
732
733 /* check if the pipe is empty */
734 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
735 /* Add td to the end */
736 struct fsl_req *lastreq;
737 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
738 lastreq->tail->next_td_ptr =
739 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
740 /* Ensure dTD's next dtd pointer to be updated */
741 wmb();
742 /* Read prime bit, if 1 goto done */
743 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
744 return;
745
746 do {
747 /* Set ATDTW bit in USBCMD */
748 temp = fsl_readl(&dr_regs->usbcmd);
749 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
750
751 /* Read correct status bit */
752 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
753
754 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
755
756 /* Write ATDTW bit to 0 */
757 temp = fsl_readl(&dr_regs->usbcmd);
758 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
759
760 if (tmp_stat)
761 return;
762 }
763
764 fsl_prime_ep(ep, req->head);
765 }
766
767 /* Fill in the dTD structure
768 * @req: request that the transfer belongs to
769 * @length: return actually data length of the dTD
770 * @dma: return dma address of the dTD
771 * @is_last: return flag if it is the last dTD of the request
772 * return: pointer to the built dTD */
fsl_build_dtd(struct fsl_req * req,unsigned * length,dma_addr_t * dma,int * is_last,gfp_t gfp_flags)773 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
774 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
775 {
776 u32 swap_temp;
777 struct ep_td_struct *dtd;
778
779 /* how big will this transfer be? */
780 *length = min(req->req.length - req->req.actual,
781 (unsigned)EP_MAX_LENGTH_TRANSFER);
782
783 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
784 if (dtd == NULL)
785 return dtd;
786
787 dtd->td_dma = *dma;
788 /* Clear reserved field */
789 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
790 swap_temp &= ~DTD_RESERVED_FIELDS;
791 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
792
793 /* Init all of buffer page pointers */
794 swap_temp = (u32) (req->req.dma + req->req.actual);
795 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
796 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
797 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
798 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
799 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
800
801 req->req.actual += *length;
802
803 /* zlp is needed if req->req.zero is set */
804 if (req->req.zero) {
805 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
806 *is_last = 1;
807 else
808 *is_last = 0;
809 } else if (req->req.length == req->req.actual)
810 *is_last = 1;
811 else
812 *is_last = 0;
813
814 if ((*is_last) == 0)
815 dev_vdbg(&udc_controller->gadget.dev, "multi-dtd request!\n");
816 /* Fill in the transfer size; set active bit */
817 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
818
819 /* Enable interrupt for the last dtd of a request */
820 if (*is_last && !req->req.no_interrupt)
821 swap_temp |= DTD_IOC;
822
823 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
824
825 mb();
826
827 dev_vdbg(&udc_controller->gadget.dev, "length = %d address= 0x%x\n", *length, (int)*dma);
828
829 return dtd;
830 }
831
832 /* Generate dtd chain for a request */
fsl_req_to_dtd(struct fsl_req * req,gfp_t gfp_flags)833 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
834 {
835 unsigned count;
836 int is_last;
837 int is_first =1;
838 struct ep_td_struct *last_dtd = NULL, *dtd;
839 dma_addr_t dma;
840
841 do {
842 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
843 if (dtd == NULL)
844 return -ENOMEM;
845
846 if (is_first) {
847 is_first = 0;
848 req->head = dtd;
849 } else {
850 last_dtd->next_td_ptr = cpu_to_hc32(dma);
851 last_dtd->next_td_virt = dtd;
852 }
853 last_dtd = dtd;
854
855 req->dtd_count++;
856 } while (!is_last);
857
858 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
859
860 req->tail = dtd;
861
862 return 0;
863 }
864
865 /* queues (submits) an I/O request to an endpoint */
866 static int
fsl_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)867 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
868 {
869 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
870 struct fsl_req *req = container_of(_req, struct fsl_req, req);
871 struct fsl_udc *udc = ep->udc;
872 unsigned long flags;
873 int ret;
874
875 /* catch various bogus parameters */
876 if (!_req || !req->req.complete || !req->req.buf
877 || !list_empty(&req->queue)) {
878 dev_vdbg(&udc->gadget.dev, "%s, bad params\n", __func__);
879 return -EINVAL;
880 }
881 if (unlikely(!ep->ep.desc)) {
882 dev_vdbg(&udc->gadget.dev, "%s, bad ep\n", __func__);
883 return -EINVAL;
884 }
885 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
886 if (req->req.length > ep->ep.maxpacket)
887 return -EMSGSIZE;
888 }
889
890 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
891 return -ESHUTDOWN;
892
893 req->ep = ep;
894
895 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
896 if (ret)
897 return ret;
898
899 req->req.status = -EINPROGRESS;
900 req->req.actual = 0;
901 req->dtd_count = 0;
902
903 /* build dtds and push them to device queue */
904 if (!fsl_req_to_dtd(req, gfp_flags)) {
905 spin_lock_irqsave(&udc->lock, flags);
906 fsl_queue_td(ep, req);
907 } else {
908 return -ENOMEM;
909 }
910
911 /* irq handler advances the queue */
912 if (req != NULL)
913 list_add_tail(&req->queue, &ep->queue);
914 spin_unlock_irqrestore(&udc->lock, flags);
915
916 return 0;
917 }
918
919 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
fsl_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)920 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
921 {
922 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
923 struct fsl_req *req = NULL;
924 struct fsl_req *iter;
925 unsigned long flags;
926 int ep_num, stopped, ret = 0;
927 u32 epctrl;
928
929 if (!_ep || !_req)
930 return -EINVAL;
931
932 spin_lock_irqsave(&ep->udc->lock, flags);
933 stopped = ep->stopped;
934
935 /* Stop the ep before we deal with the queue */
936 ep->stopped = 1;
937 ep_num = ep_index(ep);
938 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
939 if (ep_is_in(ep))
940 epctrl &= ~EPCTRL_TX_ENABLE;
941 else
942 epctrl &= ~EPCTRL_RX_ENABLE;
943 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
944
945 /* make sure it's actually queued on this endpoint */
946 list_for_each_entry(iter, &ep->queue, queue) {
947 if (&iter->req != _req)
948 continue;
949 req = iter;
950 break;
951 }
952 if (!req) {
953 ret = -EINVAL;
954 goto out;
955 }
956
957 /* The request is in progress, or completed but not dequeued */
958 if (ep->queue.next == &req->queue) {
959 _req->status = -ECONNRESET;
960 fsl_ep_fifo_flush(_ep); /* flush current transfer */
961
962 /* The request isn't the last request in this ep queue */
963 if (req->queue.next != &ep->queue) {
964 struct fsl_req *next_req;
965
966 next_req = list_entry(req->queue.next, struct fsl_req,
967 queue);
968
969 /* prime with dTD of next request */
970 fsl_prime_ep(ep, next_req->head);
971 }
972 /* The request hasn't been processed, patch up the TD chain */
973 } else {
974 struct fsl_req *prev_req;
975
976 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
977 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
978 }
979
980 done(ep, req, -ECONNRESET);
981
982 /* Enable EP */
983 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
984 if (ep_is_in(ep))
985 epctrl |= EPCTRL_TX_ENABLE;
986 else
987 epctrl |= EPCTRL_RX_ENABLE;
988 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
989 ep->stopped = stopped;
990
991 spin_unlock_irqrestore(&ep->udc->lock, flags);
992 return ret;
993 }
994
995 /*-------------------------------------------------------------------------*/
996
997 /*-----------------------------------------------------------------
998 * modify the endpoint halt feature
999 * @ep: the non-isochronous endpoint being stalled
1000 * @value: 1--set halt 0--clear halt
1001 * Returns zero, or a negative error code.
1002 *----------------------------------------------------------------*/
fsl_ep_set_halt(struct usb_ep * _ep,int value)1003 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1004 {
1005 struct fsl_ep *ep = NULL;
1006 unsigned long flags;
1007 int status = -EOPNOTSUPP; /* operation not supported */
1008 unsigned char ep_dir = 0, ep_num = 0;
1009 struct fsl_udc *udc = NULL;
1010
1011 ep = container_of(_ep, struct fsl_ep, ep);
1012 udc = ep->udc;
1013 if (!_ep || !ep->ep.desc) {
1014 status = -EINVAL;
1015 goto out;
1016 }
1017
1018 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1019 status = -EOPNOTSUPP;
1020 goto out;
1021 }
1022
1023 /* Attempt to halt IN ep will fail if any transfer requests
1024 * are still queue */
1025 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1026 status = -EAGAIN;
1027 goto out;
1028 }
1029
1030 status = 0;
1031 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1032 ep_num = (unsigned char)(ep_index(ep));
1033 spin_lock_irqsave(&ep->udc->lock, flags);
1034 dr_ep_change_stall(ep_num, ep_dir, value);
1035 spin_unlock_irqrestore(&ep->udc->lock, flags);
1036
1037 if (ep_index(ep) == 0) {
1038 udc->ep0_state = WAIT_FOR_SETUP;
1039 udc->ep0_dir = 0;
1040 }
1041 out:
1042 dev_vdbg(&udc->gadget.dev, "%s %s halt stat %d\n", ep->ep.name,
1043 value ? "set" : "clear", status);
1044
1045 return status;
1046 }
1047
fsl_ep_fifo_status(struct usb_ep * _ep)1048 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1049 {
1050 struct fsl_ep *ep;
1051 struct fsl_udc *udc;
1052 int size = 0;
1053 u32 bitmask;
1054 struct ep_queue_head *qh;
1055
1056 if (!_ep || !_ep->desc || !(_ep->desc->bEndpointAddress&0xF))
1057 return -ENODEV;
1058
1059 ep = container_of(_ep, struct fsl_ep, ep);
1060
1061 udc = (struct fsl_udc *)ep->udc;
1062
1063 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1064 return -ESHUTDOWN;
1065
1066 qh = get_qh_by_ep(ep);
1067
1068 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1069 (1 << (ep_index(ep)));
1070
1071 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1072 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1073 >> DTD_LENGTH_BIT_POS;
1074
1075 pr_debug("%s %u\n", __func__, size);
1076 return size;
1077 }
1078
fsl_ep_fifo_flush(struct usb_ep * _ep)1079 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1080 {
1081 struct fsl_ep *ep;
1082 int ep_num, ep_dir;
1083 u32 bits;
1084 unsigned long timeout;
1085 #define FSL_UDC_FLUSH_TIMEOUT 1000
1086
1087 if (!_ep) {
1088 return;
1089 } else {
1090 ep = container_of(_ep, struct fsl_ep, ep);
1091 if (!ep->ep.desc)
1092 return;
1093 }
1094 ep_num = ep_index(ep);
1095 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1096
1097 if (ep_num == 0)
1098 bits = (1 << 16) | 1;
1099 else if (ep_dir == USB_SEND)
1100 bits = 1 << (16 + ep_num);
1101 else
1102 bits = 1 << ep_num;
1103
1104 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1105 do {
1106 fsl_writel(bits, &dr_regs->endptflush);
1107
1108 /* Wait until flush complete */
1109 while (fsl_readl(&dr_regs->endptflush)) {
1110 if (time_after(jiffies, timeout)) {
1111 dev_err(&udc_controller->gadget.dev,
1112 "ep flush timeout\n");
1113 return;
1114 }
1115 cpu_relax();
1116 }
1117 /* See if we need to flush again */
1118 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1119 }
1120
1121 static const struct usb_ep_ops fsl_ep_ops = {
1122 .enable = fsl_ep_enable,
1123 .disable = fsl_ep_disable,
1124
1125 .alloc_request = fsl_alloc_request,
1126 .free_request = fsl_free_request,
1127
1128 .queue = fsl_ep_queue,
1129 .dequeue = fsl_ep_dequeue,
1130
1131 .set_halt = fsl_ep_set_halt,
1132 .fifo_status = fsl_ep_fifo_status,
1133 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1134 };
1135
1136 /*-------------------------------------------------------------------------
1137 Gadget Driver Layer Operations
1138 -------------------------------------------------------------------------*/
1139
1140 /*----------------------------------------------------------------------
1141 * Get the current frame number (from DR frame_index Reg )
1142 *----------------------------------------------------------------------*/
fsl_get_frame(struct usb_gadget * gadget)1143 static int fsl_get_frame(struct usb_gadget *gadget)
1144 {
1145 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1146 }
1147
1148 /*-----------------------------------------------------------------------
1149 * Tries to wake up the host connected to this gadget
1150 -----------------------------------------------------------------------*/
fsl_wakeup(struct usb_gadget * gadget)1151 static int fsl_wakeup(struct usb_gadget *gadget)
1152 {
1153 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1154 u32 portsc;
1155
1156 /* Remote wakeup feature not enabled by host */
1157 if (!udc->remote_wakeup)
1158 return -ENOTSUPP;
1159
1160 portsc = fsl_readl(&dr_regs->portsc1);
1161 /* not suspended? */
1162 if (!(portsc & PORTSCX_PORT_SUSPEND))
1163 return 0;
1164 /* trigger force resume */
1165 portsc |= PORTSCX_PORT_FORCE_RESUME;
1166 fsl_writel(portsc, &dr_regs->portsc1);
1167 return 0;
1168 }
1169
can_pullup(struct fsl_udc * udc)1170 static int can_pullup(struct fsl_udc *udc)
1171 {
1172 return udc->driver && udc->softconnect && udc->vbus_active;
1173 }
1174
1175 /* Notify controller that VBUS is powered, Called by whatever
1176 detects VBUS sessions */
fsl_vbus_session(struct usb_gadget * gadget,int is_active)1177 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1178 {
1179 struct fsl_udc *udc;
1180 unsigned long flags;
1181
1182 udc = container_of(gadget, struct fsl_udc, gadget);
1183 spin_lock_irqsave(&udc->lock, flags);
1184 dev_vdbg(&gadget->dev, "VBUS %s\n", is_active ? "on" : "off");
1185 udc->vbus_active = (is_active != 0);
1186 if (can_pullup(udc))
1187 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1188 &dr_regs->usbcmd);
1189 else
1190 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1191 &dr_regs->usbcmd);
1192 spin_unlock_irqrestore(&udc->lock, flags);
1193 return 0;
1194 }
1195
1196 /* constrain controller's VBUS power usage
1197 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1198 * reporting how much power the device may consume. For example, this
1199 * could affect how quickly batteries are recharged.
1200 *
1201 * Returns zero on success, else negative errno.
1202 */
fsl_vbus_draw(struct usb_gadget * gadget,unsigned mA)1203 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1204 {
1205 struct fsl_udc *udc;
1206
1207 udc = container_of(gadget, struct fsl_udc, gadget);
1208 if (!IS_ERR_OR_NULL(udc->transceiver))
1209 return usb_phy_set_power(udc->transceiver, mA);
1210 return -ENOTSUPP;
1211 }
1212
1213 /* Change Data+ pullup status
1214 * this func is used by usb_gadget_connect/disconnect
1215 */
fsl_pullup(struct usb_gadget * gadget,int is_on)1216 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1217 {
1218 struct fsl_udc *udc;
1219
1220 udc = container_of(gadget, struct fsl_udc, gadget);
1221
1222 if (!udc->vbus_active)
1223 return -EOPNOTSUPP;
1224
1225 udc->softconnect = (is_on != 0);
1226 if (can_pullup(udc))
1227 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1228 &dr_regs->usbcmd);
1229 else
1230 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1231 &dr_regs->usbcmd);
1232
1233 return 0;
1234 }
1235
1236 static int fsl_udc_start(struct usb_gadget *g,
1237 struct usb_gadget_driver *driver);
1238 static int fsl_udc_stop(struct usb_gadget *g);
1239
1240 static const struct usb_gadget_ops fsl_gadget_ops = {
1241 .get_frame = fsl_get_frame,
1242 .wakeup = fsl_wakeup,
1243 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1244 .vbus_session = fsl_vbus_session,
1245 .vbus_draw = fsl_vbus_draw,
1246 .pullup = fsl_pullup,
1247 .udc_start = fsl_udc_start,
1248 .udc_stop = fsl_udc_stop,
1249 };
1250
1251 /*
1252 * Empty complete function used by this driver to fill in the req->complete
1253 * field when creating a request since the complete field is mandatory.
1254 */
fsl_noop_complete(struct usb_ep * ep,struct usb_request * req)1255 static void fsl_noop_complete(struct usb_ep *ep, struct usb_request *req) { }
1256
1257 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1258 on new transaction */
ep0stall(struct fsl_udc * udc)1259 static void ep0stall(struct fsl_udc *udc)
1260 {
1261 u32 tmp;
1262
1263 /* must set tx and rx to stall at the same time */
1264 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1265 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1266 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1267 udc->ep0_state = WAIT_FOR_SETUP;
1268 udc->ep0_dir = 0;
1269 }
1270
1271 /* Prime a status phase for ep0 */
ep0_prime_status(struct fsl_udc * udc,int direction)1272 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1273 {
1274 struct fsl_req *req = udc->status_req;
1275 struct fsl_ep *ep;
1276 int ret;
1277
1278 if (direction == EP_DIR_IN)
1279 udc->ep0_dir = USB_DIR_IN;
1280 else
1281 udc->ep0_dir = USB_DIR_OUT;
1282
1283 ep = &udc->eps[0];
1284 if (udc->ep0_state != DATA_STATE_XMIT)
1285 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1286
1287 req->ep = ep;
1288 req->req.length = 0;
1289 req->req.status = -EINPROGRESS;
1290 req->req.actual = 0;
1291 req->req.complete = fsl_noop_complete;
1292 req->dtd_count = 0;
1293
1294 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1295 if (ret)
1296 return ret;
1297
1298 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1299 fsl_queue_td(ep, req);
1300 else
1301 return -ENOMEM;
1302
1303 list_add_tail(&req->queue, &ep->queue);
1304
1305 return 0;
1306 }
1307
udc_reset_ep_queue(struct fsl_udc * udc,u8 pipe)1308 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1309 {
1310 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1311
1312 if (ep->ep.name)
1313 nuke(ep, -ESHUTDOWN);
1314 }
1315
1316 /*
1317 * ch9 Set address
1318 */
ch9setaddress(struct fsl_udc * udc,u16 value,u16 index,u16 length)1319 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1320 {
1321 /* Save the new address to device struct */
1322 udc->device_address = (u8) value;
1323 /* Update usb state */
1324 udc->usb_state = USB_STATE_ADDRESS;
1325 /* Status phase */
1326 if (ep0_prime_status(udc, EP_DIR_IN))
1327 ep0stall(udc);
1328 }
1329
1330 /*
1331 * ch9 Get status
1332 */
ch9getstatus(struct fsl_udc * udc,u8 request_type,u16 value,u16 index,u16 length)1333 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1334 u16 index, u16 length)
1335 {
1336 u16 tmp = 0; /* Status, cpu endian */
1337 struct fsl_req *req;
1338 struct fsl_ep *ep;
1339 int ret;
1340
1341 ep = &udc->eps[0];
1342
1343 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1344 /* Get device status */
1345 tmp = udc->gadget.is_selfpowered;
1346 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1347 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1348 /* Get interface status */
1349 /* We don't have interface information in udc driver */
1350 tmp = 0;
1351 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1352 /* Get endpoint status */
1353 struct fsl_ep *target_ep;
1354
1355 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1356
1357 /* stall if endpoint doesn't exist */
1358 if (!target_ep->ep.desc)
1359 goto stall;
1360 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1361 << USB_ENDPOINT_HALT;
1362 }
1363
1364 udc->ep0_dir = USB_DIR_IN;
1365 /* Borrow the per device status_req */
1366 req = udc->status_req;
1367 /* Fill in the request structure */
1368 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1369
1370 req->ep = ep;
1371 req->req.length = 2;
1372 req->req.status = -EINPROGRESS;
1373 req->req.actual = 0;
1374 req->req.complete = fsl_noop_complete;
1375 req->dtd_count = 0;
1376
1377 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1378 if (ret)
1379 goto stall;
1380
1381 /* prime the data phase */
1382 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1383 fsl_queue_td(ep, req);
1384 else /* no mem */
1385 goto stall;
1386
1387 list_add_tail(&req->queue, &ep->queue);
1388 udc->ep0_state = DATA_STATE_XMIT;
1389 if (ep0_prime_status(udc, EP_DIR_OUT))
1390 ep0stall(udc);
1391
1392 return;
1393 stall:
1394 ep0stall(udc);
1395 }
1396
setup_received_irq(struct fsl_udc * udc,struct usb_ctrlrequest * setup)1397 static void setup_received_irq(struct fsl_udc *udc,
1398 struct usb_ctrlrequest *setup)
1399 __releases(udc->lock)
1400 __acquires(udc->lock)
1401 {
1402 u16 wValue = le16_to_cpu(setup->wValue);
1403 u16 wIndex = le16_to_cpu(setup->wIndex);
1404 u16 wLength = le16_to_cpu(setup->wLength);
1405
1406 udc_reset_ep_queue(udc, 0);
1407
1408 /* We process some stardard setup requests here */
1409 switch (setup->bRequest) {
1410 case USB_REQ_GET_STATUS:
1411 /* Data+Status phase from udc */
1412 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1413 != (USB_DIR_IN | USB_TYPE_STANDARD))
1414 break;
1415 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1416 return;
1417
1418 case USB_REQ_SET_ADDRESS:
1419 /* Status phase from udc */
1420 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1421 | USB_RECIP_DEVICE))
1422 break;
1423 ch9setaddress(udc, wValue, wIndex, wLength);
1424 return;
1425
1426 case USB_REQ_CLEAR_FEATURE:
1427 case USB_REQ_SET_FEATURE:
1428 /* Status phase from udc */
1429 {
1430 int rc = -EOPNOTSUPP;
1431 u16 ptc = 0;
1432
1433 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1434 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1435 int pipe = get_pipe_by_windex(wIndex);
1436 struct fsl_ep *ep;
1437
1438 if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1439 break;
1440 ep = get_ep_by_pipe(udc, pipe);
1441
1442 spin_unlock(&udc->lock);
1443 rc = fsl_ep_set_halt(&ep->ep,
1444 (setup->bRequest == USB_REQ_SET_FEATURE)
1445 ? 1 : 0);
1446 spin_lock(&udc->lock);
1447
1448 } else if ((setup->bRequestType & (USB_RECIP_MASK
1449 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1450 | USB_TYPE_STANDARD)) {
1451 /* Note: The driver has not include OTG support yet.
1452 * This will be set when OTG support is added */
1453 if (wValue == USB_DEVICE_TEST_MODE)
1454 ptc = wIndex >> 8;
1455 else if (gadget_is_otg(&udc->gadget)) {
1456 if (setup->bRequest ==
1457 USB_DEVICE_B_HNP_ENABLE)
1458 udc->gadget.b_hnp_enable = 1;
1459 else if (setup->bRequest ==
1460 USB_DEVICE_A_HNP_SUPPORT)
1461 udc->gadget.a_hnp_support = 1;
1462 else if (setup->bRequest ==
1463 USB_DEVICE_A_ALT_HNP_SUPPORT)
1464 udc->gadget.a_alt_hnp_support = 1;
1465 }
1466 rc = 0;
1467 } else
1468 break;
1469
1470 if (rc == 0) {
1471 if (ep0_prime_status(udc, EP_DIR_IN))
1472 ep0stall(udc);
1473 }
1474 if (ptc) {
1475 u32 tmp;
1476
1477 mdelay(10);
1478 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1479 fsl_writel(tmp, &dr_regs->portsc1);
1480 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1481 }
1482
1483 return;
1484 }
1485
1486 default:
1487 break;
1488 }
1489
1490 /* Requests handled by gadget */
1491 if (wLength) {
1492 /* Data phase from gadget, status phase from udc */
1493 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1494 ? USB_DIR_IN : USB_DIR_OUT;
1495 spin_unlock(&udc->lock);
1496 if (udc->driver->setup(&udc->gadget,
1497 &udc->local_setup_buff) < 0)
1498 ep0stall(udc);
1499 spin_lock(&udc->lock);
1500 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1501 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1502 /*
1503 * If the data stage is IN, send status prime immediately.
1504 * See 2.0 Spec chapter 8.5.3.3 for detail.
1505 */
1506 if (udc->ep0_state == DATA_STATE_XMIT)
1507 if (ep0_prime_status(udc, EP_DIR_OUT))
1508 ep0stall(udc);
1509
1510 } else {
1511 /* No data phase, IN status from gadget */
1512 udc->ep0_dir = USB_DIR_IN;
1513 spin_unlock(&udc->lock);
1514 if (udc->driver->setup(&udc->gadget,
1515 &udc->local_setup_buff) < 0)
1516 ep0stall(udc);
1517 spin_lock(&udc->lock);
1518 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1519 }
1520 }
1521
1522 /* Process request for Data or Status phase of ep0
1523 * prime status phase if needed */
ep0_req_complete(struct fsl_udc * udc,struct fsl_ep * ep0,struct fsl_req * req)1524 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1525 struct fsl_req *req)
1526 {
1527 if (udc->usb_state == USB_STATE_ADDRESS) {
1528 /* Set the new address */
1529 u32 new_address = (u32) udc->device_address;
1530 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1531 &dr_regs->deviceaddr);
1532 }
1533
1534 done(ep0, req, 0);
1535
1536 switch (udc->ep0_state) {
1537 case DATA_STATE_XMIT:
1538 /* already primed at setup_received_irq */
1539 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1540 break;
1541 case DATA_STATE_RECV:
1542 /* send status phase */
1543 if (ep0_prime_status(udc, EP_DIR_IN))
1544 ep0stall(udc);
1545 break;
1546 case WAIT_FOR_OUT_STATUS:
1547 udc->ep0_state = WAIT_FOR_SETUP;
1548 break;
1549 case WAIT_FOR_SETUP:
1550 dev_err(&udc->gadget.dev, "Unexpected ep0 packets\n");
1551 break;
1552 default:
1553 ep0stall(udc);
1554 break;
1555 }
1556 }
1557
1558 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1559 * being corrupted by another incoming setup packet */
tripwire_handler(struct fsl_udc * udc,u8 ep_num,u8 * buffer_ptr)1560 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1561 {
1562 u32 temp;
1563 struct ep_queue_head *qh;
1564 struct fsl_usb2_platform_data *pdata = udc->pdata;
1565
1566 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1567
1568 /* Clear bit in ENDPTSETUPSTAT */
1569 temp = fsl_readl(&dr_regs->endptsetupstat);
1570 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1571
1572 /* while a hazard exists when setup package arrives */
1573 do {
1574 /* Set Setup Tripwire */
1575 temp = fsl_readl(&dr_regs->usbcmd);
1576 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1577
1578 /* Copy the setup packet to local buffer */
1579 if (pdata->le_setup_buf) {
1580 u32 *p = (u32 *)buffer_ptr;
1581 u32 *s = (u32 *)qh->setup_buffer;
1582
1583 /* Convert little endian setup buffer to CPU endian */
1584 *p++ = le32_to_cpu(*s++);
1585 *p = le32_to_cpu(*s);
1586 } else {
1587 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1588 }
1589 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1590
1591 /* Clear Setup Tripwire */
1592 temp = fsl_readl(&dr_regs->usbcmd);
1593 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1594 }
1595
1596 /* process-ep_req(): free the completed Tds for this req */
process_ep_req(struct fsl_udc * udc,int pipe,struct fsl_req * curr_req)1597 static int process_ep_req(struct fsl_udc *udc, int pipe,
1598 struct fsl_req *curr_req)
1599 {
1600 struct ep_td_struct *curr_td;
1601 int actual, remaining_length, j, tmp;
1602 int status = 0;
1603 int errors = 0;
1604 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1605 int direction = pipe % 2;
1606
1607 curr_td = curr_req->head;
1608 actual = curr_req->req.length;
1609
1610 for (j = 0; j < curr_req->dtd_count; j++) {
1611 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1612 & DTD_PACKET_SIZE)
1613 >> DTD_LENGTH_BIT_POS;
1614 actual -= remaining_length;
1615
1616 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1617 if (errors & DTD_ERROR_MASK) {
1618 if (errors & DTD_STATUS_HALTED) {
1619 dev_err(&udc->gadget.dev, "dTD error %08x QH=%d\n", errors, pipe);
1620 /* Clear the errors and Halt condition */
1621 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1622 tmp &= ~errors;
1623 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1624 status = -EPIPE;
1625 /* FIXME: continue with next queued TD? */
1626
1627 break;
1628 }
1629 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1630 dev_vdbg(&udc->gadget.dev, "Transfer overflow\n");
1631 status = -EPROTO;
1632 break;
1633 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1634 dev_vdbg(&udc->gadget.dev, "ISO error\n");
1635 status = -EILSEQ;
1636 break;
1637 } else
1638 dev_err(&udc->gadget.dev,
1639 "Unknown error has occurred (0x%x)!\n",
1640 errors);
1641
1642 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1643 & DTD_STATUS_ACTIVE) {
1644 dev_vdbg(&udc->gadget.dev, "Request not complete\n");
1645 status = REQ_UNCOMPLETE;
1646 return status;
1647 } else if (remaining_length) {
1648 if (direction) {
1649 dev_vdbg(&udc->gadget.dev,
1650 "Transmit dTD remaining length not zero\n");
1651 status = -EPROTO;
1652 break;
1653 } else {
1654 break;
1655 }
1656 } else {
1657 dev_vdbg(&udc->gadget.dev,
1658 "dTD transmitted successful\n");
1659 }
1660
1661 if (j != curr_req->dtd_count - 1)
1662 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1663 }
1664
1665 if (status)
1666 return status;
1667
1668 curr_req->req.actual = actual;
1669
1670 return 0;
1671 }
1672
1673 /* Process a DTD completion interrupt */
dtd_complete_irq(struct fsl_udc * udc)1674 static void dtd_complete_irq(struct fsl_udc *udc)
1675 {
1676 u32 bit_pos;
1677 int i, ep_num, direction, bit_mask, status;
1678 struct fsl_ep *curr_ep;
1679 struct fsl_req *curr_req, *temp_req;
1680
1681 /* Clear the bits in the register */
1682 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1683 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1684
1685 if (!bit_pos)
1686 return;
1687
1688 for (i = 0; i < udc->max_ep; i++) {
1689 ep_num = i >> 1;
1690 direction = i % 2;
1691
1692 bit_mask = 1 << (ep_num + 16 * direction);
1693
1694 if (!(bit_pos & bit_mask))
1695 continue;
1696
1697 curr_ep = get_ep_by_pipe(udc, i);
1698
1699 /* If the ep is configured */
1700 if (!curr_ep->ep.name) {
1701 dev_warn(&udc->gadget.dev, "Invalid EP?\n");
1702 continue;
1703 }
1704
1705 /* process the req queue until an uncomplete request */
1706 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1707 queue) {
1708 status = process_ep_req(udc, i, curr_req);
1709
1710 dev_vdbg(&udc->gadget.dev,
1711 "status of process_ep_req= %d, ep = %d\n",
1712 status, ep_num);
1713 if (status == REQ_UNCOMPLETE)
1714 break;
1715 /* write back status to req */
1716 curr_req->req.status = status;
1717
1718 if (ep_num == 0) {
1719 ep0_req_complete(udc, curr_ep, curr_req);
1720 break;
1721 } else
1722 done(curr_ep, curr_req, status);
1723 }
1724 }
1725 }
1726
portscx_device_speed(u32 reg)1727 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1728 {
1729 switch (reg & PORTSCX_PORT_SPEED_MASK) {
1730 case PORTSCX_PORT_SPEED_HIGH:
1731 return USB_SPEED_HIGH;
1732 case PORTSCX_PORT_SPEED_FULL:
1733 return USB_SPEED_FULL;
1734 case PORTSCX_PORT_SPEED_LOW:
1735 return USB_SPEED_LOW;
1736 default:
1737 return USB_SPEED_UNKNOWN;
1738 }
1739 }
1740
1741 /* Process a port change interrupt */
port_change_irq(struct fsl_udc * udc)1742 static void port_change_irq(struct fsl_udc *udc)
1743 {
1744 if (udc->bus_reset)
1745 udc->bus_reset = 0;
1746
1747 /* Bus resetting is finished */
1748 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1749 /* Get the speed */
1750 udc->gadget.speed =
1751 portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1752
1753 /* Update USB state */
1754 if (!udc->resume_state)
1755 udc->usb_state = USB_STATE_DEFAULT;
1756 }
1757
1758 /* Process suspend interrupt */
suspend_irq(struct fsl_udc * udc)1759 static void suspend_irq(struct fsl_udc *udc)
1760 {
1761 udc->resume_state = udc->usb_state;
1762 udc->usb_state = USB_STATE_SUSPENDED;
1763
1764 /* report suspend to the driver, serial.c does not support this */
1765 if (udc->driver->suspend)
1766 udc->driver->suspend(&udc->gadget);
1767 }
1768
bus_resume(struct fsl_udc * udc)1769 static void bus_resume(struct fsl_udc *udc)
1770 {
1771 udc->usb_state = udc->resume_state;
1772 udc->resume_state = 0;
1773
1774 /* report resume to the driver, serial.c does not support this */
1775 if (udc->driver->resume)
1776 udc->driver->resume(&udc->gadget);
1777 }
1778
1779 /* Clear up all ep queues */
reset_queues(struct fsl_udc * udc,bool bus_reset)1780 static int reset_queues(struct fsl_udc *udc, bool bus_reset)
1781 {
1782 u8 pipe;
1783
1784 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1785 udc_reset_ep_queue(udc, pipe);
1786
1787 /* report disconnect; the driver is already quiesced */
1788 spin_unlock(&udc->lock);
1789 if (bus_reset)
1790 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1791 else
1792 udc->driver->disconnect(&udc->gadget);
1793 spin_lock(&udc->lock);
1794
1795 return 0;
1796 }
1797
1798 /* Process reset interrupt */
reset_irq(struct fsl_udc * udc)1799 static void reset_irq(struct fsl_udc *udc)
1800 {
1801 u32 temp;
1802 unsigned long timeout;
1803
1804 /* Clear the device address */
1805 temp = fsl_readl(&dr_regs->deviceaddr);
1806 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1807
1808 udc->device_address = 0;
1809
1810 /* Clear usb state */
1811 udc->resume_state = 0;
1812 udc->ep0_dir = 0;
1813 udc->ep0_state = WAIT_FOR_SETUP;
1814 udc->remote_wakeup = 0; /* default to 0 on reset */
1815 udc->gadget.b_hnp_enable = 0;
1816 udc->gadget.a_hnp_support = 0;
1817 udc->gadget.a_alt_hnp_support = 0;
1818
1819 /* Clear all the setup token semaphores */
1820 temp = fsl_readl(&dr_regs->endptsetupstat);
1821 fsl_writel(temp, &dr_regs->endptsetupstat);
1822
1823 /* Clear all the endpoint complete status bits */
1824 temp = fsl_readl(&dr_regs->endptcomplete);
1825 fsl_writel(temp, &dr_regs->endptcomplete);
1826
1827 timeout = jiffies + 100;
1828 while (fsl_readl(&dr_regs->endpointprime)) {
1829 /* Wait until all endptprime bits cleared */
1830 if (time_after(jiffies, timeout)) {
1831 dev_err(&udc->gadget.dev, "Timeout for reset\n");
1832 break;
1833 }
1834 cpu_relax();
1835 }
1836
1837 /* Write 1s to the flush register */
1838 fsl_writel(0xffffffff, &dr_regs->endptflush);
1839
1840 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1841 dev_vdbg(&udc->gadget.dev, "Bus reset\n");
1842 /* Bus is reseting */
1843 udc->bus_reset = 1;
1844 /* Reset all the queues, include XD, dTD, EP queue
1845 * head and TR Queue */
1846 reset_queues(udc, true);
1847 udc->usb_state = USB_STATE_DEFAULT;
1848 } else {
1849 dev_vdbg(&udc->gadget.dev, "Controller reset\n");
1850 /* initialize usb hw reg except for regs for EP, not
1851 * touch usbintr reg */
1852 dr_controller_setup(udc);
1853
1854 /* Reset all internal used Queues */
1855 reset_queues(udc, false);
1856
1857 ep0_setup(udc);
1858
1859 /* Enable DR IRQ reg, Set Run bit, change udc state */
1860 dr_controller_run(udc);
1861 udc->usb_state = USB_STATE_ATTACHED;
1862 }
1863 }
1864
1865 /*
1866 * USB device controller interrupt handler
1867 */
fsl_udc_irq(int irq,void * _udc)1868 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1869 {
1870 struct fsl_udc *udc = _udc;
1871 u32 irq_src;
1872 irqreturn_t status = IRQ_NONE;
1873 unsigned long flags;
1874
1875 /* Disable ISR for OTG host mode */
1876 if (udc->stopped)
1877 return IRQ_NONE;
1878 spin_lock_irqsave(&udc->lock, flags);
1879 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1880 /* Clear notification bits */
1881 fsl_writel(irq_src, &dr_regs->usbsts);
1882
1883 /* dev_vdbg(&udc->gadget.dev, "irq_src [0x%8x]", irq_src); */
1884
1885 /* Need to resume? */
1886 if (udc->usb_state == USB_STATE_SUSPENDED)
1887 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1888 bus_resume(udc);
1889
1890 /* USB Interrupt */
1891 if (irq_src & USB_STS_INT) {
1892 dev_vdbg(&udc->gadget.dev, "Packet int\n");
1893 /* Setup package, we only support ep0 as control ep */
1894 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1895 tripwire_handler(udc, 0,
1896 (u8 *) (&udc->local_setup_buff));
1897 setup_received_irq(udc, &udc->local_setup_buff);
1898 status = IRQ_HANDLED;
1899 }
1900
1901 /* completion of dtd */
1902 if (fsl_readl(&dr_regs->endptcomplete)) {
1903 dtd_complete_irq(udc);
1904 status = IRQ_HANDLED;
1905 }
1906 }
1907
1908 /* SOF (for ISO transfer) */
1909 if (irq_src & USB_STS_SOF) {
1910 status = IRQ_HANDLED;
1911 }
1912
1913 /* Port Change */
1914 if (irq_src & USB_STS_PORT_CHANGE) {
1915 port_change_irq(udc);
1916 status = IRQ_HANDLED;
1917 }
1918
1919 /* Reset Received */
1920 if (irq_src & USB_STS_RESET) {
1921 dev_vdbg(&udc->gadget.dev, "reset int\n");
1922 reset_irq(udc);
1923 status = IRQ_HANDLED;
1924 }
1925
1926 /* Sleep Enable (Suspend) */
1927 if (irq_src & USB_STS_SUSPEND) {
1928 suspend_irq(udc);
1929 status = IRQ_HANDLED;
1930 }
1931
1932 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1933 dev_vdbg(&udc->gadget.dev, "Error IRQ %x\n", irq_src);
1934 }
1935
1936 spin_unlock_irqrestore(&udc->lock, flags);
1937 return status;
1938 }
1939
1940 /*----------------------------------------------------------------*
1941 * Hook to gadget drivers
1942 * Called by initialization code of gadget drivers
1943 *----------------------------------------------------------------*/
fsl_udc_start(struct usb_gadget * g,struct usb_gadget_driver * driver)1944 static int fsl_udc_start(struct usb_gadget *g,
1945 struct usb_gadget_driver *driver)
1946 {
1947 int retval = 0;
1948 unsigned long flags;
1949
1950 /* lock is needed but whether should use this lock or another */
1951 spin_lock_irqsave(&udc_controller->lock, flags);
1952
1953 /* hook up the driver */
1954 udc_controller->driver = driver;
1955 spin_unlock_irqrestore(&udc_controller->lock, flags);
1956 g->is_selfpowered = 1;
1957
1958 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1959 /* Suspend the controller until OTG enable it */
1960 udc_controller->stopped = 1;
1961 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1962
1963 /* connect to bus through transceiver */
1964 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1965 retval = otg_set_peripheral(
1966 udc_controller->transceiver->otg,
1967 &udc_controller->gadget);
1968 if (retval < 0) {
1969 dev_err(&udc_controller->gadget.dev, "can't bind to transceiver\n");
1970 udc_controller->driver = NULL;
1971 return retval;
1972 }
1973 }
1974 } else {
1975 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1976 dr_controller_run(udc_controller);
1977 udc_controller->usb_state = USB_STATE_ATTACHED;
1978 udc_controller->ep0_state = WAIT_FOR_SETUP;
1979 udc_controller->ep0_dir = 0;
1980 }
1981
1982 return retval;
1983 }
1984
1985 /* Disconnect from gadget driver */
fsl_udc_stop(struct usb_gadget * g)1986 static int fsl_udc_stop(struct usb_gadget *g)
1987 {
1988 struct fsl_ep *loop_ep;
1989 unsigned long flags;
1990
1991 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
1992 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
1993
1994 /* stop DR, disable intr */
1995 dr_controller_stop(udc_controller);
1996
1997 /* in fact, no needed */
1998 udc_controller->usb_state = USB_STATE_ATTACHED;
1999 udc_controller->ep0_state = WAIT_FOR_SETUP;
2000 udc_controller->ep0_dir = 0;
2001
2002 /* stand operation */
2003 spin_lock_irqsave(&udc_controller->lock, flags);
2004 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2005 nuke(&udc_controller->eps[0], -ESHUTDOWN);
2006 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2007 ep.ep_list)
2008 nuke(loop_ep, -ESHUTDOWN);
2009 spin_unlock_irqrestore(&udc_controller->lock, flags);
2010
2011 udc_controller->driver = NULL;
2012
2013 return 0;
2014 }
2015
2016 /*-------------------------------------------------------------------------
2017 PROC File System Support
2018 -------------------------------------------------------------------------*/
2019 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2020
2021 #include <linux/seq_file.h>
2022
2023 static const char proc_filename[] = "driver/fsl_usb2_udc";
2024
fsl_proc_read(struct seq_file * m,void * v)2025 static int fsl_proc_read(struct seq_file *m, void *v)
2026 {
2027 unsigned long flags;
2028 int i;
2029 u32 tmp_reg;
2030 struct fsl_ep *ep = NULL;
2031 struct fsl_req *req;
2032
2033 struct fsl_udc *udc = udc_controller;
2034
2035 spin_lock_irqsave(&udc->lock, flags);
2036
2037 /* ------basic driver information ---- */
2038 seq_printf(m,
2039 DRIVER_DESC "\n"
2040 "%s version: %s\n"
2041 "Gadget driver: %s\n\n",
2042 driver_name, DRIVER_VERSION,
2043 udc->driver ? udc->driver->driver.name : "(none)");
2044
2045 /* ------ DR Registers ----- */
2046 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2047 seq_printf(m,
2048 "USBCMD reg:\n"
2049 "SetupTW: %d\n"
2050 "Run/Stop: %s\n\n",
2051 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2052 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2053
2054 tmp_reg = fsl_readl(&dr_regs->usbsts);
2055 seq_printf(m,
2056 "USB Status Reg:\n"
2057 "Dr Suspend: %d Reset Received: %d System Error: %s "
2058 "USB Error Interrupt: %s\n\n",
2059 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2060 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2061 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2062 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2063
2064 tmp_reg = fsl_readl(&dr_regs->usbintr);
2065 seq_printf(m,
2066 "USB Interrupt Enable Reg:\n"
2067 "Sleep Enable: %d SOF Received Enable: %d "
2068 "Reset Enable: %d\n"
2069 "System Error Enable: %d "
2070 "Port Change Detected Enable: %d\n"
2071 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2072 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2073 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2074 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2075 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2076 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2077 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2078 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2079
2080 tmp_reg = fsl_readl(&dr_regs->frindex);
2081 seq_printf(m,
2082 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2083 (tmp_reg & USB_FRINDEX_MASKS));
2084
2085 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2086 seq_printf(m,
2087 "USB Device Address Reg: Device Addr is 0x%x\n\n",
2088 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2089
2090 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2091 seq_printf(m,
2092 "USB Endpoint List Address Reg: "
2093 "Device Addr is 0x%x\n\n",
2094 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2095
2096 tmp_reg = fsl_readl(&dr_regs->portsc1);
2097 seq_printf(m,
2098 "USB Port Status&Control Reg:\n"
2099 "Port Transceiver Type : %s Port Speed: %s\n"
2100 "PHY Low Power Suspend: %s Port Reset: %s "
2101 "Port Suspend Mode: %s\n"
2102 "Over-current Change: %s "
2103 "Port Enable/Disable Change: %s\n"
2104 "Port Enabled/Disabled: %s "
2105 "Current Connect Status: %s\n\n", ( {
2106 const char *s;
2107 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2108 case PORTSCX_PTS_UTMI:
2109 s = "UTMI"; break;
2110 case PORTSCX_PTS_ULPI:
2111 s = "ULPI "; break;
2112 case PORTSCX_PTS_FSLS:
2113 s = "FS/LS Serial"; break;
2114 default:
2115 s = "None"; break;
2116 }
2117 s;} ),
2118 usb_speed_string(portscx_device_speed(tmp_reg)),
2119 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2120 "Normal PHY mode" : "Low power mode",
2121 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2122 "Not in Reset",
2123 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2124 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2125 "No",
2126 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2127 "Not change",
2128 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2129 "Not correct",
2130 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2131 "Attached" : "Not-Att");
2132
2133 tmp_reg = fsl_readl(&dr_regs->usbmode);
2134 seq_printf(m,
2135 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2136 const char *s;
2137 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2138 case USB_MODE_CTRL_MODE_IDLE:
2139 s = "Idle"; break;
2140 case USB_MODE_CTRL_MODE_DEVICE:
2141 s = "Device Controller"; break;
2142 case USB_MODE_CTRL_MODE_HOST:
2143 s = "Host Controller"; break;
2144 default:
2145 s = "None"; break;
2146 }
2147 s;
2148 } ));
2149
2150 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2151 seq_printf(m,
2152 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2153 (tmp_reg & EP_SETUP_STATUS_MASK));
2154
2155 for (i = 0; i < udc->max_ep / 2; i++) {
2156 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2157 seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg);
2158 }
2159 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2160 seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2161
2162 if (udc->pdata->have_sysif_regs) {
2163 tmp_reg = usb_sys_regs->snoop1;
2164 seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2165
2166 tmp_reg = usb_sys_regs->control;
2167 seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg);
2168 }
2169
2170 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2171 ep = &udc->eps[0];
2172 seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n",
2173 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2174
2175 if (list_empty(&ep->queue)) {
2176 seq_puts(m, "its req queue is empty\n\n");
2177 } else {
2178 list_for_each_entry(req, &ep->queue, queue) {
2179 seq_printf(m,
2180 "req %p actual 0x%x length 0x%x buf %p\n",
2181 &req->req, req->req.actual,
2182 req->req.length, req->req.buf);
2183 }
2184 }
2185 /* other gadget->eplist ep */
2186 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2187 if (ep->ep.desc) {
2188 seq_printf(m,
2189 "\nFor %s Maxpkt is 0x%x "
2190 "index is 0x%x\n",
2191 ep->ep.name, ep_maxpacket(ep),
2192 ep_index(ep));
2193
2194 if (list_empty(&ep->queue)) {
2195 seq_puts(m, "its req queue is empty\n\n");
2196 } else {
2197 list_for_each_entry(req, &ep->queue, queue) {
2198 seq_printf(m,
2199 "req %p actual 0x%x length "
2200 "0x%x buf %p\n",
2201 &req->req, req->req.actual,
2202 req->req.length, req->req.buf);
2203 } /* end for each_entry of ep req */
2204 } /* end for else */
2205 } /* end for if(ep->queue) */
2206 } /* end (ep->desc) */
2207
2208 spin_unlock_irqrestore(&udc->lock, flags);
2209 return 0;
2210 }
2211
2212 #define create_proc_file() \
2213 proc_create_single(proc_filename, 0, NULL, fsl_proc_read)
2214 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2215
2216 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2217
2218 #define create_proc_file() do {} while (0)
2219 #define remove_proc_file() do {} while (0)
2220
2221 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2222
2223 /*-------------------------------------------------------------------------*/
2224
2225 /* Release udc structures */
fsl_udc_release(struct device * dev)2226 static void fsl_udc_release(struct device *dev)
2227 {
2228 complete(udc_controller->done);
2229 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2230 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2231 kfree(udc_controller);
2232 }
2233
2234 /******************************************************************
2235 Internal structure setup functions
2236 *******************************************************************/
2237 /*------------------------------------------------------------------
2238 * init resource for global controller called by fsl_udc_probe()
2239 * On success the udc handle is initialized, on failure it is
2240 * unchanged (reset).
2241 * Return 0 on success and -1 on allocation failure
2242 ------------------------------------------------------------------*/
struct_udc_setup(struct fsl_udc * udc,struct platform_device * pdev)2243 static int struct_udc_setup(struct fsl_udc *udc,
2244 struct platform_device *pdev)
2245 {
2246 struct fsl_usb2_platform_data *pdata;
2247 size_t size;
2248
2249 pdata = dev_get_platdata(&pdev->dev);
2250 udc->phy_mode = pdata->phy_mode;
2251
2252 udc->eps = kcalloc(udc->max_ep, sizeof(struct fsl_ep), GFP_KERNEL);
2253 if (!udc->eps) {
2254 dev_err(&udc->gadget.dev, "kmalloc udc endpoint status failed\n");
2255 goto eps_alloc_failed;
2256 }
2257
2258 /* initialized QHs, take care of alignment */
2259 size = udc->max_ep * sizeof(struct ep_queue_head);
2260 if (size < QH_ALIGNMENT)
2261 size = QH_ALIGNMENT;
2262 else if ((size % QH_ALIGNMENT) != 0) {
2263 size += QH_ALIGNMENT + 1;
2264 size &= ~(QH_ALIGNMENT - 1);
2265 }
2266 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2267 &udc->ep_qh_dma, GFP_KERNEL);
2268 if (!udc->ep_qh) {
2269 dev_err(&udc->gadget.dev, "malloc QHs for udc failed\n");
2270 goto ep_queue_alloc_failed;
2271 }
2272
2273 udc->ep_qh_size = size;
2274
2275 /* Initialize ep0 status request structure */
2276 /* FIXME: fsl_alloc_request() ignores ep argument */
2277 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2278 struct fsl_req, req);
2279 if (!udc->status_req) {
2280 dev_err(&udc->gadget.dev, "kzalloc for udc status request failed\n");
2281 goto udc_status_alloc_failed;
2282 }
2283
2284 /* allocate a small amount of memory to get valid address */
2285 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2286 if (!udc->status_req->req.buf) {
2287 dev_err(&udc->gadget.dev, "kzalloc for udc request buffer failed\n");
2288 goto udc_req_buf_alloc_failed;
2289 }
2290
2291 udc->resume_state = USB_STATE_NOTATTACHED;
2292 udc->usb_state = USB_STATE_POWERED;
2293 udc->ep0_dir = 0;
2294 udc->remote_wakeup = 0; /* default to 0 on reset */
2295
2296 return 0;
2297
2298 udc_req_buf_alloc_failed:
2299 kfree(udc->status_req);
2300 udc_status_alloc_failed:
2301 kfree(udc->ep_qh);
2302 udc->ep_qh_size = 0;
2303 ep_queue_alloc_failed:
2304 kfree(udc->eps);
2305 eps_alloc_failed:
2306 udc->phy_mode = 0;
2307 return -1;
2308
2309 }
2310
2311 /*----------------------------------------------------------------
2312 * Setup the fsl_ep struct for eps
2313 * Link fsl_ep->ep to gadget->ep_list
2314 * ep0out is not used so do nothing here
2315 * ep0in should be taken care
2316 *--------------------------------------------------------------*/
struct_ep_setup(struct fsl_udc * udc,unsigned char index,char * name,int link)2317 static int struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2318 char *name, int link)
2319 {
2320 struct fsl_ep *ep = &udc->eps[index];
2321
2322 ep->udc = udc;
2323 strcpy(ep->name, name);
2324 ep->ep.name = ep->name;
2325
2326 ep->ep.ops = &fsl_ep_ops;
2327 ep->stopped = 0;
2328
2329 if (index == 0) {
2330 ep->ep.caps.type_control = true;
2331 } else {
2332 ep->ep.caps.type_iso = true;
2333 ep->ep.caps.type_bulk = true;
2334 ep->ep.caps.type_int = true;
2335 }
2336
2337 if (index & 1)
2338 ep->ep.caps.dir_in = true;
2339 else
2340 ep->ep.caps.dir_out = true;
2341
2342 /* for ep0: maxP defined in desc
2343 * for other eps, maxP is set by epautoconfig() called by gadget layer
2344 */
2345 usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
2346
2347 /* the queue lists any req for this ep */
2348 INIT_LIST_HEAD(&ep->queue);
2349
2350 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2351 if (link)
2352 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2353 ep->gadget = &udc->gadget;
2354 ep->qh = &udc->ep_qh[index];
2355
2356 return 0;
2357 }
2358
2359 /* Driver probe function
2360 * all initialization operations implemented here except enabling usb_intr reg
2361 * board setup should have been done in the platform code
2362 */
fsl_udc_probe(struct platform_device * pdev)2363 static int fsl_udc_probe(struct platform_device *pdev)
2364 {
2365 struct fsl_usb2_platform_data *pdata;
2366 struct resource *res;
2367 int ret = -ENODEV;
2368 unsigned int i;
2369 u32 dccparams;
2370
2371 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2372 if (udc_controller == NULL)
2373 return -ENOMEM;
2374
2375 pdata = dev_get_platdata(&pdev->dev);
2376 udc_controller->pdata = pdata;
2377 spin_lock_init(&udc_controller->lock);
2378 udc_controller->stopped = 1;
2379
2380 #ifdef CONFIG_USB_OTG
2381 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2382 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2383 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2384 dev_err(&udc_controller->gadget.dev, "Can't find OTG driver!\n");
2385 ret = -ENODEV;
2386 goto err_kfree;
2387 }
2388 }
2389 #endif
2390
2391 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2392 if (!res) {
2393 ret = -ENXIO;
2394 goto err_kfree;
2395 }
2396
2397 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2398 if (!request_mem_region(res->start, resource_size(res),
2399 driver_name)) {
2400 dev_err(&udc_controller->gadget.dev, "request mem region for %s failed\n", pdev->name);
2401 ret = -EBUSY;
2402 goto err_kfree;
2403 }
2404 }
2405
2406 dr_regs = ioremap(res->start, resource_size(res));
2407 if (!dr_regs) {
2408 ret = -ENOMEM;
2409 goto err_release_mem_region;
2410 }
2411
2412 pdata->regs = (void __iomem *)dr_regs;
2413
2414 /*
2415 * do platform specific init: check the clock, grab/config pins, etc.
2416 */
2417 if (pdata->init && pdata->init(pdev)) {
2418 ret = -ENODEV;
2419 goto err_iounmap;
2420 }
2421
2422 /* Set accessors only after pdata->init() ! */
2423 fsl_set_accessors(pdata);
2424
2425 if (pdata->have_sysif_regs)
2426 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2427
2428 /* Read Device Controller Capability Parameters register */
2429 dccparams = fsl_readl(&dr_regs->dccparams);
2430 if (!(dccparams & DCCPARAMS_DC)) {
2431 dev_err(&udc_controller->gadget.dev, "This SOC doesn't support device role\n");
2432 ret = -ENODEV;
2433 goto err_exit;
2434 }
2435 /* Get max device endpoints */
2436 /* DEN is bidirectional ep number, max_ep doubles the number */
2437 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2438
2439 ret = platform_get_irq(pdev, 0);
2440 if (ret <= 0) {
2441 ret = ret ? : -ENODEV;
2442 goto err_exit;
2443 }
2444 udc_controller->irq = ret;
2445
2446 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2447 driver_name, udc_controller);
2448 if (ret != 0) {
2449 dev_err(&udc_controller->gadget.dev, "cannot request irq %d err %d\n",
2450 udc_controller->irq, ret);
2451 goto err_exit;
2452 }
2453
2454 /* Initialize the udc structure including QH member and other member */
2455 if (struct_udc_setup(udc_controller, pdev)) {
2456 dev_err(&udc_controller->gadget.dev, "Can't initialize udc data structure\n");
2457 ret = -ENOMEM;
2458 goto err_free_irq;
2459 }
2460
2461 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2462 /* initialize usb hw reg except for regs for EP,
2463 * leave usbintr reg untouched */
2464 dr_controller_setup(udc_controller);
2465 }
2466
2467 /* Setup gadget structure */
2468 udc_controller->gadget.ops = &fsl_gadget_ops;
2469 udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2470 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2471 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2472 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2473 udc_controller->gadget.name = driver_name;
2474
2475 /* Setup gadget.dev and register with kernel */
2476 dev_set_name(&udc_controller->gadget.dev, "gadget");
2477 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2478
2479 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2480 udc_controller->gadget.is_otg = 1;
2481
2482 /* setup QH and epctrl for ep0 */
2483 ep0_setup(udc_controller);
2484
2485 /* setup udc->eps[] for ep0 */
2486 struct_ep_setup(udc_controller, 0, "ep0", 0);
2487 /* for ep0: the desc defined here;
2488 * for other eps, gadget layer called ep_enable with defined desc
2489 */
2490 udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
2491 usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep,
2492 USB_MAX_CTRL_PAYLOAD);
2493
2494 /* setup the udc->eps[] for non-control endpoints and link
2495 * to gadget.ep_list */
2496 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2497 char name[16];
2498
2499 sprintf(name, "ep%dout", i);
2500 struct_ep_setup(udc_controller, i * 2, name, 1);
2501 sprintf(name, "ep%din", i);
2502 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2503 }
2504
2505 /* use dma_pool for TD management */
2506 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2507 sizeof(struct ep_td_struct),
2508 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2509 if (udc_controller->td_pool == NULL) {
2510 ret = -ENOMEM;
2511 goto err_free_irq;
2512 }
2513
2514 ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
2515 fsl_udc_release);
2516 if (ret)
2517 goto err_del_udc;
2518
2519 create_proc_file();
2520 return 0;
2521
2522 err_del_udc:
2523 dma_pool_destroy(udc_controller->td_pool);
2524 err_free_irq:
2525 free_irq(udc_controller->irq, udc_controller);
2526 err_exit:
2527 if (pdata->exit)
2528 pdata->exit(pdev);
2529 err_iounmap:
2530 iounmap(dr_regs);
2531 err_release_mem_region:
2532 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2533 release_mem_region(res->start, resource_size(res));
2534 err_kfree:
2535 kfree(udc_controller);
2536 udc_controller = NULL;
2537 return ret;
2538 }
2539
2540 /* Driver removal function
2541 * Free resources and finish pending transactions
2542 */
fsl_udc_remove(struct platform_device * pdev)2543 static void fsl_udc_remove(struct platform_device *pdev)
2544 {
2545 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2546 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
2547
2548 DECLARE_COMPLETION_ONSTACK(done);
2549
2550 if (!udc_controller) {
2551 dev_err(&pdev->dev,
2552 "Driver still in use but removing anyhow\n");
2553 return;
2554 }
2555
2556 udc_controller->done = &done;
2557 usb_del_gadget_udc(&udc_controller->gadget);
2558
2559 /* DR has been stopped in usb_gadget_unregister_driver() */
2560 remove_proc_file();
2561
2562 /* Free allocated memory */
2563 kfree(udc_controller->status_req->req.buf);
2564 kfree(udc_controller->status_req);
2565 kfree(udc_controller->eps);
2566
2567 dma_pool_destroy(udc_controller->td_pool);
2568 free_irq(udc_controller->irq, udc_controller);
2569 iounmap(dr_regs);
2570 if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
2571 release_mem_region(res->start, resource_size(res));
2572
2573 /* free udc --wait for the release() finished */
2574 wait_for_completion(&done);
2575
2576 /*
2577 * do platform specific un-initialization:
2578 * release iomux pins, etc.
2579 */
2580 if (pdata->exit)
2581 pdata->exit(pdev);
2582 }
2583
2584 /*-----------------------------------------------------------------
2585 * Modify Power management attributes
2586 * Used by OTG statemachine to disable gadget temporarily
2587 -----------------------------------------------------------------*/
fsl_udc_suspend(struct platform_device * pdev,pm_message_t state)2588 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2589 {
2590 dr_controller_stop(udc_controller);
2591 return 0;
2592 }
2593
2594 /*-----------------------------------------------------------------
2595 * Invoked on USB resume. May be called in_interrupt.
2596 * Here we start the DR controller and enable the irq
2597 *-----------------------------------------------------------------*/
fsl_udc_resume(struct platform_device * pdev)2598 static int fsl_udc_resume(struct platform_device *pdev)
2599 {
2600 /* Enable DR irq reg and set controller Run */
2601 if (udc_controller->stopped) {
2602 dr_controller_setup(udc_controller);
2603 dr_controller_run(udc_controller);
2604 }
2605 udc_controller->usb_state = USB_STATE_ATTACHED;
2606 udc_controller->ep0_state = WAIT_FOR_SETUP;
2607 udc_controller->ep0_dir = 0;
2608 return 0;
2609 }
2610
fsl_udc_otg_suspend(struct device * dev,pm_message_t state)2611 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2612 {
2613 struct fsl_udc *udc = udc_controller;
2614 u32 mode, usbcmd;
2615
2616 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2617
2618 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2619
2620 /*
2621 * If the controller is already stopped, then this must be a
2622 * PM suspend. Remember this fact, so that we will leave the
2623 * controller stopped at PM resume time.
2624 */
2625 if (udc->stopped) {
2626 pr_debug("gadget already stopped, leaving early\n");
2627 udc->already_stopped = 1;
2628 return 0;
2629 }
2630
2631 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2632 pr_debug("gadget not in device mode, leaving early\n");
2633 return 0;
2634 }
2635
2636 /* stop the controller */
2637 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2638 fsl_writel(usbcmd, &dr_regs->usbcmd);
2639
2640 udc->stopped = 1;
2641
2642 pr_info("USB Gadget suspended\n");
2643
2644 return 0;
2645 }
2646
fsl_udc_otg_resume(struct device * dev)2647 static int fsl_udc_otg_resume(struct device *dev)
2648 {
2649 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2650 udc_controller->stopped, udc_controller->already_stopped);
2651
2652 /*
2653 * If the controller was stopped at suspend time, then
2654 * don't resume it now.
2655 */
2656 if (udc_controller->already_stopped) {
2657 udc_controller->already_stopped = 0;
2658 pr_debug("gadget was already stopped, leaving early\n");
2659 return 0;
2660 }
2661
2662 pr_info("USB Gadget resume\n");
2663
2664 return fsl_udc_resume(NULL);
2665 }
2666 /*-------------------------------------------------------------------------
2667 Register entry point for the peripheral controller driver
2668 --------------------------------------------------------------------------*/
2669 static const struct platform_device_id fsl_udc_devtype[] = {
2670 {
2671 .name = "fsl-usb2-udc",
2672 }, {
2673 /* sentinel */
2674 }
2675 };
2676 MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
2677
2678 static const struct of_device_id fsl_udc_dt_ids[] = {
2679 { .compatible = "fsl-usb2-dr" },
2680 { .compatible = "fsl-usb2-mph" },
2681 { .compatible = "fsl,mpc5121-usb2-dr" },
2682 { /* sentinel */ }
2683 };
2684 MODULE_DEVICE_TABLE(of, fsl_udc_dt_ids);
2685
2686 static struct platform_driver udc_driver = {
2687 .probe = fsl_udc_probe,
2688 .remove_new = fsl_udc_remove,
2689 .id_table = fsl_udc_devtype,
2690 /* these suspend and resume are not usb suspend and resume */
2691 .suspend = fsl_udc_suspend,
2692 .resume = fsl_udc_resume,
2693 .driver = {
2694 .name = driver_name,
2695 .of_match_table = fsl_udc_dt_ids,
2696 /* udc suspend/resume called from OTG driver */
2697 .suspend = fsl_udc_otg_suspend,
2698 .resume = fsl_udc_otg_resume,
2699 },
2700 };
2701
2702 module_platform_driver(udc_driver);
2703
2704 MODULE_DESCRIPTION(DRIVER_DESC);
2705 MODULE_AUTHOR(DRIVER_AUTHOR);
2706 MODULE_LICENSE("GPL");
2707 MODULE_ALIAS("platform:fsl-usb2-udc");
2708