1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the ARM specific subclass of TargetMachine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H 15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H 16 17 #include "ARMInstrInfo.h" 18 #include "ARMSubtarget.h" 19 #include "llvm/IR/DataLayout.h" 20 #include "llvm/Target/TargetMachine.h" 21 22 namespace llvm { 23 24 class ARMBaseTargetMachine : public LLVMTargetMachine { 25 public: 26 enum ARMABI { 27 ARM_ABI_UNKNOWN, 28 ARM_ABI_APCS, 29 ARM_ABI_AAPCS // ARM EABI 30 } TargetABI; 31 32 protected: 33 std::unique_ptr<TargetLoweringObjectFile> TLOF; 34 ARMSubtarget Subtarget; 35 bool isLittle; 36 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap; 37 38 public: 39 ARMBaseTargetMachine(const Target &T, StringRef TT, 40 StringRef CPU, StringRef FS, 41 const TargetOptions &Options, 42 Reloc::Model RM, CodeModel::Model CM, 43 CodeGenOpt::Level OL, 44 bool isLittle); 45 ~ARMBaseTargetMachine() override; 46 getSubtargetImpl()47 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; } 48 const ARMSubtarget *getSubtargetImpl(const Function &F) const override; 49 50 /// \brief Register ARM analysis passes with a pass manager. 51 void addAnalysisPasses(PassManagerBase &PM) override; 52 53 // Pass Pipeline Configuration 54 TargetPassConfig *createPassConfig(PassManagerBase &PM) override; 55 getObjFileLowering()56 TargetLoweringObjectFile *getObjFileLowering() const override { 57 return TLOF.get(); 58 } 59 }; 60 61 /// ARMTargetMachine - ARM target machine. 62 /// 63 class ARMTargetMachine : public ARMBaseTargetMachine { 64 virtual void anchor(); 65 public: 66 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, 67 const TargetOptions &Options, Reloc::Model RM, 68 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle); 69 }; 70 71 /// ARMLETargetMachine - ARM little endian target machine. 72 /// 73 class ARMLETargetMachine : public ARMTargetMachine { 74 void anchor() override; 75 public: 76 ARMLETargetMachine(const Target &T, StringRef TT, 77 StringRef CPU, StringRef FS, const TargetOptions &Options, 78 Reloc::Model RM, CodeModel::Model CM, 79 CodeGenOpt::Level OL); 80 }; 81 82 /// ARMBETargetMachine - ARM big endian target machine. 83 /// 84 class ARMBETargetMachine : public ARMTargetMachine { 85 void anchor() override; 86 public: 87 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, 88 const TargetOptions &Options, Reloc::Model RM, 89 CodeModel::Model CM, CodeGenOpt::Level OL); 90 }; 91 92 /// ThumbTargetMachine - Thumb target machine. 93 /// Due to the way architectures are handled, this represents both 94 /// Thumb-1 and Thumb-2. 95 /// 96 class ThumbTargetMachine : public ARMBaseTargetMachine { 97 virtual void anchor(); 98 public: 99 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, 100 const TargetOptions &Options, Reloc::Model RM, 101 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle); 102 }; 103 104 /// ThumbLETargetMachine - Thumb little endian target machine. 105 /// 106 class ThumbLETargetMachine : public ThumbTargetMachine { 107 void anchor() override; 108 public: 109 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU, 110 StringRef FS, const TargetOptions &Options, 111 Reloc::Model RM, CodeModel::Model CM, 112 CodeGenOpt::Level OL); 113 }; 114 115 /// ThumbBETargetMachine - Thumb big endian target machine. 116 /// 117 class ThumbBETargetMachine : public ThumbTargetMachine { 118 void anchor() override; 119 public: 120 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU, 121 StringRef FS, const TargetOptions &Options, 122 Reloc::Model RM, CodeModel::Model CM, 123 CodeGenOpt::Level OL); 124 }; 125 126 } // end namespace llvm 127 128 #endif 129