1 //===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// ARM target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
14 ///
15 //===----------------------------------------------------------------------===//
16
17 #include "ARM.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/Analysis/TargetTransformInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Target/CostTable.h"
22 #include "llvm/Target/TargetLowering.h"
23 using namespace llvm;
24
25 #define DEBUG_TYPE "armtti"
26
27 // Declare the pass initialization routine locally as target-specific passes
28 // don't have a target-wide initialization entry point, and so we rely on the
29 // pass constructor initialization.
30 namespace llvm {
31 void initializeARMTTIPass(PassRegistry &);
32 }
33
34 namespace {
35
36 class ARMTTI final : public ImmutablePass, public TargetTransformInfo {
37 const ARMBaseTargetMachine *TM;
38 const ARMSubtarget *ST;
39 const ARMTargetLowering *TLI;
40
41 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
42 /// are set if the result needs to be inserted and/or extracted from vectors.
43 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
44
45 public:
ARMTTI()46 ARMTTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) {
47 llvm_unreachable("This pass cannot be directly constructed");
48 }
49
ARMTTI(const ARMBaseTargetMachine * TM)50 ARMTTI(const ARMBaseTargetMachine *TM)
51 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
52 TLI(TM->getSubtargetImpl()->getTargetLowering()) {
53 initializeARMTTIPass(*PassRegistry::getPassRegistry());
54 }
55
initializePass()56 void initializePass() override {
57 pushTTIStack(this);
58 }
59
getAnalysisUsage(AnalysisUsage & AU) const60 void getAnalysisUsage(AnalysisUsage &AU) const override {
61 TargetTransformInfo::getAnalysisUsage(AU);
62 }
63
64 /// Pass identification.
65 static char ID;
66
67 /// Provide necessary pointer adjustments for the two base classes.
getAdjustedAnalysisPointer(const void * ID)68 void *getAdjustedAnalysisPointer(const void *ID) override {
69 if (ID == &TargetTransformInfo::ID)
70 return (TargetTransformInfo*)this;
71 return this;
72 }
73
74 /// \name Scalar TTI Implementations
75 /// @{
76 using TargetTransformInfo::getIntImmCost;
77 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
78
79 /// @}
80
81
82 /// \name Vector TTI Implementations
83 /// @{
84
getNumberOfRegisters(bool Vector) const85 unsigned getNumberOfRegisters(bool Vector) const override {
86 if (Vector) {
87 if (ST->hasNEON())
88 return 16;
89 return 0;
90 }
91
92 if (ST->isThumb1Only())
93 return 8;
94 return 13;
95 }
96
getRegisterBitWidth(bool Vector) const97 unsigned getRegisterBitWidth(bool Vector) const override {
98 if (Vector) {
99 if (ST->hasNEON())
100 return 128;
101 return 0;
102 }
103
104 return 32;
105 }
106
getMaxInterleaveFactor() const107 unsigned getMaxInterleaveFactor() const override {
108 // These are out of order CPUs:
109 if (ST->isCortexA15() || ST->isSwift())
110 return 2;
111 return 1;
112 }
113
114 unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
115 int Index, Type *SubTp) const override;
116
117 unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
118 Type *Src) const override;
119
120 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
121 Type *CondTy) const override;
122
123 unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
124 unsigned Index) const override;
125
126 unsigned getAddressComputationCost(Type *Val,
127 bool IsComplex) const override;
128
129 unsigned getArithmeticInstrCost(
130 unsigned Opcode, Type *Ty, OperandValueKind Op1Info = OK_AnyValue,
131 OperandValueKind Op2Info = OK_AnyValue,
132 OperandValueProperties Opd1PropInfo = OP_None,
133 OperandValueProperties Opd2PropInfo = OP_None) const override;
134
135 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
136 unsigned AddressSpace) const override;
137 /// @}
138 };
139
140 } // end anonymous namespace
141
142 INITIALIZE_AG_PASS(ARMTTI, TargetTransformInfo, "armtti",
143 "ARM Target Transform Info", true, true, false)
144 char ARMTTI::ID = 0;
145
146 ImmutablePass *
createARMTargetTransformInfoPass(const ARMBaseTargetMachine * TM)147 llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) {
148 return new ARMTTI(TM);
149 }
150
151
getIntImmCost(const APInt & Imm,Type * Ty) const152 unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
153 assert(Ty->isIntegerTy());
154
155 unsigned Bits = Ty->getPrimitiveSizeInBits();
156 if (Bits == 0 || Bits > 32)
157 return 4;
158
159 int32_t SImmVal = Imm.getSExtValue();
160 uint32_t ZImmVal = Imm.getZExtValue();
161 if (!ST->isThumb()) {
162 if ((SImmVal >= 0 && SImmVal < 65536) ||
163 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
164 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
165 return 1;
166 return ST->hasV6T2Ops() ? 2 : 3;
167 }
168 if (ST->isThumb2()) {
169 if ((SImmVal >= 0 && SImmVal < 65536) ||
170 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
171 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
172 return 1;
173 return ST->hasV6T2Ops() ? 2 : 3;
174 }
175 // Thumb1.
176 if (SImmVal >= 0 && SImmVal < 256)
177 return 1;
178 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
179 return 2;
180 // Load from constantpool.
181 return 3;
182 }
183
getCastInstrCost(unsigned Opcode,Type * Dst,Type * Src) const184 unsigned ARMTTI::getCastInstrCost(unsigned Opcode, Type *Dst,
185 Type *Src) const {
186 int ISD = TLI->InstructionOpcodeToISD(Opcode);
187 assert(ISD && "Invalid opcode");
188
189 // Single to/from double precision conversions.
190 static const CostTblEntry<MVT::SimpleValueType> NEONFltDblTbl[] = {
191 // Vector fptrunc/fpext conversions.
192 { ISD::FP_ROUND, MVT::v2f64, 2 },
193 { ISD::FP_EXTEND, MVT::v2f32, 2 },
194 { ISD::FP_EXTEND, MVT::v4f32, 4 }
195 };
196
197 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
198 ISD == ISD::FP_EXTEND)) {
199 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
200 int Idx = CostTableLookup(NEONFltDblTbl, ISD, LT.second);
201 if (Idx != -1)
202 return LT.first * NEONFltDblTbl[Idx].Cost;
203 }
204
205 EVT SrcTy = TLI->getValueType(Src);
206 EVT DstTy = TLI->getValueType(Dst);
207
208 if (!SrcTy.isSimple() || !DstTy.isSimple())
209 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
210
211 // Some arithmetic, load and store operations have specific instructions
212 // to cast up/down their types automatically at no extra cost.
213 // TODO: Get these tables to know at least what the related operations are.
214 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
215 NEONVectorConversionTbl[] = {
216 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
217 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
218 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
219 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
220 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
221 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
222
223 // The number of vmovl instructions for the extension.
224 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
225 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
226 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
227 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
228 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
229 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
230 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
231 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
232 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
233 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
234
235 // Operations that we legalize using splitting.
236 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
237 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
238
239 // Vector float <-> i32 conversions.
240 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
241 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
242
243 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
244 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
245 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
246 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
247 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
248 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
249 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
250 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
251 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
252 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
253 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
254 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
255 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
256 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
257 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
258 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
259 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
260 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
261 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
262 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
263
264 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
265 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
266 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
267 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
268 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
269 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
270
271 // Vector double <-> i32 conversions.
272 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
273 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
274
275 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
276 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
277 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
278 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
279 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
280 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
281
282 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
283 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
284 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
285 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
286 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
287 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
288 };
289
290 if (SrcTy.isVector() && ST->hasNEON()) {
291 int Idx = ConvertCostTableLookup(NEONVectorConversionTbl, ISD,
292 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
293 if (Idx != -1)
294 return NEONVectorConversionTbl[Idx].Cost;
295 }
296
297 // Scalar float to integer conversions.
298 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
299 NEONFloatConversionTbl[] = {
300 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
301 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
302 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
303 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
304 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
305 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
306 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
307 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
308 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
309 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
310 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
311 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
312 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
313 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
314 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
315 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
316 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
317 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
318 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
319 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
320 };
321 if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
322 int Idx = ConvertCostTableLookup(NEONFloatConversionTbl, ISD,
323 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
324 if (Idx != -1)
325 return NEONFloatConversionTbl[Idx].Cost;
326 }
327
328 // Scalar integer to float conversions.
329 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
330 NEONIntegerConversionTbl[] = {
331 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
332 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
333 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 },
334 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 },
335 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
336 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
337 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
338 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
339 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
340 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
341 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
342 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
343 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
344 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
345 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 },
346 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 },
347 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
348 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
349 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 },
350 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 }
351 };
352
353 if (SrcTy.isInteger() && ST->hasNEON()) {
354 int Idx = ConvertCostTableLookup(NEONIntegerConversionTbl, ISD,
355 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
356 if (Idx != -1)
357 return NEONIntegerConversionTbl[Idx].Cost;
358 }
359
360 // Scalar integer conversion costs.
361 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
362 ARMIntegerConversionTbl[] = {
363 // i16 -> i64 requires two dependent operations.
364 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
365
366 // Truncates on i64 are assumed to be free.
367 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 },
368 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 },
369 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
370 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
371 };
372
373 if (SrcTy.isInteger()) {
374 int Idx = ConvertCostTableLookup(ARMIntegerConversionTbl, ISD,
375 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
376 if (Idx != -1)
377 return ARMIntegerConversionTbl[Idx].Cost;
378 }
379
380 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
381 }
382
getVectorInstrCost(unsigned Opcode,Type * ValTy,unsigned Index) const383 unsigned ARMTTI::getVectorInstrCost(unsigned Opcode, Type *ValTy,
384 unsigned Index) const {
385 // Penalize inserting into an D-subregister. We end up with a three times
386 // lower estimated throughput on swift.
387 if (ST->isSwift() &&
388 Opcode == Instruction::InsertElement &&
389 ValTy->isVectorTy() &&
390 ValTy->getScalarSizeInBits() <= 32)
391 return 3;
392
393 // Cross-class copies are expensive on many microarchitectures,
394 // so assume they are expensive by default.
395 if ((Opcode == Instruction::InsertElement ||
396 Opcode == Instruction::ExtractElement) &&
397 ValTy->getVectorElementType()->isIntegerTy())
398 return 3;
399
400 return TargetTransformInfo::getVectorInstrCost(Opcode, ValTy, Index);
401 }
402
getCmpSelInstrCost(unsigned Opcode,Type * ValTy,Type * CondTy) const403 unsigned ARMTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
404 Type *CondTy) const {
405
406 int ISD = TLI->InstructionOpcodeToISD(Opcode);
407 // On NEON a a vector select gets lowered to vbsl.
408 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
409 // Lowering of some vector selects is currently far from perfect.
410 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
411 NEONVectorSelectTbl[] = {
412 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 },
413 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
414 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
415 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
416 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
417 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }
418 };
419
420 EVT SelCondTy = TLI->getValueType(CondTy);
421 EVT SelValTy = TLI->getValueType(ValTy);
422 if (SelCondTy.isSimple() && SelValTy.isSimple()) {
423 int Idx = ConvertCostTableLookup(NEONVectorSelectTbl, ISD,
424 SelCondTy.getSimpleVT(),
425 SelValTy.getSimpleVT());
426 if (Idx != -1)
427 return NEONVectorSelectTbl[Idx].Cost;
428 }
429
430 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
431 return LT.first;
432 }
433
434 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
435 }
436
getAddressComputationCost(Type * Ty,bool IsComplex) const437 unsigned ARMTTI::getAddressComputationCost(Type *Ty, bool IsComplex) const {
438 // Address computations in vectorized code with non-consecutive addresses will
439 // likely result in more instructions compared to scalar code where the
440 // computation can more often be merged into the index mode. The resulting
441 // extra micro-ops can significantly decrease throughput.
442 unsigned NumVectorInstToHideOverhead = 10;
443
444 if (Ty->isVectorTy() && IsComplex)
445 return NumVectorInstToHideOverhead;
446
447 // In many cases the address computation is not merged into the instruction
448 // addressing mode.
449 return 1;
450 }
451
getShuffleCost(ShuffleKind Kind,Type * Tp,int Index,Type * SubTp) const452 unsigned ARMTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
453 Type *SubTp) const {
454 // We only handle costs of reverse and alternate shuffles for now.
455 if (Kind != SK_Reverse && Kind != SK_Alternate)
456 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
457
458 if (Kind == SK_Reverse) {
459 static const CostTblEntry<MVT::SimpleValueType> NEONShuffleTbl[] = {
460 // Reverse shuffle cost one instruction if we are shuffling within a
461 // double word (vrev) or two if we shuffle a quad word (vrev, vext).
462 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
463 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
464 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
465 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
466
467 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
468 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
469 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 2},
470 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 2}};
471
472 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
473
474 int Idx = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
475 if (Idx == -1)
476 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
477
478 return LT.first * NEONShuffleTbl[Idx].Cost;
479 }
480 if (Kind == SK_Alternate) {
481 static const CostTblEntry<MVT::SimpleValueType> NEONAltShuffleTbl[] = {
482 // Alt shuffle cost table for ARM. Cost is the number of instructions
483 // required to create the shuffled vector.
484
485 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
486 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
487 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
488 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
489
490 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
491 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
492 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 2},
493
494 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 16},
495
496 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 32}};
497
498 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
499 int Idx =
500 CostTableLookup(NEONAltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
501 if (Idx == -1)
502 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
503 return LT.first * NEONAltShuffleTbl[Idx].Cost;
504 }
505 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
506 }
507
getArithmeticInstrCost(unsigned Opcode,Type * Ty,OperandValueKind Op1Info,OperandValueKind Op2Info,OperandValueProperties Opd1PropInfo,OperandValueProperties Opd2PropInfo) const508 unsigned ARMTTI::getArithmeticInstrCost(
509 unsigned Opcode, Type *Ty, OperandValueKind Op1Info,
510 OperandValueKind Op2Info, OperandValueProperties Opd1PropInfo,
511 OperandValueProperties Opd2PropInfo) const {
512
513 int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
514 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
515
516 const unsigned FunctionCallDivCost = 20;
517 const unsigned ReciprocalDivCost = 10;
518 static const CostTblEntry<MVT::SimpleValueType> CostTbl[] = {
519 // Division.
520 // These costs are somewhat random. Choose a cost of 20 to indicate that
521 // vectorizing devision (added function call) is going to be very expensive.
522 // Double registers types.
523 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
524 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
525 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
526 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
527 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
528 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost},
529 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
530 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
531 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
532 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost},
533 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
534 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
535 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
536 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost},
537 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
538 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
539 // Quad register types.
540 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
541 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
542 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
543 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
544 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
545 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost},
546 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
547 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
548 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
549 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
550 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
551 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
552 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
553 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
554 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
555 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
556 // Multiplication.
557 };
558
559 int Idx = -1;
560
561 if (ST->hasNEON())
562 Idx = CostTableLookup(CostTbl, ISDOpcode, LT.second);
563
564 if (Idx != -1)
565 return LT.first * CostTbl[Idx].Cost;
566
567 unsigned Cost = TargetTransformInfo::getArithmeticInstrCost(
568 Opcode, Ty, Op1Info, Op2Info, Opd1PropInfo, Opd2PropInfo);
569
570 // This is somewhat of a hack. The problem that we are facing is that SROA
571 // creates a sequence of shift, and, or instructions to construct values.
572 // These sequences are recognized by the ISel and have zero-cost. Not so for
573 // the vectorized code. Because we have support for v2i64 but not i64 those
574 // sequences look particularly beneficial to vectorize.
575 // To work around this we increase the cost of v2i64 operations to make them
576 // seem less beneficial.
577 if (LT.second == MVT::v2i64 &&
578 Op2Info == TargetTransformInfo::OK_UniformConstantValue)
579 Cost += 4;
580
581 return Cost;
582 }
583
getMemoryOpCost(unsigned Opcode,Type * Src,unsigned Alignment,unsigned AddressSpace) const584 unsigned ARMTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
585 unsigned AddressSpace) const {
586 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
587
588 if (Src->isVectorTy() && Alignment != 16 &&
589 Src->getVectorElementType()->isDoubleTy()) {
590 // Unaligned loads/stores are extremely inefficient.
591 // We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr.
592 return LT.first * 4;
593 }
594 return LT.first;
595 }
596