1 //===-- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "Thumb1RegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetMachine.h"
34
35 namespace llvm {
36 extern cl::opt<bool> ReuseFrameIndexVals;
37 }
38
39 using namespace llvm;
40
Thumb1RegisterInfo(const ARMSubtarget & sti)41 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMSubtarget &sti)
42 : ARMBaseRegisterInfo(sti) {
43 }
44
45 const TargetRegisterClass*
getLargestLegalSuperClass(const TargetRegisterClass * RC) const46 Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
47 const {
48 if (ARM::tGPRRegClass.hasSubClassEq(RC))
49 return &ARM::tGPRRegClass;
50 return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
51 }
52
53 const TargetRegisterClass *
getPointerRegClass(const MachineFunction & MF,unsigned Kind) const54 Thumb1RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
55 const {
56 return &ARM::tGPRRegClass;
57 }
58
59 /// emitLoadConstPool - Emits a load from constpool to materialize the
60 /// specified immediate.
61 void
emitLoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,DebugLoc dl,unsigned DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,unsigned PredReg,unsigned MIFlags) const62 Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator &MBBI,
64 DebugLoc dl,
65 unsigned DestReg, unsigned SubIdx,
66 int Val,
67 ARMCC::CondCodes Pred, unsigned PredReg,
68 unsigned MIFlags) const {
69 assert((isARMLowRegister(DestReg) ||
70 isVirtualRegister(DestReg)) &&
71 "Thumb1 does not have ldr to high register");
72
73 MachineFunction &MF = *MBB.getParent();
74 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
75 MachineConstantPool *ConstantPool = MF.getConstantPool();
76 const Constant *C = ConstantInt::get(
77 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
78 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
79
80 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
81 .addReg(DestReg, getDefRegState(true), SubIdx)
82 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
83 .setMIFlags(MIFlags);
84 }
85
86
87 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
88 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
89 /// in a register using mov / mvn sequences or load the immediate from a
90 /// constpool entry.
91 static
emitThumbRegPlusImmInReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,DebugLoc dl,unsigned DestReg,unsigned BaseReg,int NumBytes,bool CanChangeCC,const TargetInstrInfo & TII,const ARMBaseRegisterInfo & MRI,unsigned MIFlags=MachineInstr::NoFlags)92 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator &MBBI,
94 DebugLoc dl,
95 unsigned DestReg, unsigned BaseReg,
96 int NumBytes, bool CanChangeCC,
97 const TargetInstrInfo &TII,
98 const ARMBaseRegisterInfo& MRI,
99 unsigned MIFlags = MachineInstr::NoFlags) {
100 MachineFunction &MF = *MBB.getParent();
101 bool isHigh = !isARMLowRegister(DestReg) ||
102 (BaseReg != 0 && !isARMLowRegister(BaseReg));
103 bool isSub = false;
104 // Subtract doesn't have high register version. Load the negative value
105 // if either base or dest register is a high register. Also, if do not
106 // issue sub as part of the sequence if condition register is to be
107 // preserved.
108 if (NumBytes < 0 && !isHigh && CanChangeCC) {
109 isSub = true;
110 NumBytes = -NumBytes;
111 }
112 unsigned LdReg = DestReg;
113 if (DestReg == ARM::SP)
114 assert(BaseReg == ARM::SP && "Unexpected!");
115 if (!isARMLowRegister(DestReg) && !MRI.isVirtualRegister(DestReg))
116 LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
117
118 if (NumBytes <= 255 && NumBytes >= 0 && CanChangeCC) {
119 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
120 .addImm(NumBytes).setMIFlags(MIFlags);
121 } else if (NumBytes < 0 && NumBytes >= -255 && CanChangeCC) {
122 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
123 .addImm(NumBytes).setMIFlags(MIFlags);
124 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
125 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags);
126 } else
127 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes,
128 ARMCC::AL, 0, MIFlags);
129
130 // Emit add / sub.
131 int Opc = (isSub) ? ARM::tSUBrr : ((isHigh || !CanChangeCC) ? ARM::tADDhirr
132 : ARM::tADDrr);
133 MachineInstrBuilder MIB =
134 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
135 if (Opc != ARM::tADDhirr)
136 MIB = AddDefaultT1CC(MIB);
137 if (DestReg == ARM::SP || isSub)
138 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
139 else
140 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
141 AddDefaultPred(MIB);
142 }
143
144 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
145 /// a destreg = basereg + immediate in Thumb code. Tries a series of ADDs or
146 /// SUBs first, and uses a constant pool value if the instruction sequence would
147 /// be too long. This is allowed to modify the condition flags.
emitThumbRegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,DebugLoc dl,unsigned DestReg,unsigned BaseReg,int NumBytes,const TargetInstrInfo & TII,const ARMBaseRegisterInfo & MRI,unsigned MIFlags)148 void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
149 MachineBasicBlock::iterator &MBBI,
150 DebugLoc dl,
151 unsigned DestReg, unsigned BaseReg,
152 int NumBytes, const TargetInstrInfo &TII,
153 const ARMBaseRegisterInfo& MRI,
154 unsigned MIFlags) {
155 bool isSub = NumBytes < 0;
156 unsigned Bytes = (unsigned)NumBytes;
157 if (isSub) Bytes = -NumBytes;
158
159 int CopyOpc = 0;
160 unsigned CopyBits = 0;
161 unsigned CopyScale = 1;
162 bool CopyNeedsCC = false;
163 int ExtraOpc = 0;
164 unsigned ExtraBits = 0;
165 unsigned ExtraScale = 1;
166 bool ExtraNeedsCC = false;
167
168 // Strategy:
169 // We need to select two types of instruction, maximizing the available
170 // immediate range of each. The instructions we use will depend on whether
171 // DestReg and BaseReg are low, high or the stack pointer.
172 // * CopyOpc - DestReg = BaseReg + imm
173 // This will be emitted once if DestReg != BaseReg, and never if
174 // DestReg == BaseReg.
175 // * ExtraOpc - DestReg = DestReg + imm
176 // This will be emitted as many times as necessary to add the
177 // full immediate.
178 // If the immediate ranges of these instructions are not large enough to cover
179 // NumBytes with a reasonable number of instructions, we fall back to using a
180 // value loaded from a constant pool.
181 if (DestReg == ARM::SP) {
182 if (BaseReg == ARM::SP) {
183 // sp -> sp
184 // Already in right reg, no copy needed
185 } else {
186 // low -> sp or high -> sp
187 CopyOpc = ARM::tMOVr;
188 CopyBits = 0;
189 }
190 ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi;
191 ExtraBits = 7;
192 ExtraScale = 4;
193 } else if (isARMLowRegister(DestReg)) {
194 if (BaseReg == ARM::SP) {
195 // sp -> low
196 assert(!isSub && "Thumb1 does not have tSUBrSPi");
197 CopyOpc = ARM::tADDrSPi;
198 CopyBits = 8;
199 CopyScale = 4;
200 } else if (DestReg == BaseReg) {
201 // low -> same low
202 // Already in right reg, no copy needed
203 } else if (isARMLowRegister(BaseReg)) {
204 // low -> different low
205 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3;
206 CopyBits = 3;
207 CopyNeedsCC = true;
208 } else {
209 // high -> low
210 CopyOpc = ARM::tMOVr;
211 CopyBits = 0;
212 }
213 ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
214 ExtraBits = 8;
215 ExtraNeedsCC = true;
216 } else /* DestReg is high */ {
217 if (DestReg == BaseReg) {
218 // high -> same high
219 // Already in right reg, no copy needed
220 } else {
221 // {low,high,sp} -> high
222 CopyOpc = ARM::tMOVr;
223 CopyBits = 0;
224 }
225 ExtraOpc = 0;
226 }
227
228 // We could handle an unaligned immediate with an unaligned copy instruction
229 // and an aligned extra instruction, but this case is not currently needed.
230 assert(((Bytes & 3) == 0 || ExtraScale == 1) &&
231 "Unaligned offset, but all instructions require alignment");
232
233 unsigned CopyRange = ((1 << CopyBits) - 1) * CopyScale;
234 // If we would emit the copy with an immediate of 0, just use tMOVr.
235 if (CopyOpc && Bytes < CopyScale) {
236 CopyOpc = ARM::tMOVr;
237 CopyScale = 1;
238 CopyNeedsCC = false;
239 CopyRange = 0;
240 }
241 unsigned ExtraRange = ((1 << ExtraBits) - 1) * ExtraScale; // per instruction
242 unsigned RequiredCopyInstrs = CopyOpc ? 1 : 0;
243 unsigned RangeAfterCopy = (CopyRange > Bytes) ? 0 : (Bytes - CopyRange);
244
245 // We could handle this case when the copy instruction does not require an
246 // aligned immediate, but we do not currently do this.
247 assert(RangeAfterCopy % ExtraScale == 0 &&
248 "Extra instruction requires immediate to be aligned");
249
250 unsigned RequiredExtraInstrs;
251 if (ExtraRange)
252 RequiredExtraInstrs = RoundUpToAlignment(RangeAfterCopy, ExtraRange) / ExtraRange;
253 else if (RangeAfterCopy > 0)
254 // We need an extra instruction but none is available
255 RequiredExtraInstrs = 1000000;
256 else
257 RequiredExtraInstrs = 0;
258 unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs;
259 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
260
261 // Use a constant pool, if the sequence of ADDs/SUBs is too expensive.
262 if (RequiredInstrs > Threshold) {
263 emitThumbRegPlusImmInReg(MBB, MBBI, dl,
264 DestReg, BaseReg, NumBytes, true,
265 TII, MRI, MIFlags);
266 return;
267 }
268
269 // Emit zero or one copy instructions
270 if (CopyOpc) {
271 unsigned CopyImm = std::min(Bytes, CopyRange) / CopyScale;
272 Bytes -= CopyImm * CopyScale;
273
274 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
275 if (CopyNeedsCC)
276 MIB = AddDefaultT1CC(MIB);
277 MIB.addReg(BaseReg, RegState::Kill);
278 if (CopyOpc != ARM::tMOVr) {
279 MIB.addImm(CopyImm);
280 }
281 AddDefaultPred(MIB.setMIFlags(MIFlags));
282
283 BaseReg = DestReg;
284 }
285
286 // Emit zero or more in-place add/sub instructions
287 while (Bytes) {
288 unsigned ExtraImm = std::min(Bytes, ExtraRange) / ExtraScale;
289 Bytes -= ExtraImm * ExtraScale;
290
291 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg);
292 if (ExtraNeedsCC)
293 MIB = AddDefaultT1CC(MIB);
294 MIB.addReg(BaseReg).addImm(ExtraImm);
295 MIB = AddDefaultPred(MIB);
296 MIB.setMIFlags(MIFlags);
297 }
298 }
299
removeOperands(MachineInstr & MI,unsigned i)300 static void removeOperands(MachineInstr &MI, unsigned i) {
301 unsigned Op = i;
302 for (unsigned e = MI.getNumOperands(); i != e; ++i)
303 MI.RemoveOperand(Op);
304 }
305
306 /// convertToNonSPOpcode - Change the opcode to the non-SP version, because
307 /// we're replacing the frame index with a non-SP register.
convertToNonSPOpcode(unsigned Opcode)308 static unsigned convertToNonSPOpcode(unsigned Opcode) {
309 switch (Opcode) {
310 case ARM::tLDRspi:
311 return ARM::tLDRi;
312
313 case ARM::tSTRspi:
314 return ARM::tSTRi;
315 }
316
317 return Opcode;
318 }
319
320 bool Thumb1RegisterInfo::
rewriteFrameIndex(MachineBasicBlock::iterator II,unsigned FrameRegIdx,unsigned FrameReg,int & Offset,const ARMBaseInstrInfo & TII) const321 rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
322 unsigned FrameReg, int &Offset,
323 const ARMBaseInstrInfo &TII) const {
324 MachineInstr &MI = *II;
325 MachineBasicBlock &MBB = *MI.getParent();
326 DebugLoc dl = MI.getDebugLoc();
327 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
328 unsigned Opcode = MI.getOpcode();
329 const MCInstrDesc &Desc = MI.getDesc();
330 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
331
332 if (Opcode == ARM::tADDframe) {
333 Offset += MI.getOperand(FrameRegIdx+1).getImm();
334 unsigned DestReg = MI.getOperand(0).getReg();
335
336 emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
337 *this);
338 MBB.erase(II);
339 return true;
340 } else {
341 if (AddrMode != ARMII::AddrModeT1_s)
342 llvm_unreachable("Unsupported addressing mode!");
343
344 unsigned ImmIdx = FrameRegIdx + 1;
345 int InstrOffs = MI.getOperand(ImmIdx).getImm();
346 unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
347 unsigned Scale = 4;
348
349 Offset += InstrOffs * Scale;
350 assert((Offset & (Scale - 1)) == 0 && "Can't encode this offset!");
351
352 // Common case: small offset, fits into instruction.
353 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
354 int ImmedOffset = Offset / Scale;
355 unsigned Mask = (1 << NumBits) - 1;
356
357 if ((unsigned)Offset <= Mask * Scale) {
358 // Replace the FrameIndex with the frame register (e.g., sp).
359 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
360 ImmOp.ChangeToImmediate(ImmedOffset);
361
362 // If we're using a register where sp was stored, convert the instruction
363 // to the non-SP version.
364 unsigned NewOpc = convertToNonSPOpcode(Opcode);
365 if (NewOpc != Opcode && FrameReg != ARM::SP)
366 MI.setDesc(TII.get(NewOpc));
367
368 return true;
369 }
370
371 NumBits = 5;
372 Mask = (1 << NumBits) - 1;
373
374 // If this is a thumb spill / restore, we will be using a constpool load to
375 // materialize the offset.
376 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
377 ImmOp.ChangeToImmediate(0);
378 } else {
379 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
380 ImmedOffset = ImmedOffset & Mask;
381 ImmOp.ChangeToImmediate(ImmedOffset);
382 Offset &= ~(Mask * Scale);
383 }
384 }
385
386 return Offset == 0;
387 }
388
resolveFrameIndex(MachineInstr & MI,unsigned BaseReg,int64_t Offset) const389 void Thumb1RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
390 int64_t Offset) const {
391 const ARMBaseInstrInfo &TII =
392 *static_cast<const ARMBaseInstrInfo *>(MI.getParent()
393 ->getParent()
394 ->getTarget()
395 .getSubtargetImpl()
396 ->getInstrInfo());
397 int Off = Offset; // ARM doesn't need the general 64-bit offsets
398 unsigned i = 0;
399
400 while (!MI.getOperand(i).isFI()) {
401 ++i;
402 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
403 }
404 bool Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
405 assert (Done && "Unable to resolve frame index!");
406 (void)Done;
407 }
408
409 /// saveScavengerRegister - Spill the register so it can be used by the
410 /// register scavenger. Return true.
411 bool
saveScavengerRegister(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,MachineBasicBlock::iterator & UseMI,const TargetRegisterClass * RC,unsigned Reg) const412 Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
413 MachineBasicBlock::iterator I,
414 MachineBasicBlock::iterator &UseMI,
415 const TargetRegisterClass *RC,
416 unsigned Reg) const {
417 // Thumb1 can't use the emergency spill slot on the stack because
418 // ldr/str immediate offsets must be positive, and if we're referencing
419 // off the frame pointer (if, for example, there are alloca() calls in
420 // the function, the offset will be negative. Use R12 instead since that's
421 // a call clobbered register that we know won't be used in Thumb1 mode.
422 const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
423 DebugLoc DL;
424 AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
425 .addReg(ARM::R12, RegState::Define)
426 .addReg(Reg, RegState::Kill));
427
428 // The UseMI is where we would like to restore the register. If there's
429 // interference with R12 before then, however, we'll need to restore it
430 // before that instead and adjust the UseMI.
431 bool done = false;
432 for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
433 if (II->isDebugValue())
434 continue;
435 // If this instruction affects R12, adjust our restore point.
436 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
437 const MachineOperand &MO = II->getOperand(i);
438 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {
439 UseMI = II;
440 done = true;
441 break;
442 }
443 if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
444 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
445 continue;
446 if (MO.getReg() == ARM::R12) {
447 UseMI = II;
448 done = true;
449 break;
450 }
451 }
452 }
453 // Restore the register from R12
454 AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
455 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
456
457 return true;
458 }
459
460 void
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const461 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
462 int SPAdj, unsigned FIOperandNum,
463 RegScavenger *RS) const {
464 unsigned VReg = 0;
465 MachineInstr &MI = *II;
466 MachineBasicBlock &MBB = *MI.getParent();
467 MachineFunction &MF = *MBB.getParent();
468 const ARMBaseInstrInfo &TII =
469 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
470 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
471 DebugLoc dl = MI.getDebugLoc();
472 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
473
474 unsigned FrameReg = ARM::SP;
475 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
476 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
477 MF.getFrameInfo()->getStackSize() + SPAdj;
478
479 if (MF.getFrameInfo()->hasVarSizedObjects()) {
480 assert(SPAdj == 0 && MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
481 "Unexpected");
482 // There are alloca()'s in this function, must reference off the frame
483 // pointer or base pointer instead.
484 if (!hasBasePointer(MF)) {
485 FrameReg = getFrameRegister(MF);
486 Offset -= AFI->getFramePtrSpillOffset();
487 } else
488 FrameReg = BasePtr;
489 }
490
491 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
492 // call frame setup/destroy instructions have already been eliminated. That
493 // means the stack pointer cannot be used to access the emergency spill slot
494 // when !hasReservedCallFrame().
495 #ifndef NDEBUG
496 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
497 assert(MF.getTarget()
498 .getSubtargetImpl()
499 ->getFrameLowering()
500 ->hasReservedCallFrame(MF) &&
501 "Cannot use SP to access the emergency spill slot in "
502 "functions without a reserved call frame");
503 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
504 "Cannot use SP to access the emergency spill slot in "
505 "functions with variable sized frame objects");
506 }
507 #endif // NDEBUG
508
509 // Special handling of dbg_value instructions.
510 if (MI.isDebugValue()) {
511 MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
512 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
513 return;
514 }
515
516 // Modify MI as necessary to handle as much of 'Offset' as possible
517 assert(AFI->isThumbFunction() &&
518 "This eliminateFrameIndex only supports Thumb1!");
519 if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
520 return;
521
522 // If we get here, the immediate doesn't fit into the instruction. We folded
523 // as much as possible above, handle the rest, providing a register that is
524 // SP+LargeImm.
525 assert(Offset && "This code isn't needed if offset already handled!");
526
527 unsigned Opcode = MI.getOpcode();
528
529 // Remove predicate first.
530 int PIdx = MI.findFirstPredOperandIdx();
531 if (PIdx != -1)
532 removeOperands(MI, PIdx);
533
534 if (MI.mayLoad()) {
535 // Use the destination register to materialize sp + offset.
536 unsigned TmpReg = MI.getOperand(0).getReg();
537 bool UseRR = false;
538 if (Opcode == ARM::tLDRspi) {
539 if (FrameReg == ARM::SP)
540 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
541 Offset, false, TII, *this);
542 else {
543 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
544 UseRR = true;
545 }
546 } else {
547 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
548 *this);
549 }
550
551 MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
552 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
553 if (UseRR)
554 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
555 // register. The offset is already handled in the vreg value.
556 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
557 false);
558 } else if (MI.mayStore()) {
559 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
560 bool UseRR = false;
561
562 if (Opcode == ARM::tSTRspi) {
563 if (FrameReg == ARM::SP)
564 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
565 Offset, false, TII, *this);
566 else {
567 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
568 UseRR = true;
569 }
570 } else
571 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
572 *this);
573 MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
574 MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true);
575 if (UseRR)
576 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
577 // register. The offset is already handled in the vreg value.
578 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
579 false);
580 } else {
581 llvm_unreachable("Unexpected opcode!");
582 }
583
584 // Add predicate back if it's needed.
585 if (MI.isPredicable())
586 AddDefaultPred(MIB);
587 }
588