1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the Mips Disassembler.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "Mips.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
24
25 using namespace llvm;
26
27 #define DEBUG_TYPE "mips-disassembler"
28
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
30
31 namespace {
32
33 /// A disasembler class for Mips.
34 class MipsDisassemblerBase : public MCDisassembler {
35 public:
MipsDisassemblerBase(const MCSubtargetInfo & STI,MCContext & Ctx,bool IsBigEndian)36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
37 bool IsBigEndian)
38 : MCDisassembler(STI, Ctx),
39 IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
40 IsBigEndian(IsBigEndian) {}
41
~MipsDisassemblerBase()42 virtual ~MipsDisassemblerBase() {}
43
isGP64Bit() const44 bool isGP64Bit() const { return IsGP64Bit; }
45
46 private:
47 bool IsGP64Bit;
48 protected:
49 bool IsBigEndian;
50 };
51
52 /// A disasembler class for Mips32.
53 class MipsDisassembler : public MipsDisassemblerBase {
54 bool IsMicroMips;
55 public:
MipsDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx,bool bigEndian)56 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
57 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
58 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
59 }
60
hasMips3() const61 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
hasMips32() const62 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
hasMips32r6() const63 bool hasMips32r6() const {
64 return STI.getFeatureBits() & Mips::FeatureMips32r6;
65 }
66
isGP64() const67 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
68
hasCOP3() const69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
72 }
73
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
76 raw_ostream &VStream,
77 raw_ostream &CStream) const override;
78 };
79
80 /// A disasembler class for Mips64.
81 class Mips64Disassembler : public MipsDisassemblerBase {
82 public:
Mips64Disassembler(const MCSubtargetInfo & STI,MCContext & Ctx,bool bigEndian)83 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
84 bool bigEndian) :
85 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
86
87 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
88 ArrayRef<uint8_t> Bytes, uint64_t Address,
89 raw_ostream &VStream,
90 raw_ostream &CStream) const override;
91 };
92
93 } // end anonymous namespace
94
95 // Forward declare these because the autogenerated code will reference them.
96 // Definitions are further down.
97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
98 unsigned RegNo,
99 uint64_t Address,
100 const void *Decoder);
101
102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
103 unsigned RegNo,
104 uint64_t Address,
105 const void *Decoder);
106
107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
108 unsigned RegNo,
109 uint64_t Address,
110 const void *Decoder);
111
112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
113 unsigned RegNo,
114 uint64_t Address,
115 const void *Decoder);
116
117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
118 unsigned RegNo,
119 uint64_t Address,
120 const void *Decoder);
121
122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
123 unsigned Insn,
124 uint64_t Address,
125 const void *Decoder);
126
127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
128 unsigned RegNo,
129 uint64_t Address,
130 const void *Decoder);
131
132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
133 unsigned RegNo,
134 uint64_t Address,
135 const void *Decoder);
136
137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
138 unsigned RegNo,
139 uint64_t Address,
140 const void *Decoder);
141
142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
143 unsigned RegNo,
144 uint64_t Address,
145 const void *Decoder);
146
147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
148 unsigned RegNo,
149 uint64_t Address,
150 const void *Decoder);
151
152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
153 uint64_t Address,
154 const void *Decoder);
155
156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
157 unsigned Insn,
158 uint64_t Address,
159 const void *Decoder);
160
161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
162 unsigned RegNo,
163 uint64_t Address,
164 const void *Decoder);
165
166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
167 unsigned RegNo,
168 uint64_t Address,
169 const void *Decoder);
170
171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
172 unsigned RegNo,
173 uint64_t Address,
174 const void *Decoder);
175
176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
177 unsigned RegNo,
178 uint64_t Address,
179 const void *Decoder);
180
181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
182 unsigned RegNo,
183 uint64_t Address,
184 const void *Decoder);
185
186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
187 unsigned RegNo,
188 uint64_t Address,
189 const void *Decoder);
190
191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
192 unsigned RegNo,
193 uint64_t Address,
194 const void *Decoder);
195
196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
197 unsigned RegNo,
198 uint64_t Address,
199 const void *Decoder);
200
201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
202 unsigned RegNo,
203 uint64_t Address,
204 const void *Decoder);
205
206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
207 unsigned RegNo,
208 uint64_t Address,
209 const void *Decoder);
210
211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
212 unsigned Offset,
213 uint64_t Address,
214 const void *Decoder);
215
216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
217 unsigned Insn,
218 uint64_t Address,
219 const void *Decoder);
220
221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
222 unsigned Offset,
223 uint64_t Address,
224 const void *Decoder);
225
226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
227 unsigned Offset,
228 uint64_t Address,
229 const void *Decoder);
230
231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
232 // shifted left by 1 bit.
233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
234 unsigned Offset,
235 uint64_t Address,
236 const void *Decoder);
237
238 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
239 // shifted left by 1 bit.
240 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
241 unsigned Offset,
242 uint64_t Address,
243 const void *Decoder);
244
245 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
246 // shifted left by 1 bit.
247 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
248 unsigned Insn,
249 uint64_t Address,
250 const void *Decoder);
251
252 static DecodeStatus DecodeMem(MCInst &Inst,
253 unsigned Insn,
254 uint64_t Address,
255 const void *Decoder);
256
257 static DecodeStatus DecodeCacheOp(MCInst &Inst,
258 unsigned Insn,
259 uint64_t Address,
260 const void *Decoder);
261
262 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
263 unsigned Insn,
264 uint64_t Address,
265 const void *Decoder);
266
267 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
268 unsigned Insn,
269 uint64_t Address,
270 const void *Decoder);
271
272 static DecodeStatus DecodeSyncI(MCInst &Inst,
273 unsigned Insn,
274 uint64_t Address,
275 const void *Decoder);
276
277 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
278 uint64_t Address, const void *Decoder);
279
280 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
281 unsigned Insn,
282 uint64_t Address,
283 const void *Decoder);
284
285 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
286 unsigned Insn,
287 uint64_t Address,
288 const void *Decoder);
289
290 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
291 unsigned Insn,
292 uint64_t Address,
293 const void *Decoder);
294
295 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
296 unsigned Insn,
297 uint64_t Address,
298 const void *Decoder);
299
300 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
301 uint64_t Address,
302 const void *Decoder);
303
304 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
305 uint64_t Address,
306 const void *Decoder);
307
308 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
309 uint64_t Address,
310 const void *Decoder);
311
312 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
313 uint64_t Address,
314 const void *Decoder);
315
316 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
317 unsigned Insn,
318 uint64_t Address,
319 const void *Decoder);
320
321 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
322 unsigned Value,
323 uint64_t Address,
324 const void *Decoder);
325
326 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
327 unsigned Value,
328 uint64_t Address,
329 const void *Decoder);
330
331 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
332 unsigned Value,
333 uint64_t Address,
334 const void *Decoder);
335
336 static DecodeStatus DecodeSimm4(MCInst &Inst,
337 unsigned Value,
338 uint64_t Address,
339 const void *Decoder);
340
341 static DecodeStatus DecodeSimm16(MCInst &Inst,
342 unsigned Insn,
343 uint64_t Address,
344 const void *Decoder);
345
346 // Decode the immediate field of an LSA instruction which
347 // is off by one.
348 static DecodeStatus DecodeLSAImm(MCInst &Inst,
349 unsigned Insn,
350 uint64_t Address,
351 const void *Decoder);
352
353 static DecodeStatus DecodeInsSize(MCInst &Inst,
354 unsigned Insn,
355 uint64_t Address,
356 const void *Decoder);
357
358 static DecodeStatus DecodeExtSize(MCInst &Inst,
359 unsigned Insn,
360 uint64_t Address,
361 const void *Decoder);
362
363 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
364 uint64_t Address, const void *Decoder);
365
366 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
367 uint64_t Address, const void *Decoder);
368
369 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
370 uint64_t Address, const void *Decoder);
371
372 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
373 uint64_t Address, const void *Decoder);
374
375 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
376 uint64_t Address, const void *Decoder);
377
378 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
379 /// handle.
380 template <typename InsnType>
381 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
382 const void *Decoder);
383
384 template <typename InsnType>
385 static DecodeStatus
386 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
387 const void *Decoder);
388
389 template <typename InsnType>
390 static DecodeStatus
391 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
392 const void *Decoder);
393
394 template <typename InsnType>
395 static DecodeStatus
396 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
397 const void *Decoder);
398
399 template <typename InsnType>
400 static DecodeStatus
401 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
402 const void *Decoder);
403
404 template <typename InsnType>
405 static DecodeStatus
406 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
407 const void *Decoder);
408
409 template <typename InsnType>
410 static DecodeStatus
411 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
412 const void *Decoder);
413
414 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
415 uint64_t Address,
416 const void *Decoder);
417
418 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
419 uint64_t Address,
420 const void *Decoder);
421
422 namespace llvm {
423 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
424 TheMips64elTarget;
425 }
426
createMipsDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)427 static MCDisassembler *createMipsDisassembler(
428 const Target &T,
429 const MCSubtargetInfo &STI,
430 MCContext &Ctx) {
431 return new MipsDisassembler(STI, Ctx, true);
432 }
433
createMipselDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)434 static MCDisassembler *createMipselDisassembler(
435 const Target &T,
436 const MCSubtargetInfo &STI,
437 MCContext &Ctx) {
438 return new MipsDisassembler(STI, Ctx, false);
439 }
440
createMips64Disassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)441 static MCDisassembler *createMips64Disassembler(
442 const Target &T,
443 const MCSubtargetInfo &STI,
444 MCContext &Ctx) {
445 return new Mips64Disassembler(STI, Ctx, true);
446 }
447
createMips64elDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)448 static MCDisassembler *createMips64elDisassembler(
449 const Target &T,
450 const MCSubtargetInfo &STI,
451 MCContext &Ctx) {
452 return new Mips64Disassembler(STI, Ctx, false);
453 }
454
LLVMInitializeMipsDisassembler()455 extern "C" void LLVMInitializeMipsDisassembler() {
456 // Register the disassembler.
457 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
458 createMipsDisassembler);
459 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
460 createMipselDisassembler);
461 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
462 createMips64Disassembler);
463 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
464 createMips64elDisassembler);
465 }
466
467 #include "MipsGenDisassemblerTables.inc"
468
getReg(const void * D,unsigned RC,unsigned RegNo)469 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
470 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
471 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
472 return *(RegInfo->getRegClass(RC).begin() + RegNo);
473 }
474
475 template <typename InsnType>
DecodeINSVE_DF(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)476 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
477 const void *Decoder) {
478 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
479 // The size of the n field depends on the element size
480 // The register class also depends on this.
481 InsnType tmp = fieldFromInstruction(insn, 17, 5);
482 unsigned NSize = 0;
483 DecodeFN RegDecoder = nullptr;
484 if ((tmp & 0x18) == 0x00) { // INSVE_B
485 NSize = 4;
486 RegDecoder = DecodeMSA128BRegisterClass;
487 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
488 NSize = 3;
489 RegDecoder = DecodeMSA128HRegisterClass;
490 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
491 NSize = 2;
492 RegDecoder = DecodeMSA128WRegisterClass;
493 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
494 NSize = 1;
495 RegDecoder = DecodeMSA128DRegisterClass;
496 } else
497 llvm_unreachable("Invalid encoding");
498
499 assert(NSize != 0 && RegDecoder != nullptr);
500
501 // $wd
502 tmp = fieldFromInstruction(insn, 6, 5);
503 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
504 return MCDisassembler::Fail;
505 // $wd_in
506 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
507 return MCDisassembler::Fail;
508 // $n
509 tmp = fieldFromInstruction(insn, 16, NSize);
510 MI.addOperand(MCOperand::CreateImm(tmp));
511 // $ws
512 tmp = fieldFromInstruction(insn, 11, 5);
513 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
514 return MCDisassembler::Fail;
515 // $n2
516 MI.addOperand(MCOperand::CreateImm(0));
517
518 return MCDisassembler::Success;
519 }
520
521 template <typename InsnType>
DecodeAddiGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)522 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
523 uint64_t Address,
524 const void *Decoder) {
525 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
526 // (otherwise we would have matched the ADDI instruction from the earlier
527 // ISA's instead).
528 //
529 // We have:
530 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
531 // BOVC if rs >= rt
532 // BEQZALC if rs == 0 && rt != 0
533 // BEQC if rs < rt && rs != 0
534
535 InsnType Rs = fieldFromInstruction(insn, 21, 5);
536 InsnType Rt = fieldFromInstruction(insn, 16, 5);
537 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
538 bool HasRs = false;
539
540 if (Rs >= Rt) {
541 MI.setOpcode(Mips::BOVC);
542 HasRs = true;
543 } else if (Rs != 0 && Rs < Rt) {
544 MI.setOpcode(Mips::BEQC);
545 HasRs = true;
546 } else
547 MI.setOpcode(Mips::BEQZALC);
548
549 if (HasRs)
550 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
551 Rs)));
552
553 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
554 Rt)));
555 MI.addOperand(MCOperand::CreateImm(Imm));
556
557 return MCDisassembler::Success;
558 }
559
560 template <typename InsnType>
DecodeDaddiGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)561 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
562 uint64_t Address,
563 const void *Decoder) {
564 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
565 // (otherwise we would have matched the ADDI instruction from the earlier
566 // ISA's instead).
567 //
568 // We have:
569 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
570 // BNVC if rs >= rt
571 // BNEZALC if rs == 0 && rt != 0
572 // BNEC if rs < rt && rs != 0
573
574 InsnType Rs = fieldFromInstruction(insn, 21, 5);
575 InsnType Rt = fieldFromInstruction(insn, 16, 5);
576 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
577 bool HasRs = false;
578
579 if (Rs >= Rt) {
580 MI.setOpcode(Mips::BNVC);
581 HasRs = true;
582 } else if (Rs != 0 && Rs < Rt) {
583 MI.setOpcode(Mips::BNEC);
584 HasRs = true;
585 } else
586 MI.setOpcode(Mips::BNEZALC);
587
588 if (HasRs)
589 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
590 Rs)));
591
592 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
593 Rt)));
594 MI.addOperand(MCOperand::CreateImm(Imm));
595
596 return MCDisassembler::Success;
597 }
598
599 template <typename InsnType>
DecodeBlezlGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)600 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
601 uint64_t Address,
602 const void *Decoder) {
603 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
604 // (otherwise we would have matched the BLEZL instruction from the earlier
605 // ISA's instead).
606 //
607 // We have:
608 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
609 // Invalid if rs == 0
610 // BLEZC if rs == 0 && rt != 0
611 // BGEZC if rs == rt && rt != 0
612 // BGEC if rs != rt && rs != 0 && rt != 0
613
614 InsnType Rs = fieldFromInstruction(insn, 21, 5);
615 InsnType Rt = fieldFromInstruction(insn, 16, 5);
616 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
617 bool HasRs = false;
618
619 if (Rt == 0)
620 return MCDisassembler::Fail;
621 else if (Rs == 0)
622 MI.setOpcode(Mips::BLEZC);
623 else if (Rs == Rt)
624 MI.setOpcode(Mips::BGEZC);
625 else {
626 HasRs = true;
627 MI.setOpcode(Mips::BGEC);
628 }
629
630 if (HasRs)
631 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
632 Rs)));
633
634 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
635 Rt)));
636
637 MI.addOperand(MCOperand::CreateImm(Imm));
638
639 return MCDisassembler::Success;
640 }
641
642 template <typename InsnType>
DecodeBgtzlGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)643 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
644 uint64_t Address,
645 const void *Decoder) {
646 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
647 // (otherwise we would have matched the BGTZL instruction from the earlier
648 // ISA's instead).
649 //
650 // We have:
651 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
652 // Invalid if rs == 0
653 // BGTZC if rs == 0 && rt != 0
654 // BLTZC if rs == rt && rt != 0
655 // BLTC if rs != rt && rs != 0 && rt != 0
656
657 bool HasRs = false;
658
659 InsnType Rs = fieldFromInstruction(insn, 21, 5);
660 InsnType Rt = fieldFromInstruction(insn, 16, 5);
661 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
662
663 if (Rt == 0)
664 return MCDisassembler::Fail;
665 else if (Rs == 0)
666 MI.setOpcode(Mips::BGTZC);
667 else if (Rs == Rt)
668 MI.setOpcode(Mips::BLTZC);
669 else {
670 MI.setOpcode(Mips::BLTC);
671 HasRs = true;
672 }
673
674 if (HasRs)
675 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
676 Rs)));
677
678 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
679 Rt)));
680
681 MI.addOperand(MCOperand::CreateImm(Imm));
682
683 return MCDisassembler::Success;
684 }
685
686 template <typename InsnType>
DecodeBgtzGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)687 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
688 uint64_t Address,
689 const void *Decoder) {
690 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
691 // (otherwise we would have matched the BGTZ instruction from the earlier
692 // ISA's instead).
693 //
694 // We have:
695 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
696 // BGTZ if rt == 0
697 // BGTZALC if rs == 0 && rt != 0
698 // BLTZALC if rs != 0 && rs == rt
699 // BLTUC if rs != 0 && rs != rt
700
701 InsnType Rs = fieldFromInstruction(insn, 21, 5);
702 InsnType Rt = fieldFromInstruction(insn, 16, 5);
703 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
704 bool HasRs = false;
705 bool HasRt = false;
706
707 if (Rt == 0) {
708 MI.setOpcode(Mips::BGTZ);
709 HasRs = true;
710 } else if (Rs == 0) {
711 MI.setOpcode(Mips::BGTZALC);
712 HasRt = true;
713 } else if (Rs == Rt) {
714 MI.setOpcode(Mips::BLTZALC);
715 HasRs = true;
716 } else {
717 MI.setOpcode(Mips::BLTUC);
718 HasRs = true;
719 HasRt = true;
720 }
721
722 if (HasRs)
723 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
724 Rs)));
725
726 if (HasRt)
727 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
728 Rt)));
729
730 MI.addOperand(MCOperand::CreateImm(Imm));
731
732 return MCDisassembler::Success;
733 }
734
735 template <typename InsnType>
DecodeBlezGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)736 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
737 uint64_t Address,
738 const void *Decoder) {
739 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
740 // (otherwise we would have matched the BLEZL instruction from the earlier
741 // ISA's instead).
742 //
743 // We have:
744 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
745 // Invalid if rs == 0
746 // BLEZALC if rs == 0 && rt != 0
747 // BGEZALC if rs == rt && rt != 0
748 // BGEUC if rs != rt && rs != 0 && rt != 0
749
750 InsnType Rs = fieldFromInstruction(insn, 21, 5);
751 InsnType Rt = fieldFromInstruction(insn, 16, 5);
752 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
753 bool HasRs = false;
754
755 if (Rt == 0)
756 return MCDisassembler::Fail;
757 else if (Rs == 0)
758 MI.setOpcode(Mips::BLEZALC);
759 else if (Rs == Rt)
760 MI.setOpcode(Mips::BGEZALC);
761 else {
762 HasRs = true;
763 MI.setOpcode(Mips::BGEUC);
764 }
765
766 if (HasRs)
767 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
768 Rs)));
769 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
770 Rt)));
771
772 MI.addOperand(MCOperand::CreateImm(Imm));
773
774 return MCDisassembler::Success;
775 }
776
777 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
778 /// according to the given endianess.
readInstruction16(ArrayRef<uint8_t> Bytes,uint64_t Address,uint64_t & Size,uint32_t & Insn,bool IsBigEndian)779 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
780 uint64_t &Size, uint32_t &Insn,
781 bool IsBigEndian) {
782 // We want to read exactly 2 Bytes of data.
783 if (Bytes.size() < 2) {
784 Size = 0;
785 return MCDisassembler::Fail;
786 }
787
788 if (IsBigEndian) {
789 Insn = (Bytes[0] << 8) | Bytes[1];
790 } else {
791 Insn = (Bytes[1] << 8) | Bytes[0];
792 }
793
794 return MCDisassembler::Success;
795 }
796
797 /// Read four bytes from the ArrayRef and return 32 bit word sorted
798 /// according to the given endianess
readInstruction32(ArrayRef<uint8_t> Bytes,uint64_t Address,uint64_t & Size,uint32_t & Insn,bool IsBigEndian,bool IsMicroMips)799 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
800 uint64_t &Size, uint32_t &Insn,
801 bool IsBigEndian, bool IsMicroMips) {
802 // We want to read exactly 4 Bytes of data.
803 if (Bytes.size() < 4) {
804 Size = 0;
805 return MCDisassembler::Fail;
806 }
807
808 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
809 // always precede the low 16 bits in the instruction stream (that is, they
810 // are placed at lower addresses in the instruction stream).
811 //
812 // microMIPS byte ordering:
813 // Big-endian: 0 | 1 | 2 | 3
814 // Little-endian: 1 | 0 | 3 | 2
815
816 if (IsBigEndian) {
817 // Encoded as a big-endian 32-bit word in the stream.
818 Insn =
819 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
820 } else {
821 if (IsMicroMips) {
822 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
823 (Bytes[1] << 24);
824 } else {
825 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
826 (Bytes[3] << 24);
827 }
828 }
829
830 return MCDisassembler::Success;
831 }
832
getInstruction(MCInst & Instr,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & VStream,raw_ostream & CStream) const833 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
834 ArrayRef<uint8_t> Bytes,
835 uint64_t Address,
836 raw_ostream &VStream,
837 raw_ostream &CStream) const {
838 uint32_t Insn;
839 DecodeStatus Result;
840
841 if (IsMicroMips) {
842 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
843
844 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
845 // Calling the auto-generated decoder function.
846 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
847 this, STI);
848 if (Result != MCDisassembler::Fail) {
849 Size = 2;
850 return Result;
851 }
852
853 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
854 if (Result == MCDisassembler::Fail)
855 return MCDisassembler::Fail;
856
857 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
858 // Calling the auto-generated decoder function.
859 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
860 this, STI);
861 if (Result != MCDisassembler::Fail) {
862 Size = 4;
863 return Result;
864 }
865 return MCDisassembler::Fail;
866 }
867
868 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
869 if (Result == MCDisassembler::Fail)
870 return MCDisassembler::Fail;
871
872 if (hasCOP3()) {
873 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
874 Result =
875 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
876 if (Result != MCDisassembler::Fail) {
877 Size = 4;
878 return Result;
879 }
880 }
881
882 if (hasMips32r6() && isGP64()) {
883 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
884 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
885 Address, this, STI);
886 if (Result != MCDisassembler::Fail) {
887 Size = 4;
888 return Result;
889 }
890 }
891
892 if (hasMips32r6()) {
893 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
894 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
895 Address, this, STI);
896 if (Result != MCDisassembler::Fail) {
897 Size = 4;
898 return Result;
899 }
900 }
901
902 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
903 // Calling the auto-generated decoder function.
904 Result =
905 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
906 if (Result != MCDisassembler::Fail) {
907 Size = 4;
908 return Result;
909 }
910
911 return MCDisassembler::Fail;
912 }
913
getInstruction(MCInst & Instr,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & VStream,raw_ostream & CStream) const914 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
915 ArrayRef<uint8_t> Bytes,
916 uint64_t Address,
917 raw_ostream &VStream,
918 raw_ostream &CStream) const {
919 uint32_t Insn;
920
921 DecodeStatus Result =
922 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
923 if (Result == MCDisassembler::Fail)
924 return MCDisassembler::Fail;
925
926 // Calling the auto-generated decoder function.
927 Result =
928 decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
929 if (Result != MCDisassembler::Fail) {
930 Size = 4;
931 return Result;
932 }
933 // If we fail to decode in Mips64 decoder space we can try in Mips32
934 Result =
935 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
936 if (Result != MCDisassembler::Fail) {
937 Size = 4;
938 return Result;
939 }
940
941 return MCDisassembler::Fail;
942 }
943
DecodeCPU16RegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)944 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
945 unsigned RegNo,
946 uint64_t Address,
947 const void *Decoder) {
948
949 return MCDisassembler::Fail;
950
951 }
952
DecodeGPR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)953 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
954 unsigned RegNo,
955 uint64_t Address,
956 const void *Decoder) {
957
958 if (RegNo > 31)
959 return MCDisassembler::Fail;
960
961 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
962 Inst.addOperand(MCOperand::CreateReg(Reg));
963 return MCDisassembler::Success;
964 }
965
DecodeGPRMM16RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)966 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
967 unsigned RegNo,
968 uint64_t Address,
969 const void *Decoder) {
970 if (RegNo > 7)
971 return MCDisassembler::Fail;
972 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
973 Inst.addOperand(MCOperand::CreateReg(Reg));
974 return MCDisassembler::Success;
975 }
976
DecodeGPRMM16ZeroRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)977 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
978 unsigned RegNo,
979 uint64_t Address,
980 const void *Decoder) {
981 if (RegNo > 7)
982 return MCDisassembler::Fail;
983 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
984 Inst.addOperand(MCOperand::CreateReg(Reg));
985 return MCDisassembler::Success;
986 }
987
DecodeGPR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)988 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
989 unsigned RegNo,
990 uint64_t Address,
991 const void *Decoder) {
992 if (RegNo > 31)
993 return MCDisassembler::Fail;
994 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
995 Inst.addOperand(MCOperand::CreateReg(Reg));
996 return MCDisassembler::Success;
997 }
998
DecodePtrRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)999 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1000 unsigned RegNo,
1001 uint64_t Address,
1002 const void *Decoder) {
1003 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
1004 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1005
1006 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1007 }
1008
DecodeDSPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1009 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1010 unsigned RegNo,
1011 uint64_t Address,
1012 const void *Decoder) {
1013 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1014 }
1015
DecodeFGR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1016 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1017 unsigned RegNo,
1018 uint64_t Address,
1019 const void *Decoder) {
1020 if (RegNo > 31)
1021 return MCDisassembler::Fail;
1022
1023 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1024 Inst.addOperand(MCOperand::CreateReg(Reg));
1025 return MCDisassembler::Success;
1026 }
1027
DecodeFGR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1028 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1029 unsigned RegNo,
1030 uint64_t Address,
1031 const void *Decoder) {
1032 if (RegNo > 31)
1033 return MCDisassembler::Fail;
1034
1035 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1036 Inst.addOperand(MCOperand::CreateReg(Reg));
1037 return MCDisassembler::Success;
1038 }
1039
DecodeCCRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1040 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1041 unsigned RegNo,
1042 uint64_t Address,
1043 const void *Decoder) {
1044 if (RegNo > 31)
1045 return MCDisassembler::Fail;
1046 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1047 Inst.addOperand(MCOperand::CreateReg(Reg));
1048 return MCDisassembler::Success;
1049 }
1050
DecodeFCCRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1051 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1052 unsigned RegNo,
1053 uint64_t Address,
1054 const void *Decoder) {
1055 if (RegNo > 7)
1056 return MCDisassembler::Fail;
1057 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1058 Inst.addOperand(MCOperand::CreateReg(Reg));
1059 return MCDisassembler::Success;
1060 }
1061
DecodeFGRCCRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1062 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1063 uint64_t Address,
1064 const void *Decoder) {
1065 if (RegNo > 31)
1066 return MCDisassembler::Fail;
1067
1068 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1069 Inst.addOperand(MCOperand::CreateReg(Reg));
1070 return MCDisassembler::Success;
1071 }
1072
DecodeMem(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1073 static DecodeStatus DecodeMem(MCInst &Inst,
1074 unsigned Insn,
1075 uint64_t Address,
1076 const void *Decoder) {
1077 int Offset = SignExtend32<16>(Insn & 0xffff);
1078 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1079 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1080
1081 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1082 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1083
1084 if(Inst.getOpcode() == Mips::SC ||
1085 Inst.getOpcode() == Mips::SCD){
1086 Inst.addOperand(MCOperand::CreateReg(Reg));
1087 }
1088
1089 Inst.addOperand(MCOperand::CreateReg(Reg));
1090 Inst.addOperand(MCOperand::CreateReg(Base));
1091 Inst.addOperand(MCOperand::CreateImm(Offset));
1092
1093 return MCDisassembler::Success;
1094 }
1095
DecodeCacheOp(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1096 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1097 unsigned Insn,
1098 uint64_t Address,
1099 const void *Decoder) {
1100 int Offset = SignExtend32<16>(Insn & 0xffff);
1101 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1102 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1103
1104 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1105
1106 Inst.addOperand(MCOperand::CreateReg(Base));
1107 Inst.addOperand(MCOperand::CreateImm(Offset));
1108 Inst.addOperand(MCOperand::CreateImm(Hint));
1109
1110 return MCDisassembler::Success;
1111 }
1112
DecodeCacheOpMM(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1113 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1114 unsigned Insn,
1115 uint64_t Address,
1116 const void *Decoder) {
1117 int Offset = SignExtend32<12>(Insn & 0xfff);
1118 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1119 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1120
1121 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1122
1123 Inst.addOperand(MCOperand::CreateReg(Base));
1124 Inst.addOperand(MCOperand::CreateImm(Offset));
1125 Inst.addOperand(MCOperand::CreateImm(Hint));
1126
1127 return MCDisassembler::Success;
1128 }
1129
DecodeCacheOpR6(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1130 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
1131 unsigned Insn,
1132 uint64_t Address,
1133 const void *Decoder) {
1134 int Offset = fieldFromInstruction(Insn, 7, 9);
1135 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1136 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1137
1138 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1139
1140 Inst.addOperand(MCOperand::CreateReg(Base));
1141 Inst.addOperand(MCOperand::CreateImm(Offset));
1142 Inst.addOperand(MCOperand::CreateImm(Hint));
1143
1144 return MCDisassembler::Success;
1145 }
1146
DecodeSyncI(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1147 static DecodeStatus DecodeSyncI(MCInst &Inst,
1148 unsigned Insn,
1149 uint64_t Address,
1150 const void *Decoder) {
1151 int Offset = SignExtend32<16>(Insn & 0xffff);
1152 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1153
1154 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1155
1156 Inst.addOperand(MCOperand::CreateReg(Base));
1157 Inst.addOperand(MCOperand::CreateImm(Offset));
1158
1159 return MCDisassembler::Success;
1160 }
1161
DecodeMSA128Mem(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1162 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1163 uint64_t Address, const void *Decoder) {
1164 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1165 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1166 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1167
1168 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1169 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1170
1171 Inst.addOperand(MCOperand::CreateReg(Reg));
1172 Inst.addOperand(MCOperand::CreateReg(Base));
1173
1174 // The immediate field of an LD/ST instruction is scaled which means it must
1175 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1176 // data format.
1177 // .b - 1 byte
1178 // .h - 2 bytes
1179 // .w - 4 bytes
1180 // .d - 8 bytes
1181 switch(Inst.getOpcode())
1182 {
1183 default:
1184 assert (0 && "Unexpected instruction");
1185 return MCDisassembler::Fail;
1186 break;
1187 case Mips::LD_B:
1188 case Mips::ST_B:
1189 Inst.addOperand(MCOperand::CreateImm(Offset));
1190 break;
1191 case Mips::LD_H:
1192 case Mips::ST_H:
1193 Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1194 break;
1195 case Mips::LD_W:
1196 case Mips::ST_W:
1197 Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1198 break;
1199 case Mips::LD_D:
1200 case Mips::ST_D:
1201 Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1202 break;
1203 }
1204
1205 return MCDisassembler::Success;
1206 }
1207
DecodeMemMMImm4(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1208 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1209 unsigned Insn,
1210 uint64_t Address,
1211 const void *Decoder) {
1212 unsigned Offset = Insn & 0xf;
1213 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1214 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1215
1216 switch (Inst.getOpcode()) {
1217 case Mips::LBU16_MM:
1218 case Mips::LHU16_MM:
1219 case Mips::LW16_MM:
1220 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1221 == MCDisassembler::Fail)
1222 return MCDisassembler::Fail;
1223 break;
1224 case Mips::SB16_MM:
1225 case Mips::SH16_MM:
1226 case Mips::SW16_MM:
1227 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1228 == MCDisassembler::Fail)
1229 return MCDisassembler::Fail;
1230 break;
1231 }
1232
1233 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1234 == MCDisassembler::Fail)
1235 return MCDisassembler::Fail;
1236
1237 switch (Inst.getOpcode()) {
1238 case Mips::LBU16_MM:
1239 if (Offset == 0xf)
1240 Inst.addOperand(MCOperand::CreateImm(-1));
1241 else
1242 Inst.addOperand(MCOperand::CreateImm(Offset));
1243 break;
1244 case Mips::SB16_MM:
1245 Inst.addOperand(MCOperand::CreateImm(Offset));
1246 break;
1247 case Mips::LHU16_MM:
1248 case Mips::SH16_MM:
1249 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1250 break;
1251 case Mips::LW16_MM:
1252 case Mips::SW16_MM:
1253 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1254 break;
1255 }
1256
1257 return MCDisassembler::Success;
1258 }
1259
DecodeMemMMSPImm5Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1260 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1261 unsigned Insn,
1262 uint64_t Address,
1263 const void *Decoder) {
1264 unsigned Offset = Insn & 0x1F;
1265 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1266
1267 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1268
1269 Inst.addOperand(MCOperand::CreateReg(Reg));
1270 Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1271 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1272
1273 return MCDisassembler::Success;
1274 }
1275
DecodeMemMMImm12(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1276 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1277 unsigned Insn,
1278 uint64_t Address,
1279 const void *Decoder) {
1280 int Offset = SignExtend32<12>(Insn & 0x0fff);
1281 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1282 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1283
1284 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1285 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1286
1287 switch (Inst.getOpcode()) {
1288 case Mips::SWM32_MM:
1289 case Mips::LWM32_MM:
1290 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1291 == MCDisassembler::Fail)
1292 return MCDisassembler::Fail;
1293 Inst.addOperand(MCOperand::CreateReg(Base));
1294 Inst.addOperand(MCOperand::CreateImm(Offset));
1295 break;
1296 case Mips::SC_MM:
1297 Inst.addOperand(MCOperand::CreateReg(Reg));
1298 // fallthrough
1299 default:
1300 Inst.addOperand(MCOperand::CreateReg(Reg));
1301 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1302 Inst.addOperand(MCOperand::CreateReg(Reg+1));
1303
1304 Inst.addOperand(MCOperand::CreateReg(Base));
1305 Inst.addOperand(MCOperand::CreateImm(Offset));
1306 }
1307
1308 return MCDisassembler::Success;
1309 }
1310
DecodeMemMMImm16(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1311 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1312 unsigned Insn,
1313 uint64_t Address,
1314 const void *Decoder) {
1315 int Offset = SignExtend32<16>(Insn & 0xffff);
1316 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1317 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1318
1319 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1320 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1321
1322 Inst.addOperand(MCOperand::CreateReg(Reg));
1323 Inst.addOperand(MCOperand::CreateReg(Base));
1324 Inst.addOperand(MCOperand::CreateImm(Offset));
1325
1326 return MCDisassembler::Success;
1327 }
1328
DecodeFMem(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1329 static DecodeStatus DecodeFMem(MCInst &Inst,
1330 unsigned Insn,
1331 uint64_t Address,
1332 const void *Decoder) {
1333 int Offset = SignExtend32<16>(Insn & 0xffff);
1334 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1335 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1336
1337 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1338 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1339
1340 Inst.addOperand(MCOperand::CreateReg(Reg));
1341 Inst.addOperand(MCOperand::CreateReg(Base));
1342 Inst.addOperand(MCOperand::CreateImm(Offset));
1343
1344 return MCDisassembler::Success;
1345 }
1346
DecodeFMem2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1347 static DecodeStatus DecodeFMem2(MCInst &Inst,
1348 unsigned Insn,
1349 uint64_t Address,
1350 const void *Decoder) {
1351 int Offset = SignExtend32<16>(Insn & 0xffff);
1352 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1353 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1354
1355 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1356 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1357
1358 Inst.addOperand(MCOperand::CreateReg(Reg));
1359 Inst.addOperand(MCOperand::CreateReg(Base));
1360 Inst.addOperand(MCOperand::CreateImm(Offset));
1361
1362 return MCDisassembler::Success;
1363 }
1364
DecodeFMem3(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1365 static DecodeStatus DecodeFMem3(MCInst &Inst,
1366 unsigned Insn,
1367 uint64_t Address,
1368 const void *Decoder) {
1369 int Offset = SignExtend32<16>(Insn & 0xffff);
1370 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1371 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1372
1373 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1374 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1375
1376 Inst.addOperand(MCOperand::CreateReg(Reg));
1377 Inst.addOperand(MCOperand::CreateReg(Base));
1378 Inst.addOperand(MCOperand::CreateImm(Offset));
1379
1380 return MCDisassembler::Success;
1381 }
1382
DecodeFMemCop2R6(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1383 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1384 unsigned Insn,
1385 uint64_t Address,
1386 const void *Decoder) {
1387 int Offset = SignExtend32<11>(Insn & 0x07ff);
1388 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1389 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1390
1391 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1392 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1393
1394 Inst.addOperand(MCOperand::CreateReg(Reg));
1395 Inst.addOperand(MCOperand::CreateReg(Base));
1396 Inst.addOperand(MCOperand::CreateImm(Offset));
1397
1398 return MCDisassembler::Success;
1399 }
DecodeSpecial3LlSc(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1400 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1401 unsigned Insn,
1402 uint64_t Address,
1403 const void *Decoder) {
1404 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1405 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1406 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1407
1408 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1409 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1410
1411 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1412 Inst.addOperand(MCOperand::CreateReg(Rt));
1413 }
1414
1415 Inst.addOperand(MCOperand::CreateReg(Rt));
1416 Inst.addOperand(MCOperand::CreateReg(Base));
1417 Inst.addOperand(MCOperand::CreateImm(Offset));
1418
1419 return MCDisassembler::Success;
1420 }
1421
DecodeHWRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1422 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1423 unsigned RegNo,
1424 uint64_t Address,
1425 const void *Decoder) {
1426 // Currently only hardware register 29 is supported.
1427 if (RegNo != 29)
1428 return MCDisassembler::Fail;
1429 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1430 return MCDisassembler::Success;
1431 }
1432
DecodeAFGR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1433 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1434 unsigned RegNo,
1435 uint64_t Address,
1436 const void *Decoder) {
1437 if (RegNo > 30 || RegNo %2)
1438 return MCDisassembler::Fail;
1439
1440 ;
1441 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1442 Inst.addOperand(MCOperand::CreateReg(Reg));
1443 return MCDisassembler::Success;
1444 }
1445
DecodeACC64DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1446 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1447 unsigned RegNo,
1448 uint64_t Address,
1449 const void *Decoder) {
1450 if (RegNo >= 4)
1451 return MCDisassembler::Fail;
1452
1453 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1454 Inst.addOperand(MCOperand::CreateReg(Reg));
1455 return MCDisassembler::Success;
1456 }
1457
DecodeHI32DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1458 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1459 unsigned RegNo,
1460 uint64_t Address,
1461 const void *Decoder) {
1462 if (RegNo >= 4)
1463 return MCDisassembler::Fail;
1464
1465 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1466 Inst.addOperand(MCOperand::CreateReg(Reg));
1467 return MCDisassembler::Success;
1468 }
1469
DecodeLO32DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1470 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1471 unsigned RegNo,
1472 uint64_t Address,
1473 const void *Decoder) {
1474 if (RegNo >= 4)
1475 return MCDisassembler::Fail;
1476
1477 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1478 Inst.addOperand(MCOperand::CreateReg(Reg));
1479 return MCDisassembler::Success;
1480 }
1481
DecodeMSA128BRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1482 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1483 unsigned RegNo,
1484 uint64_t Address,
1485 const void *Decoder) {
1486 if (RegNo > 31)
1487 return MCDisassembler::Fail;
1488
1489 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1490 Inst.addOperand(MCOperand::CreateReg(Reg));
1491 return MCDisassembler::Success;
1492 }
1493
DecodeMSA128HRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1494 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1495 unsigned RegNo,
1496 uint64_t Address,
1497 const void *Decoder) {
1498 if (RegNo > 31)
1499 return MCDisassembler::Fail;
1500
1501 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1502 Inst.addOperand(MCOperand::CreateReg(Reg));
1503 return MCDisassembler::Success;
1504 }
1505
DecodeMSA128WRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1506 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1507 unsigned RegNo,
1508 uint64_t Address,
1509 const void *Decoder) {
1510 if (RegNo > 31)
1511 return MCDisassembler::Fail;
1512
1513 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1514 Inst.addOperand(MCOperand::CreateReg(Reg));
1515 return MCDisassembler::Success;
1516 }
1517
DecodeMSA128DRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1518 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1519 unsigned RegNo,
1520 uint64_t Address,
1521 const void *Decoder) {
1522 if (RegNo > 31)
1523 return MCDisassembler::Fail;
1524
1525 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1526 Inst.addOperand(MCOperand::CreateReg(Reg));
1527 return MCDisassembler::Success;
1528 }
1529
DecodeMSACtrlRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1530 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1531 unsigned RegNo,
1532 uint64_t Address,
1533 const void *Decoder) {
1534 if (RegNo > 7)
1535 return MCDisassembler::Fail;
1536
1537 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1538 Inst.addOperand(MCOperand::CreateReg(Reg));
1539 return MCDisassembler::Success;
1540 }
1541
DecodeCOP2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1542 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1543 unsigned RegNo,
1544 uint64_t Address,
1545 const void *Decoder) {
1546 if (RegNo > 31)
1547 return MCDisassembler::Fail;
1548
1549 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1550 Inst.addOperand(MCOperand::CreateReg(Reg));
1551 return MCDisassembler::Success;
1552 }
1553
DecodeBranchTarget(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)1554 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1555 unsigned Offset,
1556 uint64_t Address,
1557 const void *Decoder) {
1558 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1559 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1560 return MCDisassembler::Success;
1561 }
1562
DecodeJumpTarget(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1563 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1564 unsigned Insn,
1565 uint64_t Address,
1566 const void *Decoder) {
1567
1568 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1569 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1570 return MCDisassembler::Success;
1571 }
1572
DecodeBranchTarget21(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)1573 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1574 unsigned Offset,
1575 uint64_t Address,
1576 const void *Decoder) {
1577 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1578
1579 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1580 return MCDisassembler::Success;
1581 }
1582
DecodeBranchTarget26(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)1583 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1584 unsigned Offset,
1585 uint64_t Address,
1586 const void *Decoder) {
1587 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1588
1589 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1590 return MCDisassembler::Success;
1591 }
1592
DecodeBranchTarget7MM(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)1593 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1594 unsigned Offset,
1595 uint64_t Address,
1596 const void *Decoder) {
1597 int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1598 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1599 return MCDisassembler::Success;
1600 }
1601
DecodeBranchTargetMM(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)1602 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1603 unsigned Offset,
1604 uint64_t Address,
1605 const void *Decoder) {
1606 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1607 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1608 return MCDisassembler::Success;
1609 }
1610
DecodeJumpTargetMM(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1611 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1612 unsigned Insn,
1613 uint64_t Address,
1614 const void *Decoder) {
1615 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1616 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1617 return MCDisassembler::Success;
1618 }
1619
DecodeAddiur2Simm7(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)1620 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1621 unsigned Value,
1622 uint64_t Address,
1623 const void *Decoder) {
1624 if (Value == 0)
1625 Inst.addOperand(MCOperand::CreateImm(1));
1626 else if (Value == 0x7)
1627 Inst.addOperand(MCOperand::CreateImm(-1));
1628 else
1629 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1630 return MCDisassembler::Success;
1631 }
1632
DecodeUImm6Lsl2(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)1633 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1634 unsigned Value,
1635 uint64_t Address,
1636 const void *Decoder) {
1637 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1638 return MCDisassembler::Success;
1639 }
1640
DecodeLiSimm7(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)1641 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1642 unsigned Value,
1643 uint64_t Address,
1644 const void *Decoder) {
1645 if (Value == 0x7F)
1646 Inst.addOperand(MCOperand::CreateImm(-1));
1647 else
1648 Inst.addOperand(MCOperand::CreateImm(Value));
1649 return MCDisassembler::Success;
1650 }
1651
DecodeSimm4(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)1652 static DecodeStatus DecodeSimm4(MCInst &Inst,
1653 unsigned Value,
1654 uint64_t Address,
1655 const void *Decoder) {
1656 Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1657 return MCDisassembler::Success;
1658 }
1659
DecodeSimm16(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1660 static DecodeStatus DecodeSimm16(MCInst &Inst,
1661 unsigned Insn,
1662 uint64_t Address,
1663 const void *Decoder) {
1664 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1665 return MCDisassembler::Success;
1666 }
1667
DecodeLSAImm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1668 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1669 unsigned Insn,
1670 uint64_t Address,
1671 const void *Decoder) {
1672 // We add one to the immediate field as it was encoded as 'imm - 1'.
1673 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1674 return MCDisassembler::Success;
1675 }
1676
DecodeInsSize(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1677 static DecodeStatus DecodeInsSize(MCInst &Inst,
1678 unsigned Insn,
1679 uint64_t Address,
1680 const void *Decoder) {
1681 // First we need to grab the pos(lsb) from MCInst.
1682 int Pos = Inst.getOperand(2).getImm();
1683 int Size = (int) Insn - Pos + 1;
1684 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1685 return MCDisassembler::Success;
1686 }
1687
DecodeExtSize(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1688 static DecodeStatus DecodeExtSize(MCInst &Inst,
1689 unsigned Insn,
1690 uint64_t Address,
1691 const void *Decoder) {
1692 int Size = (int) Insn + 1;
1693 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1694 return MCDisassembler::Success;
1695 }
1696
DecodeSimm19Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1697 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1698 uint64_t Address, const void *Decoder) {
1699 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1700 return MCDisassembler::Success;
1701 }
1702
DecodeSimm18Lsl3(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1703 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1704 uint64_t Address, const void *Decoder) {
1705 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1706 return MCDisassembler::Success;
1707 }
1708
DecodeSimm9SP(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1709 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1710 uint64_t Address, const void *Decoder) {
1711 int32_t DecodedValue;
1712 switch (Insn) {
1713 case 0: DecodedValue = 256; break;
1714 case 1: DecodedValue = 257; break;
1715 case 510: DecodedValue = -258; break;
1716 case 511: DecodedValue = -257; break;
1717 default: DecodedValue = SignExtend32<9>(Insn); break;
1718 }
1719 Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1720 return MCDisassembler::Success;
1721 }
1722
DecodeANDI16Imm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1723 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1724 uint64_t Address, const void *Decoder) {
1725 // Insn must be >= 0, since it is unsigned that condition is always true.
1726 assert(Insn < 16);
1727 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1728 255, 32768, 65535};
1729 Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1730 return MCDisassembler::Success;
1731 }
1732
DecodeUImm5lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1733 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1734 uint64_t Address, const void *Decoder) {
1735 Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1736 return MCDisassembler::Success;
1737 }
1738
DecodeRegListOperand(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1739 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1740 unsigned Insn,
1741 uint64_t Address,
1742 const void *Decoder) {
1743 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1744 Mips::S6, Mips::FP};
1745 unsigned RegNum;
1746
1747 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1748 // Empty register lists are not allowed.
1749 if (RegLst == 0)
1750 return MCDisassembler::Fail;
1751
1752 RegNum = RegLst & 0xf;
1753 for (unsigned i = 0; i < RegNum; i++)
1754 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1755
1756 if (RegLst & 0x10)
1757 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1758
1759 return MCDisassembler::Success;
1760 }
1761
DecodeRegListOperand16(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1762 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1763 uint64_t Address,
1764 const void *Decoder) {
1765 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1766 unsigned RegNum;
1767
1768 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1769 // Empty register lists are not allowed.
1770 if (RegLst == 0)
1771 return MCDisassembler::Fail;
1772
1773 RegNum = RegLst & 0x3;
1774 for (unsigned i = 0; i < RegNum - 1; i++)
1775 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1776
1777 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1778
1779 return MCDisassembler::Success;
1780 }
1781