1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is the top level entry point for the PowerPC target. 11// 12//===----------------------------------------------------------------------===// 13 14// Get the target-independent interfaces which we are implementing. 15// 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// PowerPC Subtarget features. 20// 21 22//===----------------------------------------------------------------------===// 23// CPU Directives // 24//===----------------------------------------------------------------------===// 25 26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; 27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; 28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; 29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; 33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; 34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; 35def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; 36def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; 37def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; 38def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", 39 "PPC::DIR_E500mc", "">; 40def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", 41 "PPC::DIR_E5500", "">; 42def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">; 43def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">; 44def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">; 45def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">; 46def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; 47def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; 48def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; 49def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">; 50 51def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 52 "Enable 64-bit instructions">; 53def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 54 "Enable 64-bit registers usage for ppc32 [beta]">; 55def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 56 "Use condition-register bits individually">; 57def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 58 "Enable Altivec instructions">; 59def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 60 "Enable SPE instructions">; 61def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 62 "Enable the MFOCRF instruction">; 63def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 64 "Enable the fsqrt instruction">; 65def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 66 "Enable the fcpsgn instruction">; 67def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 68 "Enable the fre instruction">; 69def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 70 "Enable the fres instruction">; 71def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 72 "Enable the frsqrte instruction">; 73def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 74 "Enable the frsqrtes instruction">; 75def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 76 "Assume higher precision reciprocal estimates">; 77def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 78 "Enable the stfiwx instruction">; 79def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 80 "Enable the lfiwax instruction">; 81def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 82 "Enable the fri[mnpz] instructions">; 83def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 84 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">; 85def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 86 "Enable the isel instruction">; 87def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true", 88 "Enable the popcnt[dw] instructions">; 89def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 90 "Enable the ldbrx instruction">; 91def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 92 "Enable the cmpb instruction">; 93def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 94 "Enable Book E instructions">; 95def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 96 "Has only the msync instruction instead of sync", 97 [FeatureBookE]>; 98def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 99 "Enable E500/E500mc instructions">; 100def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 101 "Enable PPC 4xx instructions">; 102def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 103 "Enable PPC 6xx instructions">; 104def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 105 "Enable QPX instructions">; 106def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 107 "Enable VSX instructions", 108 [FeatureAltivec]>; 109def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 110 "Enable POWER8 vector instructions", 111 [FeatureVSX, FeatureAltivec]>; 112 113def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true", 114 "Treat mftb as deprecated">; 115def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 116 "Treat vector data stream cache control instructions as deprecated">; 117 118// Note: Future features to add when support is extended to more 119// recent ISA levels: 120// 121// DFP p6, p6x, p7 decimal floating-point instructions 122// POPCNTB p5 through p7 popcntb and related instructions 123 124//===----------------------------------------------------------------------===// 125// ABI Selection // 126//===----------------------------------------------------------------------===// 127 128def FeatureELFv1 : SubtargetFeature<"elfv1", "TargetABI", "PPC_ABI_ELFv1", 129 "Use the ELFv1 ABI">; 130 131def FeatureELFv2 : SubtargetFeature<"elfv2", "TargetABI", "PPC_ABI_ELFv2", 132 "Use the ELFv2 ABI">; 133 134//===----------------------------------------------------------------------===// 135// Classes used for relation maps. 136//===----------------------------------------------------------------------===// 137// RecFormRel - Filter class used to relate non-record-form instructions with 138// their record-form variants. 139class RecFormRel; 140 141// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 142// FMA instruction forms with their corresponding factor-killing forms. 143class AltVSXFMARel { 144 bit IsVSXFMAAlt = 0; 145} 146 147//===----------------------------------------------------------------------===// 148// Relation Map Definitions. 149//===----------------------------------------------------------------------===// 150 151def getRecordFormOpcode : InstrMapping { 152 let FilterClass = "RecFormRel"; 153 // Instructions with the same BaseName and Interpretation64Bit values 154 // form a row. 155 let RowFields = ["BaseName", "Interpretation64Bit"]; 156 // Instructions with the same RC value form a column. 157 let ColFields = ["RC"]; 158 // The key column are the non-record-form instructions. 159 let KeyCol = ["0"]; 160 // Value columns RC=1 161 let ValueCols = [["1"]]; 162} 163 164def getNonRecordFormOpcode : InstrMapping { 165 let FilterClass = "RecFormRel"; 166 // Instructions with the same BaseName and Interpretation64Bit values 167 // form a row. 168 let RowFields = ["BaseName", "Interpretation64Bit"]; 169 // Instructions with the same RC value form a column. 170 let ColFields = ["RC"]; 171 // The key column are the record-form instructions. 172 let KeyCol = ["1"]; 173 // Value columns are RC=0 174 let ValueCols = [["0"]]; 175} 176 177def getAltVSXFMAOpcode : InstrMapping { 178 let FilterClass = "AltVSXFMARel"; 179 // Instructions with the same BaseName and Interpretation64Bit values 180 // form a row. 181 let RowFields = ["BaseName"]; 182 // Instructions with the same RC value form a column. 183 let ColFields = ["IsVSXFMAAlt"]; 184 // The key column are the (default) addend-killing instructions. 185 let KeyCol = ["0"]; 186 // Value columns IsVSXFMAAlt=1 187 let ValueCols = [["1"]]; 188} 189 190//===----------------------------------------------------------------------===// 191// Register File Description 192//===----------------------------------------------------------------------===// 193 194include "PPCRegisterInfo.td" 195include "PPCSchedule.td" 196include "PPCInstrInfo.td" 197 198//===----------------------------------------------------------------------===// 199// PowerPC processors supported. 200// 201 202def : Processor<"generic", G3Itineraries, [Directive32]>; 203def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 204 FeatureFRES, FeatureFRSQRTE, 205 FeatureBookE, FeatureMSYNC, 206 DeprecatedMFTB]>; 207def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 208 FeatureFRES, FeatureFRSQRTE, 209 FeatureBookE, FeatureMSYNC, 210 DeprecatedMFTB]>; 211def : Processor<"601", G3Itineraries, [Directive601]>; 212def : Processor<"602", G3Itineraries, [Directive602]>; 213def : Processor<"603", G3Itineraries, [Directive603, 214 FeatureFRES, FeatureFRSQRTE]>; 215def : Processor<"603e", G3Itineraries, [Directive603, 216 FeatureFRES, FeatureFRSQRTE]>; 217def : Processor<"603ev", G3Itineraries, [Directive603, 218 FeatureFRES, FeatureFRSQRTE]>; 219def : Processor<"604", G3Itineraries, [Directive604, 220 FeatureFRES, FeatureFRSQRTE]>; 221def : Processor<"604e", G3Itineraries, [Directive604, 222 FeatureFRES, FeatureFRSQRTE]>; 223def : Processor<"620", G3Itineraries, [Directive620, 224 FeatureFRES, FeatureFRSQRTE]>; 225def : Processor<"750", G4Itineraries, [Directive750, 226 FeatureFRES, FeatureFRSQRTE]>; 227def : Processor<"g3", G3Itineraries, [Directive750, 228 FeatureFRES, FeatureFRSQRTE]>; 229def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 230 FeatureFRES, FeatureFRSQRTE]>; 231def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 232 FeatureFRES, FeatureFRSQRTE]>; 233def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 234 FeatureFRES, FeatureFRSQRTE]>; 235def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 236 FeatureFRES, FeatureFRSQRTE]>; 237def : ProcessorModel<"970", G5Model, 238 [Directive970, FeatureAltivec, 239 FeatureMFOCRF, FeatureFSqrt, 240 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 241 Feature64Bit /*, Feature64BitRegs */]>; 242def : ProcessorModel<"g5", G5Model, 243 [Directive970, FeatureAltivec, 244 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 245 FeatureFRES, FeatureFRSQRTE, 246 Feature64Bit /*, Feature64BitRegs */, 247 DeprecatedMFTB, DeprecatedDST]>; 248def : ProcessorModel<"e500mc", PPCE500mcModel, 249 [DirectiveE500mc, FeatureMFOCRF, 250 FeatureSTFIWX, FeatureBookE, FeatureISEL, 251 DeprecatedMFTB]>; 252def : ProcessorModel<"e5500", PPCE5500Model, 253 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 254 FeatureSTFIWX, FeatureBookE, FeatureISEL, 255 DeprecatedMFTB]>; 256def : ProcessorModel<"a2", PPCA2Model, 257 [DirectiveA2, FeatureBookE, FeatureMFOCRF, 258 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 259 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 260 FeatureSTFIWX, FeatureLFIWAX, 261 FeatureFPRND, FeatureFPCVT, FeatureISEL, 262 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit 263 /*, Feature64BitRegs */, DeprecatedMFTB]>; 264def : ProcessorModel<"a2q", PPCA2Model, 265 [DirectiveA2, FeatureBookE, FeatureMFOCRF, 266 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 267 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 268 FeatureSTFIWX, FeatureLFIWAX, 269 FeatureFPRND, FeatureFPCVT, FeatureISEL, 270 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit 271 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>; 272def : ProcessorModel<"pwr3", G5Model, 273 [DirectivePwr3, FeatureAltivec, 274 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 275 FeatureSTFIWX, Feature64Bit]>; 276def : ProcessorModel<"pwr4", G5Model, 277 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 278 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 279 FeatureSTFIWX, Feature64Bit]>; 280def : ProcessorModel<"pwr5", G5Model, 281 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 282 FeatureFSqrt, FeatureFRE, FeatureFRES, 283 FeatureFRSQRTE, FeatureFRSQRTES, 284 FeatureSTFIWX, Feature64Bit, 285 DeprecatedMFTB, DeprecatedDST]>; 286def : ProcessorModel<"pwr5x", G5Model, 287 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 288 FeatureFSqrt, FeatureFRE, FeatureFRES, 289 FeatureFRSQRTE, FeatureFRSQRTES, 290 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 291 DeprecatedMFTB, DeprecatedDST]>; 292def : ProcessorModel<"pwr6", G5Model, 293 [DirectivePwr6, FeatureAltivec, 294 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 295 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 296 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 297 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 298 DeprecatedMFTB, DeprecatedDST]>; 299def : ProcessorModel<"pwr6x", G5Model, 300 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 301 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 302 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 303 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 304 FeatureFPRND, Feature64Bit, 305 DeprecatedMFTB, DeprecatedDST]>; 306def : ProcessorModel<"pwr7", P7Model, 307 [DirectivePwr7, FeatureAltivec, FeatureVSX, 308 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 309 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 310 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 311 FeatureFPRND, FeatureFPCVT, FeatureISEL, 312 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, 313 Feature64Bit /*, Feature64BitRegs */, 314 DeprecatedMFTB, DeprecatedDST]>; 315def : ProcessorModel<"pwr8", P8Model, 316 [DirectivePwr8, FeatureAltivec, FeatureVSX, FeatureP8Vector, 317 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 318 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 319 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 320 FeatureFPRND, FeatureFPCVT, FeatureISEL, 321 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, 322 Feature64Bit /*, Feature64BitRegs */, 323 DeprecatedMFTB, DeprecatedDST]>; 324def : Processor<"ppc", G3Itineraries, [Directive32]>; 325def : ProcessorModel<"ppc64", G5Model, 326 [Directive64, FeatureAltivec, 327 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 328 FeatureFRSQRTE, FeatureSTFIWX, 329 Feature64Bit /*, Feature64BitRegs */]>; 330def : ProcessorModel<"ppc64le", G5Model, 331 [Directive64, FeatureAltivec, 332 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 333 FeatureFRSQRTE, FeatureSTFIWX, 334 Feature64Bit /*, Feature64BitRegs */]>; 335 336//===----------------------------------------------------------------------===// 337// Calling Conventions 338//===----------------------------------------------------------------------===// 339 340include "PPCCallingConv.td" 341 342def PPCInstrInfo : InstrInfo { 343 let isLittleEndianEncoding = 1; 344 345 // FIXME: Unset this when no longer needed! 346 let decodePositionallyEncodedOperands = 1; 347 348 let noNamedPositionallyEncodedOperands = 1; 349} 350 351def PPCAsmParser : AsmParser { 352 let ShouldEmitMatchRegisterName = 0; 353} 354 355def PPCAsmParserVariant : AsmParserVariant { 356 int Variant = 0; 357 358 // We do not use hard coded registers in asm strings. However, some 359 // InstAlias definitions use immediate literals. Set RegisterPrefix 360 // so that those are not misinterpreted as registers. 361 string RegisterPrefix = "%"; 362} 363 364def PPC : Target { 365 // Information about the instructions. 366 let InstructionSet = PPCInstrInfo; 367 368 let AssemblyParsers = [PPCAsmParser]; 369 let AssemblyParserVariants = [PPCAsmParserVariant]; 370} 371