1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPC.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/CodeGen/ScheduleDAG.h"
31 #include "llvm/CodeGen/SlotIndexes.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39
40 using namespace llvm;
41
42 #define DEBUG_TYPE "ppc-instr-info"
43
44 #define GET_INSTRMAP_INFO
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "PPCGenInstrInfo.inc"
47
48 static cl::
49 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
50 cl::desc("Disable analysis for CTR loops"));
51
52 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
53 cl::desc("Disable compare instruction optimization"), cl::Hidden);
54
55 static cl::opt<bool> DisableVSXFMAMutate("disable-ppc-vsx-fma-mutation",
56 cl::desc("Disable VSX FMA instruction mutation"), cl::Hidden);
57
58 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
59 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
60 cl::Hidden);
61
62 // Pin the vtable to this file.
anchor()63 void PPCInstrInfo::anchor() {}
64
PPCInstrInfo(PPCSubtarget & STI)65 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
66 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
67 Subtarget(STI), RI(STI) {}
68
69 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
70 /// this target when scheduling the DAG.
71 ScheduleHazardRecognizer *
CreateTargetHazardRecognizer(const TargetSubtargetInfo * STI,const ScheduleDAG * DAG) const72 PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
73 const ScheduleDAG *DAG) const {
74 unsigned Directive =
75 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
76 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
77 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
78 const InstrItineraryData *II =
79 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
80 return new ScoreboardHazardRecognizer(II, DAG);
81 }
82
83 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
84 }
85
86 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
87 /// to use for this target when scheduling the DAG.
CreateTargetPostRAHazardRecognizer(const InstrItineraryData * II,const ScheduleDAG * DAG) const88 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
89 const InstrItineraryData *II,
90 const ScheduleDAG *DAG) const {
91 unsigned Directive =
92 DAG->TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
93
94 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
95 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
96
97 // Most subtargets use a PPC970 recognizer.
98 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
99 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
100 assert(DAG->TII && "No InstrInfo?");
101
102 return new PPCHazardRecognizer970(*DAG);
103 }
104
105 return new ScoreboardHazardRecognizer(II, DAG);
106 }
107
108
getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr * DefMI,unsigned DefIdx,const MachineInstr * UseMI,unsigned UseIdx) const109 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
110 const MachineInstr *DefMI, unsigned DefIdx,
111 const MachineInstr *UseMI,
112 unsigned UseIdx) const {
113 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
114 UseMI, UseIdx);
115
116 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
117 unsigned Reg = DefMO.getReg();
118
119 const TargetRegisterInfo *TRI = &getRegisterInfo();
120 bool IsRegCR;
121 if (TRI->isVirtualRegister(Reg)) {
122 const MachineRegisterInfo *MRI =
123 &DefMI->getParent()->getParent()->getRegInfo();
124 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
125 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
126 } else {
127 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
128 PPC::CRBITRCRegClass.contains(Reg);
129 }
130
131 if (UseMI->isBranch() && IsRegCR) {
132 if (Latency < 0)
133 Latency = getInstrLatency(ItinData, DefMI);
134
135 // On some cores, there is an additional delay between writing to a condition
136 // register, and using it from a branch.
137 unsigned Directive = Subtarget.getDarwinDirective();
138 switch (Directive) {
139 default: break;
140 case PPC::DIR_7400:
141 case PPC::DIR_750:
142 case PPC::DIR_970:
143 case PPC::DIR_E5500:
144 case PPC::DIR_PWR4:
145 case PPC::DIR_PWR5:
146 case PPC::DIR_PWR5X:
147 case PPC::DIR_PWR6:
148 case PPC::DIR_PWR6X:
149 case PPC::DIR_PWR7:
150 case PPC::DIR_PWR8:
151 Latency += 2;
152 break;
153 }
154 }
155
156 return Latency;
157 }
158
159 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
isCoalescableExtInstr(const MachineInstr & MI,unsigned & SrcReg,unsigned & DstReg,unsigned & SubIdx) const160 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
161 unsigned &SrcReg, unsigned &DstReg,
162 unsigned &SubIdx) const {
163 switch (MI.getOpcode()) {
164 default: return false;
165 case PPC::EXTSW:
166 case PPC::EXTSW_32_64:
167 SrcReg = MI.getOperand(1).getReg();
168 DstReg = MI.getOperand(0).getReg();
169 SubIdx = PPC::sub_32;
170 return true;
171 }
172 }
173
isLoadFromStackSlot(const MachineInstr * MI,int & FrameIndex) const174 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
175 int &FrameIndex) const {
176 // Note: This list must be kept consistent with LoadRegFromStackSlot.
177 switch (MI->getOpcode()) {
178 default: break;
179 case PPC::LD:
180 case PPC::LWZ:
181 case PPC::LFS:
182 case PPC::LFD:
183 case PPC::RESTORE_CR:
184 case PPC::RESTORE_CRBIT:
185 case PPC::LVX:
186 case PPC::LXVD2X:
187 case PPC::RESTORE_VRSAVE:
188 // Check for the operands added by addFrameReference (the immediate is the
189 // offset which defaults to 0).
190 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
191 MI->getOperand(2).isFI()) {
192 FrameIndex = MI->getOperand(2).getIndex();
193 return MI->getOperand(0).getReg();
194 }
195 break;
196 }
197 return 0;
198 }
199
isStoreToStackSlot(const MachineInstr * MI,int & FrameIndex) const200 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
201 int &FrameIndex) const {
202 // Note: This list must be kept consistent with StoreRegToStackSlot.
203 switch (MI->getOpcode()) {
204 default: break;
205 case PPC::STD:
206 case PPC::STW:
207 case PPC::STFS:
208 case PPC::STFD:
209 case PPC::SPILL_CR:
210 case PPC::SPILL_CRBIT:
211 case PPC::STVX:
212 case PPC::STXVD2X:
213 case PPC::SPILL_VRSAVE:
214 // Check for the operands added by addFrameReference (the immediate is the
215 // offset which defaults to 0).
216 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
217 MI->getOperand(2).isFI()) {
218 FrameIndex = MI->getOperand(2).getIndex();
219 return MI->getOperand(0).getReg();
220 }
221 break;
222 }
223 return 0;
224 }
225
226 // commuteInstruction - We can commute rlwimi instructions, but only if the
227 // rotate amt is zero. We also have to munge the immediates a bit.
228 MachineInstr *
commuteInstruction(MachineInstr * MI,bool NewMI) const229 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
230 MachineFunction &MF = *MI->getParent()->getParent();
231
232 // Normal instructions can be commuted the obvious way.
233 if (MI->getOpcode() != PPC::RLWIMI &&
234 MI->getOpcode() != PPC::RLWIMIo)
235 return TargetInstrInfo::commuteInstruction(MI, NewMI);
236 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
237 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
238 // changing the relative order of the mask operands might change what happens
239 // to the high-bits of the mask (and, thus, the result).
240
241 // Cannot commute if it has a non-zero rotate count.
242 if (MI->getOperand(3).getImm() != 0)
243 return nullptr;
244
245 // If we have a zero rotate count, we have:
246 // M = mask(MB,ME)
247 // Op0 = (Op1 & ~M) | (Op2 & M)
248 // Change this to:
249 // M = mask((ME+1)&31, (MB-1)&31)
250 // Op0 = (Op2 & ~M) | (Op1 & M)
251
252 // Swap op1/op2
253 unsigned Reg0 = MI->getOperand(0).getReg();
254 unsigned Reg1 = MI->getOperand(1).getReg();
255 unsigned Reg2 = MI->getOperand(2).getReg();
256 unsigned SubReg1 = MI->getOperand(1).getSubReg();
257 unsigned SubReg2 = MI->getOperand(2).getSubReg();
258 bool Reg1IsKill = MI->getOperand(1).isKill();
259 bool Reg2IsKill = MI->getOperand(2).isKill();
260 bool ChangeReg0 = false;
261 // If machine instrs are no longer in two-address forms, update
262 // destination register as well.
263 if (Reg0 == Reg1) {
264 // Must be two address instruction!
265 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
266 "Expecting a two-address instruction!");
267 assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
268 Reg2IsKill = false;
269 ChangeReg0 = true;
270 }
271
272 // Masks.
273 unsigned MB = MI->getOperand(4).getImm();
274 unsigned ME = MI->getOperand(5).getImm();
275
276 if (NewMI) {
277 // Create a new instruction.
278 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
279 bool Reg0IsDead = MI->getOperand(0).isDead();
280 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
281 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
282 .addReg(Reg2, getKillRegState(Reg2IsKill))
283 .addReg(Reg1, getKillRegState(Reg1IsKill))
284 .addImm((ME+1) & 31)
285 .addImm((MB-1) & 31);
286 }
287
288 if (ChangeReg0) {
289 MI->getOperand(0).setReg(Reg2);
290 MI->getOperand(0).setSubReg(SubReg2);
291 }
292 MI->getOperand(2).setReg(Reg1);
293 MI->getOperand(1).setReg(Reg2);
294 MI->getOperand(2).setSubReg(SubReg1);
295 MI->getOperand(1).setSubReg(SubReg2);
296 MI->getOperand(2).setIsKill(Reg1IsKill);
297 MI->getOperand(1).setIsKill(Reg2IsKill);
298
299 // Swap the mask around.
300 MI->getOperand(4).setImm((ME+1) & 31);
301 MI->getOperand(5).setImm((MB-1) & 31);
302 return MI;
303 }
304
findCommutedOpIndices(MachineInstr * MI,unsigned & SrcOpIdx1,unsigned & SrcOpIdx2) const305 bool PPCInstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
306 unsigned &SrcOpIdx2) const {
307 // For VSX A-Type FMA instructions, it is the first two operands that can be
308 // commuted, however, because the non-encoded tied input operand is listed
309 // first, the operands to swap are actually the second and third.
310
311 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
312 if (AltOpc == -1)
313 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
314
315 SrcOpIdx1 = 2;
316 SrcOpIdx2 = 3;
317 return true;
318 }
319
insertNoop(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI) const320 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
321 MachineBasicBlock::iterator MI) const {
322 // This function is used for scheduling, and the nop wanted here is the type
323 // that terminates dispatch groups on the POWER cores.
324 unsigned Directive = Subtarget.getDarwinDirective();
325 unsigned Opcode;
326 switch (Directive) {
327 default: Opcode = PPC::NOP; break;
328 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
329 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
330 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
331 }
332
333 DebugLoc DL;
334 BuildMI(MBB, MI, DL, get(Opcode));
335 }
336
337 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
getNoopForMachoTarget(MCInst & NopInst) const338 void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
339 NopInst.setOpcode(PPC::NOP);
340 }
341
342 // Branch analysis.
343 // Note: If the condition register is set to CTR or CTR8 then this is a
344 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
AnalyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const345 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
346 MachineBasicBlock *&FBB,
347 SmallVectorImpl<MachineOperand> &Cond,
348 bool AllowModify) const {
349 bool isPPC64 = Subtarget.isPPC64();
350
351 // If the block has no terminators, it just falls into the block after it.
352 MachineBasicBlock::iterator I = MBB.end();
353 if (I == MBB.begin())
354 return false;
355 --I;
356 while (I->isDebugValue()) {
357 if (I == MBB.begin())
358 return false;
359 --I;
360 }
361 if (!isUnpredicatedTerminator(I))
362 return false;
363
364 // Get the last instruction in the block.
365 MachineInstr *LastInst = I;
366
367 // If there is only one terminator instruction, process it.
368 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
369 if (LastInst->getOpcode() == PPC::B) {
370 if (!LastInst->getOperand(0).isMBB())
371 return true;
372 TBB = LastInst->getOperand(0).getMBB();
373 return false;
374 } else if (LastInst->getOpcode() == PPC::BCC) {
375 if (!LastInst->getOperand(2).isMBB())
376 return true;
377 // Block ends with fall-through condbranch.
378 TBB = LastInst->getOperand(2).getMBB();
379 Cond.push_back(LastInst->getOperand(0));
380 Cond.push_back(LastInst->getOperand(1));
381 return false;
382 } else if (LastInst->getOpcode() == PPC::BC) {
383 if (!LastInst->getOperand(1).isMBB())
384 return true;
385 // Block ends with fall-through condbranch.
386 TBB = LastInst->getOperand(1).getMBB();
387 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
388 Cond.push_back(LastInst->getOperand(0));
389 return false;
390 } else if (LastInst->getOpcode() == PPC::BCn) {
391 if (!LastInst->getOperand(1).isMBB())
392 return true;
393 // Block ends with fall-through condbranch.
394 TBB = LastInst->getOperand(1).getMBB();
395 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
396 Cond.push_back(LastInst->getOperand(0));
397 return false;
398 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
399 LastInst->getOpcode() == PPC::BDNZ) {
400 if (!LastInst->getOperand(0).isMBB())
401 return true;
402 if (DisableCTRLoopAnal)
403 return true;
404 TBB = LastInst->getOperand(0).getMBB();
405 Cond.push_back(MachineOperand::CreateImm(1));
406 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
407 true));
408 return false;
409 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
410 LastInst->getOpcode() == PPC::BDZ) {
411 if (!LastInst->getOperand(0).isMBB())
412 return true;
413 if (DisableCTRLoopAnal)
414 return true;
415 TBB = LastInst->getOperand(0).getMBB();
416 Cond.push_back(MachineOperand::CreateImm(0));
417 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
418 true));
419 return false;
420 }
421
422 // Otherwise, don't know what this is.
423 return true;
424 }
425
426 // Get the instruction before it if it's a terminator.
427 MachineInstr *SecondLastInst = I;
428
429 // If there are three terminators, we don't know what sort of block this is.
430 if (SecondLastInst && I != MBB.begin() &&
431 isUnpredicatedTerminator(--I))
432 return true;
433
434 // If the block ends with PPC::B and PPC:BCC, handle it.
435 if (SecondLastInst->getOpcode() == PPC::BCC &&
436 LastInst->getOpcode() == PPC::B) {
437 if (!SecondLastInst->getOperand(2).isMBB() ||
438 !LastInst->getOperand(0).isMBB())
439 return true;
440 TBB = SecondLastInst->getOperand(2).getMBB();
441 Cond.push_back(SecondLastInst->getOperand(0));
442 Cond.push_back(SecondLastInst->getOperand(1));
443 FBB = LastInst->getOperand(0).getMBB();
444 return false;
445 } else if (SecondLastInst->getOpcode() == PPC::BC &&
446 LastInst->getOpcode() == PPC::B) {
447 if (!SecondLastInst->getOperand(1).isMBB() ||
448 !LastInst->getOperand(0).isMBB())
449 return true;
450 TBB = SecondLastInst->getOperand(1).getMBB();
451 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
452 Cond.push_back(SecondLastInst->getOperand(0));
453 FBB = LastInst->getOperand(0).getMBB();
454 return false;
455 } else if (SecondLastInst->getOpcode() == PPC::BCn &&
456 LastInst->getOpcode() == PPC::B) {
457 if (!SecondLastInst->getOperand(1).isMBB() ||
458 !LastInst->getOperand(0).isMBB())
459 return true;
460 TBB = SecondLastInst->getOperand(1).getMBB();
461 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
462 Cond.push_back(SecondLastInst->getOperand(0));
463 FBB = LastInst->getOperand(0).getMBB();
464 return false;
465 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
466 SecondLastInst->getOpcode() == PPC::BDNZ) &&
467 LastInst->getOpcode() == PPC::B) {
468 if (!SecondLastInst->getOperand(0).isMBB() ||
469 !LastInst->getOperand(0).isMBB())
470 return true;
471 if (DisableCTRLoopAnal)
472 return true;
473 TBB = SecondLastInst->getOperand(0).getMBB();
474 Cond.push_back(MachineOperand::CreateImm(1));
475 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
476 true));
477 FBB = LastInst->getOperand(0).getMBB();
478 return false;
479 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
480 SecondLastInst->getOpcode() == PPC::BDZ) &&
481 LastInst->getOpcode() == PPC::B) {
482 if (!SecondLastInst->getOperand(0).isMBB() ||
483 !LastInst->getOperand(0).isMBB())
484 return true;
485 if (DisableCTRLoopAnal)
486 return true;
487 TBB = SecondLastInst->getOperand(0).getMBB();
488 Cond.push_back(MachineOperand::CreateImm(0));
489 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
490 true));
491 FBB = LastInst->getOperand(0).getMBB();
492 return false;
493 }
494
495 // If the block ends with two PPC:Bs, handle it. The second one is not
496 // executed, so remove it.
497 if (SecondLastInst->getOpcode() == PPC::B &&
498 LastInst->getOpcode() == PPC::B) {
499 if (!SecondLastInst->getOperand(0).isMBB())
500 return true;
501 TBB = SecondLastInst->getOperand(0).getMBB();
502 I = LastInst;
503 if (AllowModify)
504 I->eraseFromParent();
505 return false;
506 }
507
508 // Otherwise, can't handle this.
509 return true;
510 }
511
RemoveBranch(MachineBasicBlock & MBB) const512 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
513 MachineBasicBlock::iterator I = MBB.end();
514 if (I == MBB.begin()) return 0;
515 --I;
516 while (I->isDebugValue()) {
517 if (I == MBB.begin())
518 return 0;
519 --I;
520 }
521 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
522 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
523 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
524 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
525 return 0;
526
527 // Remove the branch.
528 I->eraseFromParent();
529
530 I = MBB.end();
531
532 if (I == MBB.begin()) return 1;
533 --I;
534 if (I->getOpcode() != PPC::BCC &&
535 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
536 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
537 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
538 return 1;
539
540 // Remove the branch.
541 I->eraseFromParent();
542 return 2;
543 }
544
545 unsigned
InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,const SmallVectorImpl<MachineOperand> & Cond,DebugLoc DL) const546 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
547 MachineBasicBlock *FBB,
548 const SmallVectorImpl<MachineOperand> &Cond,
549 DebugLoc DL) const {
550 // Shouldn't be a fall through.
551 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
552 assert((Cond.size() == 2 || Cond.size() == 0) &&
553 "PPC branch conditions have two components!");
554
555 bool isPPC64 = Subtarget.isPPC64();
556
557 // One-way branch.
558 if (!FBB) {
559 if (Cond.empty()) // Unconditional branch
560 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
561 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
562 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
563 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
564 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
565 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
566 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
567 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
568 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
569 else // Conditional branch
570 BuildMI(&MBB, DL, get(PPC::BCC))
571 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
572 return 1;
573 }
574
575 // Two-way Conditional Branch.
576 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
577 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
578 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
579 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
580 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
581 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
582 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
583 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
584 else
585 BuildMI(&MBB, DL, get(PPC::BCC))
586 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
587 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
588 return 2;
589 }
590
591 // Select analysis.
canInsertSelect(const MachineBasicBlock & MBB,const SmallVectorImpl<MachineOperand> & Cond,unsigned TrueReg,unsigned FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const592 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
593 const SmallVectorImpl<MachineOperand> &Cond,
594 unsigned TrueReg, unsigned FalseReg,
595 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
596 if (!Subtarget.hasISEL())
597 return false;
598
599 if (Cond.size() != 2)
600 return false;
601
602 // If this is really a bdnz-like condition, then it cannot be turned into a
603 // select.
604 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
605 return false;
606
607 // Check register classes.
608 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
609 const TargetRegisterClass *RC =
610 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
611 if (!RC)
612 return false;
613
614 // isel is for regular integer GPRs only.
615 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
616 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
617 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
618 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
619 return false;
620
621 // FIXME: These numbers are for the A2, how well they work for other cores is
622 // an open question. On the A2, the isel instruction has a 2-cycle latency
623 // but single-cycle throughput. These numbers are used in combination with
624 // the MispredictPenalty setting from the active SchedMachineModel.
625 CondCycles = 1;
626 TrueCycles = 1;
627 FalseCycles = 1;
628
629 return true;
630 }
631
insertSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,DebugLoc dl,unsigned DestReg,const SmallVectorImpl<MachineOperand> & Cond,unsigned TrueReg,unsigned FalseReg) const632 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
633 MachineBasicBlock::iterator MI, DebugLoc dl,
634 unsigned DestReg,
635 const SmallVectorImpl<MachineOperand> &Cond,
636 unsigned TrueReg, unsigned FalseReg) const {
637 assert(Cond.size() == 2 &&
638 "PPC branch conditions have two components!");
639
640 assert(Subtarget.hasISEL() &&
641 "Cannot insert select on target without ISEL support");
642
643 // Get the register classes.
644 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
645 const TargetRegisterClass *RC =
646 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
647 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
648
649 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
650 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
651 assert((Is64Bit ||
652 PPC::GPRCRegClass.hasSubClassEq(RC) ||
653 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
654 "isel is for regular integer GPRs only");
655
656 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
657 unsigned SelectPred = Cond[0].getImm();
658
659 unsigned SubIdx;
660 bool SwapOps;
661 switch (SelectPred) {
662 default: llvm_unreachable("invalid predicate for isel");
663 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
664 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
665 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
666 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
667 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
668 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
669 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
670 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
671 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
672 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
673 }
674
675 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
676 SecondReg = SwapOps ? TrueReg : FalseReg;
677
678 // The first input register of isel cannot be r0. If it is a member
679 // of a register class that can be r0, then copy it first (the
680 // register allocator should eliminate the copy).
681 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
682 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
683 const TargetRegisterClass *FirstRC =
684 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
685 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
686 unsigned OldFirstReg = FirstReg;
687 FirstReg = MRI.createVirtualRegister(FirstRC);
688 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
689 .addReg(OldFirstReg);
690 }
691
692 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
693 .addReg(FirstReg).addReg(SecondReg)
694 .addReg(Cond[1].getReg(), 0, SubIdx);
695 }
696
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const697 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
698 MachineBasicBlock::iterator I, DebugLoc DL,
699 unsigned DestReg, unsigned SrcReg,
700 bool KillSrc) const {
701 // We can end up with self copies and similar things as a result of VSX copy
702 // legalization. Promote them here.
703 const TargetRegisterInfo *TRI = &getRegisterInfo();
704 if (PPC::F8RCRegClass.contains(DestReg) &&
705 PPC::VSLRCRegClass.contains(SrcReg)) {
706 unsigned SuperReg =
707 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
708
709 if (VSXSelfCopyCrash && SrcReg == SuperReg)
710 llvm_unreachable("nop VSX copy");
711
712 DestReg = SuperReg;
713 } else if (PPC::VRRCRegClass.contains(DestReg) &&
714 PPC::VSHRCRegClass.contains(SrcReg)) {
715 unsigned SuperReg =
716 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
717
718 if (VSXSelfCopyCrash && SrcReg == SuperReg)
719 llvm_unreachable("nop VSX copy");
720
721 DestReg = SuperReg;
722 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
723 PPC::VSLRCRegClass.contains(DestReg)) {
724 unsigned SuperReg =
725 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
726
727 if (VSXSelfCopyCrash && DestReg == SuperReg)
728 llvm_unreachable("nop VSX copy");
729
730 SrcReg = SuperReg;
731 } else if (PPC::VRRCRegClass.contains(SrcReg) &&
732 PPC::VSHRCRegClass.contains(DestReg)) {
733 unsigned SuperReg =
734 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
735
736 if (VSXSelfCopyCrash && DestReg == SuperReg)
737 llvm_unreachable("nop VSX copy");
738
739 SrcReg = SuperReg;
740 }
741
742 unsigned Opc;
743 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
744 Opc = PPC::OR;
745 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
746 Opc = PPC::OR8;
747 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
748 Opc = PPC::FMR;
749 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
750 Opc = PPC::MCRF;
751 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
752 Opc = PPC::VOR;
753 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
754 // There are two different ways this can be done:
755 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
756 // issue in VSU pipeline 0.
757 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
758 // can go to either pipeline.
759 // We'll always use xxlor here, because in practically all cases where
760 // copies are generated, they are close enough to some use that the
761 // lower-latency form is preferable.
762 Opc = PPC::XXLOR;
763 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg))
764 Opc = PPC::XXLORf;
765 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
766 Opc = PPC::CROR;
767 else
768 llvm_unreachable("Impossible reg-to-reg copy");
769
770 const MCInstrDesc &MCID = get(Opc);
771 if (MCID.getNumOperands() == 3)
772 BuildMI(MBB, I, DL, MCID, DestReg)
773 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
774 else
775 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
776 }
777
778 // This function returns true if a CR spill is necessary and false otherwise.
779 bool
StoreRegToStackSlot(MachineFunction & MF,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,SmallVectorImpl<MachineInstr * > & NewMIs,bool & NonRI,bool & SpillsVRS) const780 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
781 unsigned SrcReg, bool isKill,
782 int FrameIdx,
783 const TargetRegisterClass *RC,
784 SmallVectorImpl<MachineInstr*> &NewMIs,
785 bool &NonRI, bool &SpillsVRS) const{
786 // Note: If additional store instructions are added here,
787 // update isStoreToStackSlot.
788
789 DebugLoc DL;
790 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
791 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
792 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
793 .addReg(SrcReg,
794 getKillRegState(isKill)),
795 FrameIdx));
796 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
797 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
798 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
799 .addReg(SrcReg,
800 getKillRegState(isKill)),
801 FrameIdx));
802 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
803 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
804 .addReg(SrcReg,
805 getKillRegState(isKill)),
806 FrameIdx));
807 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
808 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
809 .addReg(SrcReg,
810 getKillRegState(isKill)),
811 FrameIdx));
812 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
813 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
814 .addReg(SrcReg,
815 getKillRegState(isKill)),
816 FrameIdx));
817 return true;
818 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
819 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
820 .addReg(SrcReg,
821 getKillRegState(isKill)),
822 FrameIdx));
823 return true;
824 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
825 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
826 .addReg(SrcReg,
827 getKillRegState(isKill)),
828 FrameIdx));
829 NonRI = true;
830 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
831 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
832 .addReg(SrcReg,
833 getKillRegState(isKill)),
834 FrameIdx));
835 NonRI = true;
836 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
837 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX))
838 .addReg(SrcReg,
839 getKillRegState(isKill)),
840 FrameIdx));
841 NonRI = true;
842 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
843 assert(Subtarget.isDarwin() &&
844 "VRSAVE only needs spill/restore on Darwin");
845 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
846 .addReg(SrcReg,
847 getKillRegState(isKill)),
848 FrameIdx));
849 SpillsVRS = true;
850 } else {
851 llvm_unreachable("Unknown regclass!");
852 }
853
854 return false;
855 }
856
857 void
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const858 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
859 MachineBasicBlock::iterator MI,
860 unsigned SrcReg, bool isKill, int FrameIdx,
861 const TargetRegisterClass *RC,
862 const TargetRegisterInfo *TRI) const {
863 MachineFunction &MF = *MBB.getParent();
864 SmallVector<MachineInstr*, 4> NewMIs;
865
866 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
867 FuncInfo->setHasSpills();
868
869 bool NonRI = false, SpillsVRS = false;
870 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
871 NonRI, SpillsVRS))
872 FuncInfo->setSpillsCR();
873
874 if (SpillsVRS)
875 FuncInfo->setSpillsVRSAVE();
876
877 if (NonRI)
878 FuncInfo->setHasNonRISpills();
879
880 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
881 MBB.insert(MI, NewMIs[i]);
882
883 const MachineFrameInfo &MFI = *MF.getFrameInfo();
884 MachineMemOperand *MMO =
885 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
886 MachineMemOperand::MOStore,
887 MFI.getObjectSize(FrameIdx),
888 MFI.getObjectAlignment(FrameIdx));
889 NewMIs.back()->addMemOperand(MF, MMO);
890 }
891
892 bool
LoadRegFromStackSlot(MachineFunction & MF,DebugLoc DL,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,SmallVectorImpl<MachineInstr * > & NewMIs,bool & NonRI,bool & SpillsVRS) const893 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
894 unsigned DestReg, int FrameIdx,
895 const TargetRegisterClass *RC,
896 SmallVectorImpl<MachineInstr*> &NewMIs,
897 bool &NonRI, bool &SpillsVRS) const{
898 // Note: If additional load instructions are added here,
899 // update isLoadFromStackSlot.
900
901 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
902 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
903 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
904 DestReg), FrameIdx));
905 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
906 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
907 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
908 FrameIdx));
909 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
910 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
911 FrameIdx));
912 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
913 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
914 FrameIdx));
915 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
916 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
917 get(PPC::RESTORE_CR), DestReg),
918 FrameIdx));
919 return true;
920 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
921 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
922 get(PPC::RESTORE_CRBIT), DestReg),
923 FrameIdx));
924 return true;
925 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
926 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
927 FrameIdx));
928 NonRI = true;
929 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
930 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg),
931 FrameIdx));
932 NonRI = true;
933 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
934 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg),
935 FrameIdx));
936 NonRI = true;
937 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
938 assert(Subtarget.isDarwin() &&
939 "VRSAVE only needs spill/restore on Darwin");
940 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
941 get(PPC::RESTORE_VRSAVE),
942 DestReg),
943 FrameIdx));
944 SpillsVRS = true;
945 } else {
946 llvm_unreachable("Unknown regclass!");
947 }
948
949 return false;
950 }
951
952 void
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const953 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
954 MachineBasicBlock::iterator MI,
955 unsigned DestReg, int FrameIdx,
956 const TargetRegisterClass *RC,
957 const TargetRegisterInfo *TRI) const {
958 MachineFunction &MF = *MBB.getParent();
959 SmallVector<MachineInstr*, 4> NewMIs;
960 DebugLoc DL;
961 if (MI != MBB.end()) DL = MI->getDebugLoc();
962
963 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
964 FuncInfo->setHasSpills();
965
966 bool NonRI = false, SpillsVRS = false;
967 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
968 NonRI, SpillsVRS))
969 FuncInfo->setSpillsCR();
970
971 if (SpillsVRS)
972 FuncInfo->setSpillsVRSAVE();
973
974 if (NonRI)
975 FuncInfo->setHasNonRISpills();
976
977 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
978 MBB.insert(MI, NewMIs[i]);
979
980 const MachineFrameInfo &MFI = *MF.getFrameInfo();
981 MachineMemOperand *MMO =
982 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
983 MachineMemOperand::MOLoad,
984 MFI.getObjectSize(FrameIdx),
985 MFI.getObjectAlignment(FrameIdx));
986 NewMIs.back()->addMemOperand(MF, MMO);
987 }
988
989 bool PPCInstrInfo::
ReverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const990 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
991 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
992 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
993 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
994 else
995 // Leave the CR# the same, but invert the condition.
996 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
997 return false;
998 }
999
FoldImmediate(MachineInstr * UseMI,MachineInstr * DefMI,unsigned Reg,MachineRegisterInfo * MRI) const1000 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1001 unsigned Reg, MachineRegisterInfo *MRI) const {
1002 // For some instructions, it is legal to fold ZERO into the RA register field.
1003 // A zero immediate should always be loaded with a single li.
1004 unsigned DefOpc = DefMI->getOpcode();
1005 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1006 return false;
1007 if (!DefMI->getOperand(1).isImm())
1008 return false;
1009 if (DefMI->getOperand(1).getImm() != 0)
1010 return false;
1011
1012 // Note that we cannot here invert the arguments of an isel in order to fold
1013 // a ZERO into what is presented as the second argument. All we have here
1014 // is the condition bit, and that might come from a CR-logical bit operation.
1015
1016 const MCInstrDesc &UseMCID = UseMI->getDesc();
1017
1018 // Only fold into real machine instructions.
1019 if (UseMCID.isPseudo())
1020 return false;
1021
1022 unsigned UseIdx;
1023 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
1024 if (UseMI->getOperand(UseIdx).isReg() &&
1025 UseMI->getOperand(UseIdx).getReg() == Reg)
1026 break;
1027
1028 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
1029 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1030
1031 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1032
1033 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1034 // register (which might also be specified as a pointer class kind).
1035 if (UseInfo->isLookupPtrRegClass()) {
1036 if (UseInfo->RegClass /* Kind */ != 1)
1037 return false;
1038 } else {
1039 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1040 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1041 return false;
1042 }
1043
1044 // Make sure this is not tied to an output register (or otherwise
1045 // constrained). This is true for ST?UX registers, for example, which
1046 // are tied to their output registers.
1047 if (UseInfo->Constraints != 0)
1048 return false;
1049
1050 unsigned ZeroReg;
1051 if (UseInfo->isLookupPtrRegClass()) {
1052 bool isPPC64 = Subtarget.isPPC64();
1053 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1054 } else {
1055 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1056 PPC::ZERO8 : PPC::ZERO;
1057 }
1058
1059 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1060 UseMI->getOperand(UseIdx).setReg(ZeroReg);
1061
1062 if (DeleteDef)
1063 DefMI->eraseFromParent();
1064
1065 return true;
1066 }
1067
MBBDefinesCTR(MachineBasicBlock & MBB)1068 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1069 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1070 I != IE; ++I)
1071 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1072 return true;
1073 return false;
1074 }
1075
1076 // We should make sure that, if we're going to predicate both sides of a
1077 // condition (a diamond), that both sides don't define the counter register. We
1078 // can predicate counter-decrement-based branches, but while that predicates
1079 // the branching, it does not predicate the counter decrement. If we tried to
1080 // merge the triangle into one predicated block, we'd decrement the counter
1081 // twice.
isProfitableToIfCvt(MachineBasicBlock & TMBB,unsigned NumT,unsigned ExtraT,MachineBasicBlock & FMBB,unsigned NumF,unsigned ExtraF,const BranchProbability & Probability) const1082 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1083 unsigned NumT, unsigned ExtraT,
1084 MachineBasicBlock &FMBB,
1085 unsigned NumF, unsigned ExtraF,
1086 const BranchProbability &Probability) const {
1087 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1088 }
1089
1090
isPredicated(const MachineInstr * MI) const1091 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
1092 // The predicated branches are identified by their type, not really by the
1093 // explicit presence of a predicate. Furthermore, some of them can be
1094 // predicated more than once. Because if conversion won't try to predicate
1095 // any instruction which already claims to be predicated (by returning true
1096 // here), always return false. In doing so, we let isPredicable() be the
1097 // final word on whether not the instruction can be (further) predicated.
1098
1099 return false;
1100 }
1101
isUnpredicatedTerminator(const MachineInstr * MI) const1102 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1103 if (!MI->isTerminator())
1104 return false;
1105
1106 // Conditional branch is a special case.
1107 if (MI->isBranch() && !MI->isBarrier())
1108 return true;
1109
1110 return !isPredicated(MI);
1111 }
1112
PredicateInstruction(MachineInstr * MI,const SmallVectorImpl<MachineOperand> & Pred) const1113 bool PPCInstrInfo::PredicateInstruction(
1114 MachineInstr *MI,
1115 const SmallVectorImpl<MachineOperand> &Pred) const {
1116 unsigned OpC = MI->getOpcode();
1117 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1118 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1119 bool isPPC64 = Subtarget.isPPC64();
1120 MI->setDesc(get(Pred[0].getImm() ?
1121 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1122 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1123 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1124 MI->setDesc(get(PPC::BCLR));
1125 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1126 .addReg(Pred[1].getReg());
1127 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1128 MI->setDesc(get(PPC::BCLRn));
1129 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1130 .addReg(Pred[1].getReg());
1131 } else {
1132 MI->setDesc(get(PPC::BCCLR));
1133 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1134 .addImm(Pred[0].getImm())
1135 .addReg(Pred[1].getReg());
1136 }
1137
1138 return true;
1139 } else if (OpC == PPC::B) {
1140 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1141 bool isPPC64 = Subtarget.isPPC64();
1142 MI->setDesc(get(Pred[0].getImm() ?
1143 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1144 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1145 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1146 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1147 MI->RemoveOperand(0);
1148
1149 MI->setDesc(get(PPC::BC));
1150 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1151 .addReg(Pred[1].getReg())
1152 .addMBB(MBB);
1153 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1154 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1155 MI->RemoveOperand(0);
1156
1157 MI->setDesc(get(PPC::BCn));
1158 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1159 .addReg(Pred[1].getReg())
1160 .addMBB(MBB);
1161 } else {
1162 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1163 MI->RemoveOperand(0);
1164
1165 MI->setDesc(get(PPC::BCC));
1166 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1167 .addImm(Pred[0].getImm())
1168 .addReg(Pred[1].getReg())
1169 .addMBB(MBB);
1170 }
1171
1172 return true;
1173 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1174 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1175 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1176 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1177
1178 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1179 bool isPPC64 = Subtarget.isPPC64();
1180
1181 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1182 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1183 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1184 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1185 .addReg(Pred[1].getReg());
1186 return true;
1187 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1188 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
1189 (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1190 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1191 .addReg(Pred[1].getReg());
1192 return true;
1193 }
1194
1195 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
1196 (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1197 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1198 .addImm(Pred[0].getImm())
1199 .addReg(Pred[1].getReg());
1200 return true;
1201 }
1202
1203 return false;
1204 }
1205
SubsumesPredicate(const SmallVectorImpl<MachineOperand> & Pred1,const SmallVectorImpl<MachineOperand> & Pred2) const1206 bool PPCInstrInfo::SubsumesPredicate(
1207 const SmallVectorImpl<MachineOperand> &Pred1,
1208 const SmallVectorImpl<MachineOperand> &Pred2) const {
1209 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1210 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1211
1212 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1213 return false;
1214 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1215 return false;
1216
1217 // P1 can only subsume P2 if they test the same condition register.
1218 if (Pred1[1].getReg() != Pred2[1].getReg())
1219 return false;
1220
1221 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1222 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1223
1224 if (P1 == P2)
1225 return true;
1226
1227 // Does P1 subsume P2, e.g. GE subsumes GT.
1228 if (P1 == PPC::PRED_LE &&
1229 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1230 return true;
1231 if (P1 == PPC::PRED_GE &&
1232 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1233 return true;
1234
1235 return false;
1236 }
1237
DefinesPredicate(MachineInstr * MI,std::vector<MachineOperand> & Pred) const1238 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1239 std::vector<MachineOperand> &Pred) const {
1240 // Note: At the present time, the contents of Pred from this function is
1241 // unused by IfConversion. This implementation follows ARM by pushing the
1242 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1243 // predicate, instructions defining CTR or CTR8 are also included as
1244 // predicate-defining instructions.
1245
1246 const TargetRegisterClass *RCs[] =
1247 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1248 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1249
1250 bool Found = false;
1251 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1252 const MachineOperand &MO = MI->getOperand(i);
1253 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1254 const TargetRegisterClass *RC = RCs[c];
1255 if (MO.isReg()) {
1256 if (MO.isDef() && RC->contains(MO.getReg())) {
1257 Pred.push_back(MO);
1258 Found = true;
1259 }
1260 } else if (MO.isRegMask()) {
1261 for (TargetRegisterClass::iterator I = RC->begin(),
1262 IE = RC->end(); I != IE; ++I)
1263 if (MO.clobbersPhysReg(*I)) {
1264 Pred.push_back(MO);
1265 Found = true;
1266 }
1267 }
1268 }
1269 }
1270
1271 return Found;
1272 }
1273
isPredicable(MachineInstr * MI) const1274 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1275 unsigned OpC = MI->getOpcode();
1276 switch (OpC) {
1277 default:
1278 return false;
1279 case PPC::B:
1280 case PPC::BLR:
1281 case PPC::BLR8:
1282 case PPC::BCTR:
1283 case PPC::BCTR8:
1284 case PPC::BCTRL:
1285 case PPC::BCTRL8:
1286 return true;
1287 }
1288 }
1289
analyzeCompare(const MachineInstr * MI,unsigned & SrcReg,unsigned & SrcReg2,int & Mask,int & Value) const1290 bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
1291 unsigned &SrcReg, unsigned &SrcReg2,
1292 int &Mask, int &Value) const {
1293 unsigned Opc = MI->getOpcode();
1294
1295 switch (Opc) {
1296 default: return false;
1297 case PPC::CMPWI:
1298 case PPC::CMPLWI:
1299 case PPC::CMPDI:
1300 case PPC::CMPLDI:
1301 SrcReg = MI->getOperand(1).getReg();
1302 SrcReg2 = 0;
1303 Value = MI->getOperand(2).getImm();
1304 Mask = 0xFFFF;
1305 return true;
1306 case PPC::CMPW:
1307 case PPC::CMPLW:
1308 case PPC::CMPD:
1309 case PPC::CMPLD:
1310 case PPC::FCMPUS:
1311 case PPC::FCMPUD:
1312 SrcReg = MI->getOperand(1).getReg();
1313 SrcReg2 = MI->getOperand(2).getReg();
1314 return true;
1315 }
1316 }
1317
optimizeCompareInstr(MachineInstr * CmpInstr,unsigned SrcReg,unsigned SrcReg2,int Mask,int Value,const MachineRegisterInfo * MRI) const1318 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
1319 unsigned SrcReg, unsigned SrcReg2,
1320 int Mask, int Value,
1321 const MachineRegisterInfo *MRI) const {
1322 if (DisableCmpOpt)
1323 return false;
1324
1325 int OpC = CmpInstr->getOpcode();
1326 unsigned CRReg = CmpInstr->getOperand(0).getReg();
1327
1328 // FP record forms set CR1 based on the execption status bits, not a
1329 // comparison with zero.
1330 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1331 return false;
1332
1333 // The record forms set the condition register based on a signed comparison
1334 // with zero (so says the ISA manual). This is not as straightforward as it
1335 // seems, however, because this is always a 64-bit comparison on PPC64, even
1336 // for instructions that are 32-bit in nature (like slw for example).
1337 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1338 // for equality checks (as those don't depend on the sign). On PPC64,
1339 // we are restricted to equality for unsigned 64-bit comparisons and for
1340 // signed 32-bit comparisons the applicability is more restricted.
1341 bool isPPC64 = Subtarget.isPPC64();
1342 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1343 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1344 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1345
1346 // Get the unique definition of SrcReg.
1347 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1348 if (!MI) return false;
1349 int MIOpC = MI->getOpcode();
1350
1351 bool equalityOnly = false;
1352 bool noSub = false;
1353 if (isPPC64) {
1354 if (is32BitSignedCompare) {
1355 // We can perform this optimization only if MI is sign-extending.
1356 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1357 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1358 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1359 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1360 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1361 noSub = true;
1362 } else
1363 return false;
1364 } else if (is32BitUnsignedCompare) {
1365 // We can perform this optimization, equality only, if MI is
1366 // zero-extending.
1367 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1368 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1369 MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
1370 noSub = true;
1371 equalityOnly = true;
1372 } else
1373 return false;
1374 } else
1375 equalityOnly = is64BitUnsignedCompare;
1376 } else
1377 equalityOnly = is32BitUnsignedCompare;
1378
1379 if (equalityOnly) {
1380 // We need to check the uses of the condition register in order to reject
1381 // non-equality comparisons.
1382 for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg),
1383 IE = MRI->use_instr_end(); I != IE; ++I) {
1384 MachineInstr *UseMI = &*I;
1385 if (UseMI->getOpcode() == PPC::BCC) {
1386 unsigned Pred = UseMI->getOperand(0).getImm();
1387 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1388 return false;
1389 } else if (UseMI->getOpcode() == PPC::ISEL ||
1390 UseMI->getOpcode() == PPC::ISEL8) {
1391 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1392 if (SubIdx != PPC::sub_eq)
1393 return false;
1394 } else
1395 return false;
1396 }
1397 }
1398
1399 MachineBasicBlock::iterator I = CmpInstr;
1400
1401 // Scan forward to find the first use of the compare.
1402 for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
1403 I != EL; ++I) {
1404 bool FoundUse = false;
1405 for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg),
1406 JE = MRI->use_instr_end(); J != JE; ++J)
1407 if (&*J == &*I) {
1408 FoundUse = true;
1409 break;
1410 }
1411
1412 if (FoundUse)
1413 break;
1414 }
1415
1416 // There are two possible candidates which can be changed to set CR[01].
1417 // One is MI, the other is a SUB instruction.
1418 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1419 MachineInstr *Sub = nullptr;
1420 if (SrcReg2 != 0)
1421 // MI is not a candidate for CMPrr.
1422 MI = nullptr;
1423 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1424 // same BB as the comparison. This is to allow the check below to avoid calls
1425 // (and other explicit clobbers); instead we should really check for these
1426 // more explicitly (in at least a few predecessors).
1427 else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1428 // PPC does not have a record-form SUBri.
1429 return false;
1430 }
1431
1432 // Search for Sub.
1433 const TargetRegisterInfo *TRI = &getRegisterInfo();
1434 --I;
1435
1436 // Get ready to iterate backward from CmpInstr.
1437 MachineBasicBlock::iterator E = MI,
1438 B = CmpInstr->getParent()->begin();
1439
1440 for (; I != E && !noSub; --I) {
1441 const MachineInstr &Instr = *I;
1442 unsigned IOpC = Instr.getOpcode();
1443
1444 if (&*I != CmpInstr && (
1445 Instr.modifiesRegister(PPC::CR0, TRI) ||
1446 Instr.readsRegister(PPC::CR0, TRI)))
1447 // This instruction modifies or uses the record condition register after
1448 // the one we want to change. While we could do this transformation, it
1449 // would likely not be profitable. This transformation removes one
1450 // instruction, and so even forcing RA to generate one move probably
1451 // makes it unprofitable.
1452 return false;
1453
1454 // Check whether CmpInstr can be made redundant by the current instruction.
1455 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1456 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1457 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1458 ((Instr.getOperand(1).getReg() == SrcReg &&
1459 Instr.getOperand(2).getReg() == SrcReg2) ||
1460 (Instr.getOperand(1).getReg() == SrcReg2 &&
1461 Instr.getOperand(2).getReg() == SrcReg))) {
1462 Sub = &*I;
1463 break;
1464 }
1465
1466 if (I == B)
1467 // The 'and' is below the comparison instruction.
1468 return false;
1469 }
1470
1471 // Return false if no candidates exist.
1472 if (!MI && !Sub)
1473 return false;
1474
1475 // The single candidate is called MI.
1476 if (!MI) MI = Sub;
1477
1478 int NewOpC = -1;
1479 MIOpC = MI->getOpcode();
1480 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1481 NewOpC = MIOpC;
1482 else {
1483 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1484 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1485 NewOpC = MIOpC;
1486 }
1487
1488 // FIXME: On the non-embedded POWER architectures, only some of the record
1489 // forms are fast, and we should use only the fast ones.
1490
1491 // The defining instruction has a record form (or is already a record
1492 // form). It is possible, however, that we'll need to reverse the condition
1493 // code of the users.
1494 if (NewOpC == -1)
1495 return false;
1496
1497 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1498 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1499
1500 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1501 // needs to be updated to be based on SUB. Push the condition code
1502 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1503 // condition code of these operands will be modified.
1504 bool ShouldSwap = false;
1505 if (Sub) {
1506 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1507 Sub->getOperand(2).getReg() == SrcReg;
1508
1509 // The operands to subf are the opposite of sub, so only in the fixed-point
1510 // case, invert the order.
1511 ShouldSwap = !ShouldSwap;
1512 }
1513
1514 if (ShouldSwap)
1515 for (MachineRegisterInfo::use_instr_iterator
1516 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1517 I != IE; ++I) {
1518 MachineInstr *UseMI = &*I;
1519 if (UseMI->getOpcode() == PPC::BCC) {
1520 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1521 assert((!equalityOnly ||
1522 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1523 "Invalid predicate for equality-only optimization");
1524 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1525 PPC::getSwappedPredicate(Pred)));
1526 } else if (UseMI->getOpcode() == PPC::ISEL ||
1527 UseMI->getOpcode() == PPC::ISEL8) {
1528 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1529 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1530 "Invalid CR bit for equality-only optimization");
1531
1532 if (NewSubReg == PPC::sub_lt)
1533 NewSubReg = PPC::sub_gt;
1534 else if (NewSubReg == PPC::sub_gt)
1535 NewSubReg = PPC::sub_lt;
1536
1537 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1538 NewSubReg));
1539 } else // We need to abort on a user we don't understand.
1540 return false;
1541 }
1542
1543 // Create a new virtual register to hold the value of the CR set by the
1544 // record-form instruction. If the instruction was not previously in
1545 // record form, then set the kill flag on the CR.
1546 CmpInstr->eraseFromParent();
1547
1548 MachineBasicBlock::iterator MII = MI;
1549 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1550 get(TargetOpcode::COPY), CRReg)
1551 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1552
1553 if (MIOpC != NewOpC) {
1554 // We need to be careful here: we're replacing one instruction with
1555 // another, and we need to make sure that we get all of the right
1556 // implicit uses and defs. On the other hand, the caller may be holding
1557 // an iterator to this instruction, and so we can't delete it (this is
1558 // specifically the case if this is the instruction directly after the
1559 // compare).
1560
1561 const MCInstrDesc &NewDesc = get(NewOpC);
1562 MI->setDesc(NewDesc);
1563
1564 if (NewDesc.ImplicitDefs)
1565 for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
1566 *ImpDefs; ++ImpDefs)
1567 if (!MI->definesRegister(*ImpDefs))
1568 MI->addOperand(*MI->getParent()->getParent(),
1569 MachineOperand::CreateReg(*ImpDefs, true, true));
1570 if (NewDesc.ImplicitUses)
1571 for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
1572 *ImpUses; ++ImpUses)
1573 if (!MI->readsRegister(*ImpUses))
1574 MI->addOperand(*MI->getParent()->getParent(),
1575 MachineOperand::CreateReg(*ImpUses, false, true));
1576 }
1577
1578 // Modify the condition code of operands in OperandsToUpdate.
1579 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1580 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1581 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1582 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1583
1584 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1585 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1586
1587 return true;
1588 }
1589
1590 /// GetInstSize - Return the number of bytes of code the specified
1591 /// instruction may be. This returns the maximum number of bytes.
1592 ///
GetInstSizeInBytes(const MachineInstr * MI) const1593 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1594 unsigned Opcode = MI->getOpcode();
1595
1596 if (Opcode == PPC::INLINEASM) {
1597 const MachineFunction *MF = MI->getParent()->getParent();
1598 const char *AsmStr = MI->getOperand(0).getSymbolName();
1599 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1600 } else if (Opcode == TargetOpcode::STACKMAP) {
1601 return MI->getOperand(1).getImm();
1602 } else if (Opcode == TargetOpcode::PATCHPOINT) {
1603 PatchPointOpers Opers(MI);
1604 return Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
1605 } else {
1606 const MCInstrDesc &Desc = get(Opcode);
1607 return Desc.getSize();
1608 }
1609 }
1610
1611 #undef DEBUG_TYPE
1612 #define DEBUG_TYPE "ppc-vsx-fma-mutate"
1613
1614 namespace {
1615 // PPCVSXFMAMutate pass - For copies between VSX registers and non-VSX registers
1616 // (Altivec and scalar floating-point registers), we need to transform the
1617 // copies into subregister copies with other restrictions.
1618 struct PPCVSXFMAMutate : public MachineFunctionPass {
1619 static char ID;
PPCVSXFMAMutate__anonf7a0207f0111::PPCVSXFMAMutate1620 PPCVSXFMAMutate() : MachineFunctionPass(ID) {
1621 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
1622 }
1623
1624 LiveIntervals *LIS;
1625
1626 const PPCTargetMachine *TM;
1627 const PPCInstrInfo *TII;
1628
1629 protected:
processBlock__anonf7a0207f0111::PPCVSXFMAMutate1630 bool processBlock(MachineBasicBlock &MBB) {
1631 bool Changed = false;
1632
1633 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1634 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
1635 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1636 I != IE; ++I) {
1637 MachineInstr *MI = I;
1638
1639 // The default (A-type) VSX FMA form kills the addend (it is taken from
1640 // the target register, which is then updated to reflect the result of
1641 // the FMA). If the instruction, however, kills one of the registers
1642 // used for the product, then we can use the M-form instruction (which
1643 // will take that value from the to-be-defined register).
1644
1645 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
1646 if (AltOpc == -1)
1647 continue;
1648
1649 // This pass is run after register coalescing, and so we're looking for
1650 // a situation like this:
1651 // ...
1652 // %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
1653 // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
1654 // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
1655 // ...
1656 // %vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19,
1657 // %RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19
1658 // ...
1659 // Where we can eliminate the copy by changing from the A-type to the
1660 // M-type instruction. Specifically, for this example, this means:
1661 // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
1662 // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
1663 // is replaced by:
1664 // %vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9,
1665 // %RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9
1666 // and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
1667
1668 SlotIndex FMAIdx = LIS->getInstructionIndex(MI);
1669
1670 VNInfo *AddendValNo =
1671 LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn();
1672 MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def);
1673
1674 // The addend and this instruction must be in the same block.
1675
1676 if (!AddendMI || AddendMI->getParent() != MI->getParent())
1677 continue;
1678
1679 // The addend must be a full copy within the same register class.
1680
1681 if (!AddendMI->isFullCopy())
1682 continue;
1683
1684 unsigned AddendSrcReg = AddendMI->getOperand(1).getReg();
1685 if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg)) {
1686 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
1687 MRI.getRegClass(AddendSrcReg))
1688 continue;
1689 } else {
1690 // If AddendSrcReg is a physical register, make sure the destination
1691 // register class contains it.
1692 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
1693 ->contains(AddendSrcReg))
1694 continue;
1695 }
1696
1697 // In theory, there could be other uses of the addend copy before this
1698 // fma. We could deal with this, but that would require additional
1699 // logic below and I suspect it will not occur in any relevant
1700 // situations. Additionally, check whether the copy source is killed
1701 // prior to the fma. In order to replace the addend here with the
1702 // source of the copy, it must still be live here. We can't use
1703 // interval testing for a physical register, so as long as we're
1704 // walking the MIs we may as well test liveness here.
1705 bool OtherUsers = false, KillsAddendSrc = false;
1706 for (auto J = std::prev(I), JE = MachineBasicBlock::iterator(AddendMI);
1707 J != JE; --J) {
1708 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) {
1709 OtherUsers = true;
1710 break;
1711 }
1712 if (J->modifiesRegister(AddendSrcReg, TRI) ||
1713 J->killsRegister(AddendSrcReg, TRI)) {
1714 KillsAddendSrc = true;
1715 break;
1716 }
1717 }
1718
1719 if (OtherUsers || KillsAddendSrc)
1720 continue;
1721
1722 // Find one of the product operands that is killed by this instruction.
1723
1724 unsigned KilledProdOp = 0, OtherProdOp = 0;
1725 if (LIS->getInterval(MI->getOperand(2).getReg())
1726 .Query(FMAIdx).isKill()) {
1727 KilledProdOp = 2;
1728 OtherProdOp = 3;
1729 } else if (LIS->getInterval(MI->getOperand(3).getReg())
1730 .Query(FMAIdx).isKill()) {
1731 KilledProdOp = 3;
1732 OtherProdOp = 2;
1733 }
1734
1735 // If there are no killed product operands, then this transformation is
1736 // likely not profitable.
1737 if (!KilledProdOp)
1738 continue;
1739
1740 // For virtual registers, verify that the addend source register
1741 // is live here (as should have been assured above).
1742 assert((!TargetRegisterInfo::isVirtualRegister(AddendSrcReg) ||
1743 LIS->getInterval(AddendSrcReg).liveAt(FMAIdx)) &&
1744 "Addend source register is not live!");
1745
1746 // Transform: (O2 * O3) + O1 -> (O2 * O1) + O3.
1747
1748 unsigned AddReg = AddendMI->getOperand(1).getReg();
1749 unsigned KilledProdReg = MI->getOperand(KilledProdOp).getReg();
1750 unsigned OtherProdReg = MI->getOperand(OtherProdOp).getReg();
1751
1752 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg();
1753 unsigned KilledProdSubReg = MI->getOperand(KilledProdOp).getSubReg();
1754 unsigned OtherProdSubReg = MI->getOperand(OtherProdOp).getSubReg();
1755
1756 bool AddRegKill = AddendMI->getOperand(1).isKill();
1757 bool KilledProdRegKill = MI->getOperand(KilledProdOp).isKill();
1758 bool OtherProdRegKill = MI->getOperand(OtherProdOp).isKill();
1759
1760 bool AddRegUndef = AddendMI->getOperand(1).isUndef();
1761 bool KilledProdRegUndef = MI->getOperand(KilledProdOp).isUndef();
1762 bool OtherProdRegUndef = MI->getOperand(OtherProdOp).isUndef();
1763
1764 unsigned OldFMAReg = MI->getOperand(0).getReg();
1765
1766 // The transformation doesn't work well with things like:
1767 // %vreg5 = A-form-op %vreg5, %vreg11, %vreg5;
1768 // so leave such things alone.
1769 if (OldFMAReg == KilledProdReg)
1770 continue;
1771
1772 assert(OldFMAReg == AddendMI->getOperand(0).getReg() &&
1773 "Addend copy not tied to old FMA output!");
1774
1775 DEBUG(dbgs() << "VSX FMA Mutation:\n " << *MI;);
1776
1777 MI->getOperand(0).setReg(KilledProdReg);
1778 MI->getOperand(1).setReg(KilledProdReg);
1779 MI->getOperand(3).setReg(AddReg);
1780 MI->getOperand(2).setReg(OtherProdReg);
1781
1782 MI->getOperand(0).setSubReg(KilledProdSubReg);
1783 MI->getOperand(1).setSubReg(KilledProdSubReg);
1784 MI->getOperand(3).setSubReg(AddSubReg);
1785 MI->getOperand(2).setSubReg(OtherProdSubReg);
1786
1787 MI->getOperand(1).setIsKill(KilledProdRegKill);
1788 MI->getOperand(3).setIsKill(AddRegKill);
1789 MI->getOperand(2).setIsKill(OtherProdRegKill);
1790
1791 MI->getOperand(1).setIsUndef(KilledProdRegUndef);
1792 MI->getOperand(3).setIsUndef(AddRegUndef);
1793 MI->getOperand(2).setIsUndef(OtherProdRegUndef);
1794
1795 MI->setDesc(TII->get(AltOpc));
1796
1797 DEBUG(dbgs() << " -> " << *MI);
1798
1799 // The killed product operand was killed here, so we can reuse it now
1800 // for the result of the fma.
1801
1802 LiveInterval &FMAInt = LIS->getInterval(OldFMAReg);
1803 VNInfo *FMAValNo = FMAInt.getVNInfoAt(FMAIdx.getRegSlot());
1804 for (auto UI = MRI.reg_nodbg_begin(OldFMAReg), UE = MRI.reg_nodbg_end();
1805 UI != UE;) {
1806 MachineOperand &UseMO = *UI;
1807 MachineInstr *UseMI = UseMO.getParent();
1808 ++UI;
1809
1810 // Don't replace the result register of the copy we're about to erase.
1811 if (UseMI == AddendMI)
1812 continue;
1813
1814 UseMO.setReg(KilledProdReg);
1815 UseMO.setSubReg(KilledProdSubReg);
1816 }
1817
1818 // Extend the live intervals of the killed product operand to hold the
1819 // fma result.
1820
1821 LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg);
1822 for (LiveInterval::iterator AI = FMAInt.begin(), AE = FMAInt.end();
1823 AI != AE; ++AI) {
1824 // Don't add the segment that corresponds to the original copy.
1825 if (AI->valno == AddendValNo)
1826 continue;
1827
1828 VNInfo *NewFMAValNo =
1829 NewFMAInt.getNextValue(AI->start,
1830 LIS->getVNInfoAllocator());
1831
1832 NewFMAInt.addSegment(LiveInterval::Segment(AI->start, AI->end,
1833 NewFMAValNo));
1834 }
1835 DEBUG(dbgs() << " extended: " << NewFMAInt << '\n');
1836
1837 FMAInt.removeValNo(FMAValNo);
1838 DEBUG(dbgs() << " trimmed: " << FMAInt << '\n');
1839
1840 // Remove the (now unused) copy.
1841
1842 DEBUG(dbgs() << " removing: " << *AddendMI << '\n');
1843 LIS->RemoveMachineInstrFromMaps(AddendMI);
1844 AddendMI->eraseFromParent();
1845
1846 Changed = true;
1847 }
1848
1849 return Changed;
1850 }
1851
1852 public:
runOnMachineFunction__anonf7a0207f0111::PPCVSXFMAMutate1853 bool runOnMachineFunction(MachineFunction &MF) override {
1854 TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
1855 // If we don't have VSX then go ahead and return without doing
1856 // anything.
1857 if (!TM->getSubtargetImpl()->hasVSX())
1858 return false;
1859
1860 LIS = &getAnalysis<LiveIntervals>();
1861
1862 TII = TM->getSubtargetImpl()->getInstrInfo();
1863
1864 bool Changed = false;
1865
1866 if (DisableVSXFMAMutate)
1867 return Changed;
1868
1869 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
1870 MachineBasicBlock &B = *I++;
1871 if (processBlock(B))
1872 Changed = true;
1873 }
1874
1875 return Changed;
1876 }
1877
getAnalysisUsage__anonf7a0207f0111::PPCVSXFMAMutate1878 void getAnalysisUsage(AnalysisUsage &AU) const override {
1879 AU.addRequired<LiveIntervals>();
1880 AU.addPreserved<LiveIntervals>();
1881 AU.addRequired<SlotIndexes>();
1882 AU.addPreserved<SlotIndexes>();
1883 MachineFunctionPass::getAnalysisUsage(AU);
1884 }
1885 };
1886 }
1887
1888 INITIALIZE_PASS_BEGIN(PPCVSXFMAMutate, DEBUG_TYPE,
1889 "PowerPC VSX FMA Mutation", false, false)
1890 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
1891 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
1892 INITIALIZE_PASS_END(PPCVSXFMAMutate, DEBUG_TYPE,
1893 "PowerPC VSX FMA Mutation", false, false)
1894
1895 char &llvm::PPCVSXFMAMutateID = PPCVSXFMAMutate::ID;
1896
1897 char PPCVSXFMAMutate::ID = 0;
1898 FunctionPass*
createPPCVSXFMAMutatePass()1899 llvm::createPPCVSXFMAMutatePass() { return new PPCVSXFMAMutate(); }
1900
1901 #undef DEBUG_TYPE
1902 #define DEBUG_TYPE "ppc-vsx-copy"
1903
1904 namespace llvm {
1905 void initializePPCVSXCopyPass(PassRegistry&);
1906 }
1907
1908 namespace {
1909 // PPCVSXCopy pass - For copies between VSX registers and non-VSX registers
1910 // (Altivec and scalar floating-point registers), we need to transform the
1911 // copies into subregister copies with other restrictions.
1912 struct PPCVSXCopy : public MachineFunctionPass {
1913 static char ID;
PPCVSXCopy__anonf7a0207f0211::PPCVSXCopy1914 PPCVSXCopy() : MachineFunctionPass(ID) {
1915 initializePPCVSXCopyPass(*PassRegistry::getPassRegistry());
1916 }
1917
1918 const PPCTargetMachine *TM;
1919 const PPCInstrInfo *TII;
1920
IsRegInClass__anonf7a0207f0211::PPCVSXCopy1921 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC,
1922 MachineRegisterInfo &MRI) {
1923 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1924 return RC->hasSubClassEq(MRI.getRegClass(Reg));
1925 } else if (RC->contains(Reg)) {
1926 return true;
1927 }
1928
1929 return false;
1930 }
1931
IsVSReg__anonf7a0207f0211::PPCVSXCopy1932 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) {
1933 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI);
1934 }
1935
IsVRReg__anonf7a0207f0211::PPCVSXCopy1936 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) {
1937 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI);
1938 }
1939
IsF8Reg__anonf7a0207f0211::PPCVSXCopy1940 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) {
1941 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI);
1942 }
1943
1944 protected:
processBlock__anonf7a0207f0211::PPCVSXCopy1945 bool processBlock(MachineBasicBlock &MBB) {
1946 bool Changed = false;
1947
1948 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1949 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1950 I != IE; ++I) {
1951 MachineInstr *MI = I;
1952 if (!MI->isFullCopy())
1953 continue;
1954
1955 MachineOperand &DstMO = MI->getOperand(0);
1956 MachineOperand &SrcMO = MI->getOperand(1);
1957
1958 if ( IsVSReg(DstMO.getReg(), MRI) &&
1959 !IsVSReg(SrcMO.getReg(), MRI)) {
1960 // This is a copy *to* a VSX register from a non-VSX register.
1961 Changed = true;
1962
1963 const TargetRegisterClass *SrcRC =
1964 IsVRReg(SrcMO.getReg(), MRI) ? &PPC::VSHRCRegClass :
1965 &PPC::VSLRCRegClass;
1966 assert((IsF8Reg(SrcMO.getReg(), MRI) ||
1967 IsVRReg(SrcMO.getReg(), MRI)) &&
1968 "Unknown source for a VSX copy");
1969
1970 unsigned NewVReg = MRI.createVirtualRegister(SrcRC);
1971 BuildMI(MBB, MI, MI->getDebugLoc(),
1972 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg)
1973 .addImm(1) // add 1, not 0, because there is no implicit clearing
1974 // of the high bits.
1975 .addOperand(SrcMO)
1976 .addImm(IsVRReg(SrcMO.getReg(), MRI) ? PPC::sub_128 :
1977 PPC::sub_64);
1978
1979 // The source of the original copy is now the new virtual register.
1980 SrcMO.setReg(NewVReg);
1981 } else if (!IsVSReg(DstMO.getReg(), MRI) &&
1982 IsVSReg(SrcMO.getReg(), MRI)) {
1983 // This is a copy *from* a VSX register to a non-VSX register.
1984 Changed = true;
1985
1986 const TargetRegisterClass *DstRC =
1987 IsVRReg(DstMO.getReg(), MRI) ? &PPC::VSHRCRegClass :
1988 &PPC::VSLRCRegClass;
1989 assert((IsF8Reg(DstMO.getReg(), MRI) ||
1990 IsVRReg(DstMO.getReg(), MRI)) &&
1991 "Unknown destination for a VSX copy");
1992
1993 // Copy the VSX value into a new VSX register of the correct subclass.
1994 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
1995 BuildMI(MBB, MI, MI->getDebugLoc(),
1996 TII->get(TargetOpcode::COPY), NewVReg)
1997 .addOperand(SrcMO);
1998
1999 // Transform the original copy into a subregister extraction copy.
2000 SrcMO.setReg(NewVReg);
2001 SrcMO.setSubReg(IsVRReg(DstMO.getReg(), MRI) ? PPC::sub_128 :
2002 PPC::sub_64);
2003 }
2004 }
2005
2006 return Changed;
2007 }
2008
2009 public:
runOnMachineFunction__anonf7a0207f0211::PPCVSXCopy2010 bool runOnMachineFunction(MachineFunction &MF) override {
2011 TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
2012 // If we don't have VSX on the subtarget, don't do anything.
2013 if (!TM->getSubtargetImpl()->hasVSX())
2014 return false;
2015 TII = TM->getSubtargetImpl()->getInstrInfo();
2016
2017 bool Changed = false;
2018
2019 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
2020 MachineBasicBlock &B = *I++;
2021 if (processBlock(B))
2022 Changed = true;
2023 }
2024
2025 return Changed;
2026 }
2027
getAnalysisUsage__anonf7a0207f0211::PPCVSXCopy2028 void getAnalysisUsage(AnalysisUsage &AU) const override {
2029 MachineFunctionPass::getAnalysisUsage(AU);
2030 }
2031 };
2032 }
2033
2034 INITIALIZE_PASS(PPCVSXCopy, DEBUG_TYPE,
2035 "PowerPC VSX Copy Legalization", false, false)
2036
2037 char PPCVSXCopy::ID = 0;
2038 FunctionPass*
createPPCVSXCopyPass()2039 llvm::createPPCVSXCopyPass() { return new PPCVSXCopy(); }
2040
2041 #undef DEBUG_TYPE
2042 #define DEBUG_TYPE "ppc-vsx-copy-cleanup"
2043
2044 namespace llvm {
2045 void initializePPCVSXCopyCleanupPass(PassRegistry&);
2046 }
2047
2048 namespace {
2049 // PPCVSXCopyCleanup pass - We sometimes end up generating self copies of VSX
2050 // registers (mostly because the ABI code still places all values into the
2051 // "traditional" floating-point and vector registers). Remove them here.
2052 struct PPCVSXCopyCleanup : public MachineFunctionPass {
2053 static char ID;
PPCVSXCopyCleanup__anonf7a0207f0311::PPCVSXCopyCleanup2054 PPCVSXCopyCleanup() : MachineFunctionPass(ID) {
2055 initializePPCVSXCopyCleanupPass(*PassRegistry::getPassRegistry());
2056 }
2057
2058 const PPCTargetMachine *TM;
2059 const PPCInstrInfo *TII;
2060
2061 protected:
processBlock__anonf7a0207f0311::PPCVSXCopyCleanup2062 bool processBlock(MachineBasicBlock &MBB) {
2063 bool Changed = false;
2064
2065 SmallVector<MachineInstr *, 4> ToDelete;
2066 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
2067 I != IE; ++I) {
2068 MachineInstr *MI = I;
2069 if (MI->getOpcode() == PPC::XXLOR &&
2070 MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
2071 MI->getOperand(0).getReg() == MI->getOperand(2).getReg())
2072 ToDelete.push_back(MI);
2073 }
2074
2075 if (!ToDelete.empty())
2076 Changed = true;
2077
2078 for (unsigned i = 0, ie = ToDelete.size(); i != ie; ++i) {
2079 DEBUG(dbgs() << "Removing VSX self-copy: " << *ToDelete[i]);
2080 ToDelete[i]->eraseFromParent();
2081 }
2082
2083 return Changed;
2084 }
2085
2086 public:
runOnMachineFunction__anonf7a0207f0311::PPCVSXCopyCleanup2087 bool runOnMachineFunction(MachineFunction &MF) override {
2088 TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
2089 // If we don't have VSX don't bother doing anything here.
2090 if (!TM->getSubtargetImpl()->hasVSX())
2091 return false;
2092 TII = TM->getSubtargetImpl()->getInstrInfo();
2093
2094 bool Changed = false;
2095
2096 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
2097 MachineBasicBlock &B = *I++;
2098 if (processBlock(B))
2099 Changed = true;
2100 }
2101
2102 return Changed;
2103 }
2104
getAnalysisUsage__anonf7a0207f0311::PPCVSXCopyCleanup2105 void getAnalysisUsage(AnalysisUsage &AU) const override {
2106 MachineFunctionPass::getAnalysisUsage(AU);
2107 }
2108 };
2109 }
2110
2111 INITIALIZE_PASS(PPCVSXCopyCleanup, DEBUG_TYPE,
2112 "PowerPC VSX Copy Cleanup", false, false)
2113
2114 char PPCVSXCopyCleanup::ID = 0;
2115 FunctionPass*
createPPCVSXCopyCleanupPass()2116 llvm::createPPCVSXCopyCleanupPass() { return new PPCVSXCopyCleanup(); }
2117
2118 #undef DEBUG_TYPE
2119 #define DEBUG_TYPE "ppc-early-ret"
2120 STATISTIC(NumBCLR, "Number of early conditional returns");
2121 STATISTIC(NumBLR, "Number of early returns");
2122
2123 namespace llvm {
2124 void initializePPCEarlyReturnPass(PassRegistry&);
2125 }
2126
2127 namespace {
2128 // PPCEarlyReturn pass - For simple functions without epilogue code, move
2129 // returns up, and create conditional returns, to avoid unnecessary
2130 // branch-to-blr sequences.
2131 struct PPCEarlyReturn : public MachineFunctionPass {
2132 static char ID;
PPCEarlyReturn__anonf7a0207f0411::PPCEarlyReturn2133 PPCEarlyReturn() : MachineFunctionPass(ID) {
2134 initializePPCEarlyReturnPass(*PassRegistry::getPassRegistry());
2135 }
2136
2137 const PPCTargetMachine *TM;
2138 const PPCInstrInfo *TII;
2139
2140 protected:
processBlock__anonf7a0207f0411::PPCEarlyReturn2141 bool processBlock(MachineBasicBlock &ReturnMBB) {
2142 bool Changed = false;
2143
2144 MachineBasicBlock::iterator I = ReturnMBB.begin();
2145 I = ReturnMBB.SkipPHIsAndLabels(I);
2146
2147 // The block must be essentially empty except for the blr.
2148 if (I == ReturnMBB.end() ||
2149 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
2150 I != ReturnMBB.getLastNonDebugInstr())
2151 return Changed;
2152
2153 SmallVector<MachineBasicBlock*, 8> PredToRemove;
2154 for (MachineBasicBlock::pred_iterator PI = ReturnMBB.pred_begin(),
2155 PIE = ReturnMBB.pred_end(); PI != PIE; ++PI) {
2156 bool OtherReference = false, BlockChanged = false;
2157 for (MachineBasicBlock::iterator J = (*PI)->getLastNonDebugInstr();;) {
2158 if (J->getOpcode() == PPC::B) {
2159 if (J->getOperand(0).getMBB() == &ReturnMBB) {
2160 // This is an unconditional branch to the return. Replace the
2161 // branch with a blr.
2162 BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()));
2163 MachineBasicBlock::iterator K = J--;
2164 K->eraseFromParent();
2165 BlockChanged = true;
2166 ++NumBLR;
2167 continue;
2168 }
2169 } else if (J->getOpcode() == PPC::BCC) {
2170 if (J->getOperand(2).getMBB() == &ReturnMBB) {
2171 // This is a conditional branch to the return. Replace the branch
2172 // with a bclr.
2173 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
2174 .addImm(J->getOperand(0).getImm())
2175 .addReg(J->getOperand(1).getReg());
2176 MachineBasicBlock::iterator K = J--;
2177 K->eraseFromParent();
2178 BlockChanged = true;
2179 ++NumBCLR;
2180 continue;
2181 }
2182 } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) {
2183 if (J->getOperand(1).getMBB() == &ReturnMBB) {
2184 // This is a conditional branch to the return. Replace the branch
2185 // with a bclr.
2186 BuildMI(**PI, J, J->getDebugLoc(),
2187 TII->get(J->getOpcode() == PPC::BC ?
2188 PPC::BCLR : PPC::BCLRn))
2189 .addReg(J->getOperand(0).getReg());
2190 MachineBasicBlock::iterator K = J--;
2191 K->eraseFromParent();
2192 BlockChanged = true;
2193 ++NumBCLR;
2194 continue;
2195 }
2196 } else if (J->isBranch()) {
2197 if (J->isIndirectBranch()) {
2198 if (ReturnMBB.hasAddressTaken())
2199 OtherReference = true;
2200 } else
2201 for (unsigned i = 0; i < J->getNumOperands(); ++i)
2202 if (J->getOperand(i).isMBB() &&
2203 J->getOperand(i).getMBB() == &ReturnMBB)
2204 OtherReference = true;
2205 } else if (!J->isTerminator() && !J->isDebugValue())
2206 break;
2207
2208 if (J == (*PI)->begin())
2209 break;
2210
2211 --J;
2212 }
2213
2214 if ((*PI)->canFallThrough() && (*PI)->isLayoutSuccessor(&ReturnMBB))
2215 OtherReference = true;
2216
2217 // Predecessors are stored in a vector and can't be removed here.
2218 if (!OtherReference && BlockChanged) {
2219 PredToRemove.push_back(*PI);
2220 }
2221
2222 if (BlockChanged)
2223 Changed = true;
2224 }
2225
2226 for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i)
2227 PredToRemove[i]->removeSuccessor(&ReturnMBB);
2228
2229 if (Changed && !ReturnMBB.hasAddressTaken()) {
2230 // We now might be able to merge this blr-only block into its
2231 // by-layout predecessor.
2232 if (ReturnMBB.pred_size() == 1 &&
2233 (*ReturnMBB.pred_begin())->isLayoutSuccessor(&ReturnMBB)) {
2234 // Move the blr into the preceding block.
2235 MachineBasicBlock &PrevMBB = **ReturnMBB.pred_begin();
2236 PrevMBB.splice(PrevMBB.end(), &ReturnMBB, I);
2237 PrevMBB.removeSuccessor(&ReturnMBB);
2238 }
2239
2240 if (ReturnMBB.pred_empty())
2241 ReturnMBB.eraseFromParent();
2242 }
2243
2244 return Changed;
2245 }
2246
2247 public:
runOnMachineFunction__anonf7a0207f0411::PPCEarlyReturn2248 bool runOnMachineFunction(MachineFunction &MF) override {
2249 TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
2250 TII = TM->getSubtargetImpl()->getInstrInfo();
2251
2252 bool Changed = false;
2253
2254 // If the function does not have at least two blocks, then there is
2255 // nothing to do.
2256 if (MF.size() < 2)
2257 return Changed;
2258
2259 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
2260 MachineBasicBlock &B = *I++;
2261 if (processBlock(B))
2262 Changed = true;
2263 }
2264
2265 return Changed;
2266 }
2267
getAnalysisUsage__anonf7a0207f0411::PPCEarlyReturn2268 void getAnalysisUsage(AnalysisUsage &AU) const override {
2269 MachineFunctionPass::getAnalysisUsage(AU);
2270 }
2271 };
2272 }
2273
2274 INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
2275 "PowerPC Early-Return Creation", false, false)
2276
2277 char PPCEarlyReturn::ID = 0;
2278 FunctionPass*
createPPCEarlyReturnPass()2279 llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }
2280