1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the Machinelegalizer class for 10 /// AMDGPU. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 16 17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class GCNTargetMachine; 24 class LLVMContext; 25 class GCNSubtarget; 26 class MachineIRBuilder; 27 28 namespace AMDGPU { 29 struct ImageDimIntrinsicInfo; 30 } 31 /// This class provides the information for the target register banks. 32 class AMDGPULegalizerInfo final : public LegalizerInfo { 33 const GCNSubtarget &ST; 34 35 public: 36 AMDGPULegalizerInfo(const GCNSubtarget &ST, 37 const GCNTargetMachine &TM); 38 39 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override; 40 41 Register getSegmentAperture(unsigned AddrSpace, 42 MachineRegisterInfo &MRI, 43 MachineIRBuilder &B) const; 44 45 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, 46 MachineIRBuilder &B) const; 47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, 48 MachineIRBuilder &B) const; 49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, 50 MachineIRBuilder &B) const; 51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI, 52 MachineIRBuilder &B) const; 53 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, 54 MachineIRBuilder &B) const; 55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, 56 MachineIRBuilder &B, bool Signed) const; 57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, 58 MachineIRBuilder &B, bool Signed) const; 59 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const; 60 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 61 MachineIRBuilder &B) const; 62 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 63 MachineIRBuilder &B) const; 64 bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI, 65 MachineIRBuilder &B) const; 66 67 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, 68 MachineIRBuilder &B) const; 69 70 bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, 71 const GlobalValue *GV, int64_t Offset, 72 unsigned GAFlags = SIInstrInfo::MO_NONE) const; 73 74 bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, 75 MachineIRBuilder &B) const; 76 bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const; 77 78 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, 79 MachineIRBuilder &B) const; 80 81 bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, 82 MachineIRBuilder &B) const; 83 bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, 84 double Log2BaseInverted) const; 85 bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const; 86 bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const; 87 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, 88 MachineIRBuilder &B) const; 89 90 bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, 91 MachineIRBuilder &B) const; 92 93 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 94 const ArgDescriptor *Arg, 95 const TargetRegisterClass *ArgRC, LLT ArgTy) const; 96 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 97 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 98 bool legalizePreloadedArgIntrin( 99 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, 100 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 101 102 bool legalizeUDIV_UREM(MachineInstr &MI, MachineRegisterInfo &MRI, 103 MachineIRBuilder &B) const; 104 105 void legalizeUDIV_UREM32Impl(MachineIRBuilder &B, 106 Register DstReg, Register Num, Register Den, 107 bool IsRem) const; 108 109 void legalizeUDIV_UREM64Impl(MachineIRBuilder &B, 110 Register DstReg, Register Numer, Register Denom, 111 bool IsDiv) const; 112 113 bool legalizeUDIV_UREM64(MachineInstr &MI, MachineRegisterInfo &MRI, 114 MachineIRBuilder &B) const; 115 bool legalizeSDIV_SREM(MachineInstr &MI, MachineRegisterInfo &MRI, 116 MachineIRBuilder &B) const; 117 118 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 119 MachineIRBuilder &B) const; 120 bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, 121 MachineIRBuilder &B) const; 122 bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, 123 MachineIRBuilder &B) const; 124 bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, 125 MachineIRBuilder &B) const; 126 bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 127 MachineIRBuilder &B) const; 128 bool legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, 129 MachineIRBuilder &B) const; 130 bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, 131 MachineIRBuilder &B) const; 132 133 bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 134 MachineIRBuilder &B) const; 135 136 bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper, 137 MachineInstr &MI, Intrinsic::ID IID) const; 138 139 bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI, 140 MachineIRBuilder &B) const; 141 142 bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, 143 MachineIRBuilder &B) const; 144 bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, 145 MachineIRBuilder &B, unsigned AddrSpace) const; 146 147 std::tuple<Register, unsigned, unsigned> 148 splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const; 149 150 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 151 Register Reg, bool ImageStore = false) const; 152 bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 153 MachineIRBuilder &B, bool IsFormat) const; 154 bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 155 MachineIRBuilder &B, bool IsFormat) const; 156 Register fixStoreSourceType(MachineIRBuilder &B, Register VData, 157 bool IsFormat) const; 158 159 bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 160 MachineIRBuilder &B, bool IsTyped, 161 bool IsFormat) const; 162 bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 163 MachineIRBuilder &B, bool IsFormat, 164 bool IsTyped) const; 165 bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, 166 Intrinsic::ID IID) const; 167 168 bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const; 169 170 bool legalizeImageIntrinsic( 171 MachineInstr &MI, MachineIRBuilder &B, 172 GISelChangeObserver &Observer, 173 const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const; 174 175 bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const; 176 177 bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, 178 bool IsInc) const; 179 180 bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 181 MachineIRBuilder &B) const; 182 bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI, 183 MachineIRBuilder &B) const; 184 bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI, 185 MachineIRBuilder &B) const; 186 bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI, 187 MachineIRBuilder &B) const; 188 bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 189 MachineIRBuilder &B) const; 190 191 bool legalizeIntrinsic(LegalizerHelper &Helper, 192 MachineInstr &MI) const override; 193 }; 194 } // End llvm namespace. 195 #endif 196