1@c Copyright (C) 1991-2020 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@c man end 5 6@ifset GENERIC 7@page 8@node i386-Dependent 9@chapter 80386 Dependent Features 10@end ifset 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter 80386 Dependent Features 14@end ifclear 15 16@cindex i386 support 17@cindex i80386 support 18@cindex x86-64 support 19 20The i386 version @code{@value{AS}} supports both the original Intel 386 21architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture 22extending the Intel architecture to 64-bits. 23 24@menu 25* i386-Options:: Options 26* i386-Directives:: X86 specific directives 27* i386-Syntax:: Syntactical considerations 28* i386-Mnemonics:: Instruction Naming 29* i386-Regs:: Register Naming 30* i386-Prefixes:: Instruction Prefixes 31* i386-Memory:: Memory References 32* i386-Jumps:: Handling of Jump Instructions 33* i386-Float:: Floating Point 34* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 35* i386-LWP:: AMD's Lightweight Profiling Instructions 36* i386-BMI:: Bit Manipulation Instruction 37* i386-TBM:: AMD's Trailing Bit Manipulation Instructions 38* i386-16bit:: Writing 16-bit Code 39* i386-Arch:: Specifying an x86 CPU architecture 40* i386-Bugs:: AT&T Syntax bugs 41* i386-Notes:: Notes 42@end menu 43 44@node i386-Options 45@section Options 46 47@cindex options for i386 48@cindex options for x86-64 49@cindex i386 options 50@cindex x86-64 options 51 52The i386 version of @code{@value{AS}} has a few machine 53dependent options: 54 55@c man begin OPTIONS 56@table @gcctabopt 57@cindex @samp{--32} option, i386 58@cindex @samp{--32} option, x86-64 59@cindex @samp{--x32} option, i386 60@cindex @samp{--x32} option, x86-64 61@cindex @samp{--64} option, i386 62@cindex @samp{--64} option, x86-64 63@item --32 | --x32 | --64 64Select the word size, either 32 bits or 64 bits. @samp{--32} 65implies Intel i386 architecture, while @samp{--x32} and @samp{--64} 66imply AMD x86-64 architecture with 32-bit or 64-bit word-size 67respectively. 68 69These options are only available with the ELF object file format, and 70require that the necessary BFD support has been included (on a 32-bit 71platform you have to add --enable-64-bit-bfd to configure enable 64-bit 72usage and use x86-64 as target platform). 73 74@item -n 75By default, x86 GAS replaces multiple nop instructions used for 76alignment within code sections with multi-byte nop instructions such 77as leal 0(%esi,1),%esi. This switch disables the optimization if a single 78byte nop (0x90) is explicitly specified as the fill byte for alignment. 79 80@cindex @samp{--divide} option, i386 81@item --divide 82On SVR4-derived platforms, the character @samp{/} is treated as a comment 83character, which means that it cannot be used in expressions. The 84@samp{--divide} option turns @samp{/} into a normal character. This does 85not disable @samp{/} at the beginning of a line starting a comment, or 86affect using @samp{#} for starting a comment. 87 88@cindex @samp{-march=} option, i386 89@cindex @samp{-march=} option, x86-64 90@item -march=@var{CPU}[+@var{EXTENSION}@dots{}] 91This option specifies the target processor. The assembler will 92issue an error message if an attempt is made to assemble an instruction 93which will not execute on the target processor. The following 94processor names are recognized: 95@code{i8086}, 96@code{i186}, 97@code{i286}, 98@code{i386}, 99@code{i486}, 100@code{i586}, 101@code{i686}, 102@code{pentium}, 103@code{pentiumpro}, 104@code{pentiumii}, 105@code{pentiumiii}, 106@code{pentium4}, 107@code{prescott}, 108@code{nocona}, 109@code{core}, 110@code{core2}, 111@code{corei7}, 112@code{l1om}, 113@code{k1om}, 114@code{iamcu}, 115@code{k6}, 116@code{k6_2}, 117@code{athlon}, 118@code{opteron}, 119@code{k8}, 120@code{amdfam10}, 121@code{bdver1}, 122@code{bdver2}, 123@code{bdver3}, 124@code{bdver4}, 125@code{znver1}, 126@code{znver2}, 127@code{btver1}, 128@code{btver2}, 129@code{generic32} and 130@code{generic64}. 131 132In addition to the basic instruction set, the assembler can be told to 133accept various extension mnemonics. For example, 134@code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and 135@var{vmx}. The following extensions are currently supported: 136@code{8087}, 137@code{287}, 138@code{387}, 139@code{687}, 140@code{no87}, 141@code{no287}, 142@code{no387}, 143@code{no687}, 144@code{cmov}, 145@code{nocmov}, 146@code{fxsr}, 147@code{nofxsr}, 148@code{mmx}, 149@code{nommx}, 150@code{sse}, 151@code{sse2}, 152@code{sse3}, 153@code{ssse3}, 154@code{sse4.1}, 155@code{sse4.2}, 156@code{sse4}, 157@code{nosse}, 158@code{nosse2}, 159@code{nosse3}, 160@code{nossse3}, 161@code{nosse4.1}, 162@code{nosse4.2}, 163@code{nosse4}, 164@code{avx}, 165@code{avx2}, 166@code{noavx}, 167@code{noavx2}, 168@code{adx}, 169@code{rdseed}, 170@code{prfchw}, 171@code{smap}, 172@code{mpx}, 173@code{sha}, 174@code{rdpid}, 175@code{ptwrite}, 176@code{cet}, 177@code{gfni}, 178@code{vaes}, 179@code{vpclmulqdq}, 180@code{prefetchwt1}, 181@code{clflushopt}, 182@code{se1}, 183@code{clwb}, 184@code{movdiri}, 185@code{movdir64b}, 186@code{enqcmd}, 187@code{avx512f}, 188@code{avx512cd}, 189@code{avx512er}, 190@code{avx512pf}, 191@code{avx512vl}, 192@code{avx512bw}, 193@code{avx512dq}, 194@code{avx512ifma}, 195@code{avx512vbmi}, 196@code{avx512_4fmaps}, 197@code{avx512_4vnniw}, 198@code{avx512_vpopcntdq}, 199@code{avx512_vbmi2}, 200@code{avx512_vnni}, 201@code{avx512_bitalg}, 202@code{avx512_bf16}, 203@code{noavx512f}, 204@code{noavx512cd}, 205@code{noavx512er}, 206@code{noavx512pf}, 207@code{noavx512vl}, 208@code{noavx512bw}, 209@code{noavx512dq}, 210@code{noavx512ifma}, 211@code{noavx512vbmi}, 212@code{noavx512_4fmaps}, 213@code{noavx512_4vnniw}, 214@code{noavx512_vpopcntdq}, 215@code{noavx512_vbmi2}, 216@code{noavx512_vnni}, 217@code{noavx512_bitalg}, 218@code{noavx512_vp2intersect}, 219@code{noavx512_bf16}, 220@code{noenqcmd}, 221@code{vmx}, 222@code{vmfunc}, 223@code{smx}, 224@code{xsave}, 225@code{xsaveopt}, 226@code{xsavec}, 227@code{xsaves}, 228@code{aes}, 229@code{pclmul}, 230@code{fsgsbase}, 231@code{rdrnd}, 232@code{f16c}, 233@code{bmi2}, 234@code{fma}, 235@code{movbe}, 236@code{ept}, 237@code{lzcnt}, 238@code{hle}, 239@code{rtm}, 240@code{invpcid}, 241@code{clflush}, 242@code{mwaitx}, 243@code{clzero}, 244@code{wbnoinvd}, 245@code{pconfig}, 246@code{waitpkg}, 247@code{cldemote}, 248@code{rdpru}, 249@code{mcommit}, 250@code{lwp}, 251@code{fma4}, 252@code{xop}, 253@code{cx16}, 254@code{syscall}, 255@code{rdtscp}, 256@code{3dnow}, 257@code{3dnowa}, 258@code{sse4a}, 259@code{sse5}, 260@code{svme}, 261@code{abm} and 262@code{padlock}. 263Note that rather than extending a basic instruction set, the extension 264mnemonics starting with @code{no} revoke the respective functionality. 265 266When the @code{.arch} directive is used with @option{-march}, the 267@code{.arch} directive will take precedent. 268 269@cindex @samp{-mtune=} option, i386 270@cindex @samp{-mtune=} option, x86-64 271@item -mtune=@var{CPU} 272This option specifies a processor to optimize for. When used in 273conjunction with the @option{-march} option, only instructions 274of the processor specified by the @option{-march} option will be 275generated. 276 277Valid @var{CPU} values are identical to the processor list of 278@option{-march=@var{CPU}}. 279 280@cindex @samp{-msse2avx} option, i386 281@cindex @samp{-msse2avx} option, x86-64 282@item -msse2avx 283This option specifies that the assembler should encode SSE instructions 284with VEX prefix. 285 286@cindex @samp{-msse-check=} option, i386 287@cindex @samp{-msse-check=} option, x86-64 288@item -msse-check=@var{none} 289@itemx -msse-check=@var{warning} 290@itemx -msse-check=@var{error} 291These options control if the assembler should check SSE instructions. 292@option{-msse-check=@var{none}} will make the assembler not to check SSE 293instructions, which is the default. @option{-msse-check=@var{warning}} 294will make the assembler issue a warning for any SSE instruction. 295@option{-msse-check=@var{error}} will make the assembler issue an error 296for any SSE instruction. 297 298@cindex @samp{-mavxscalar=} option, i386 299@cindex @samp{-mavxscalar=} option, x86-64 300@item -mavxscalar=@var{128} 301@itemx -mavxscalar=@var{256} 302These options control how the assembler should encode scalar AVX 303instructions. @option{-mavxscalar=@var{128}} will encode scalar 304AVX instructions with 128bit vector length, which is the default. 305@option{-mavxscalar=@var{256}} will encode scalar AVX instructions 306with 256bit vector length. 307 308WARNING: Don't use this for production code - due to CPU errata the 309resulting code may not work on certain models. 310 311@cindex @samp{-mvexwig=} option, i386 312@cindex @samp{-mvexwig=} option, x86-64 313@item -mvexwig=@var{0} 314@itemx -mvexwig=@var{1} 315These options control how the assembler should encode VEX.W-ignored (WIG) 316VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX 317instructions with vex.w = 0, which is the default. 318@option{-mvexwig=@var{1}} will encode WIG EVEX instructions with 319vex.w = 1. 320 321WARNING: Don't use this for production code - due to CPU errata the 322resulting code may not work on certain models. 323 324@cindex @samp{-mevexlig=} option, i386 325@cindex @samp{-mevexlig=} option, x86-64 326@item -mevexlig=@var{128} 327@itemx -mevexlig=@var{256} 328@itemx -mevexlig=@var{512} 329These options control how the assembler should encode length-ignored 330(LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG 331EVEX instructions with 128bit vector length, which is the default. 332@option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will 333encode LIG EVEX instructions with 256bit and 512bit vector length, 334respectively. 335 336@cindex @samp{-mevexwig=} option, i386 337@cindex @samp{-mevexwig=} option, x86-64 338@item -mevexwig=@var{0} 339@itemx -mevexwig=@var{1} 340These options control how the assembler should encode w-ignored (WIG) 341EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG 342EVEX instructions with evex.w = 0, which is the default. 343@option{-mevexwig=@var{1}} will encode WIG EVEX instructions with 344evex.w = 1. 345 346@cindex @samp{-mmnemonic=} option, i386 347@cindex @samp{-mmnemonic=} option, x86-64 348@item -mmnemonic=@var{att} 349@itemx -mmnemonic=@var{intel} 350This option specifies instruction mnemonic for matching instructions. 351The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will 352take precedent. 353 354@cindex @samp{-msyntax=} option, i386 355@cindex @samp{-msyntax=} option, x86-64 356@item -msyntax=@var{att} 357@itemx -msyntax=@var{intel} 358This option specifies instruction syntax when processing instructions. 359The @code{.att_syntax} and @code{.intel_syntax} directives will 360take precedent. 361 362@cindex @samp{-mnaked-reg} option, i386 363@cindex @samp{-mnaked-reg} option, x86-64 364@item -mnaked-reg 365This option specifies that registers don't require a @samp{%} prefix. 366The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. 367 368@cindex @samp{-madd-bnd-prefix} option, i386 369@cindex @samp{-madd-bnd-prefix} option, x86-64 370@item -madd-bnd-prefix 371This option forces the assembler to add BND prefix to all branches, even 372if such prefix was not explicitly specified in the source code. 373 374@cindex @samp{-mshared} option, i386 375@cindex @samp{-mshared} option, x86-64 376@item -mno-shared 377On ELF target, the assembler normally optimizes out non-PLT relocations 378against defined non-weak global branch targets with default visibility. 379The @samp{-mshared} option tells the assembler to generate code which 380may go into a shared library where all non-weak global branch targets 381with default visibility can be preempted. The resulting code is 382slightly bigger. This option only affects the handling of branch 383instructions. 384 385@cindex @samp{-mbig-obj} option, x86-64 386@item -mbig-obj 387On x86-64 PE/COFF target this option forces the use of big object file 388format, which allows more than 32768 sections. 389 390@cindex @samp{-momit-lock-prefix=} option, i386 391@cindex @samp{-momit-lock-prefix=} option, x86-64 392@item -momit-lock-prefix=@var{no} 393@itemx -momit-lock-prefix=@var{yes} 394These options control how the assembler should encode lock prefix. 395This option is intended as a workaround for processors, that fail on 396lock prefix. This option can only be safely used with single-core, 397single-thread computers 398@option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes. 399@option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, 400which is the default. 401 402@cindex @samp{-mfence-as-lock-add=} option, i386 403@cindex @samp{-mfence-as-lock-add=} option, x86-64 404@item -mfence-as-lock-add=@var{no} 405@itemx -mfence-as-lock-add=@var{yes} 406These options control how the assembler should encode lfence, mfence and 407sfence. 408@option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and 409sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and 410@samp{lock addl $0x0, (%esp)} in 32-bit mode. 411@option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and 412sfence as usual, which is the default. 413 414@cindex @samp{-mrelax-relocations=} option, i386 415@cindex @samp{-mrelax-relocations=} option, x86-64 416@item -mrelax-relocations=@var{no} 417@itemx -mrelax-relocations=@var{yes} 418These options control whether the assembler should generate relax 419relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and 420R_X86_64_REX_GOTPCRELX, in 64-bit mode. 421@option{-mrelax-relocations=@var{yes}} will generate relax relocations. 422@option{-mrelax-relocations=@var{no}} will not generate relax 423relocations. The default can be controlled by a configure option 424@option{--enable-x86-relax-relocations}. 425 426@cindex @samp{-malign-branch-boundary=} option, i386 427@cindex @samp{-malign-branch-boundary=} option, x86-64 428@item -malign-branch-boundary=@var{NUM} 429This option controls how the assembler should align branches with segment 430prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or 431no less than 16. Branches will be aligned within @var{NUM} byte 432boundary. @option{-malign-branch-boundary=0}, which is the default, 433doesn't align branches. 434 435@cindex @samp{-malign-branch=} option, i386 436@cindex @samp{-malign-branch=} option, x86-64 437@item -malign-branch=@var{TYPE}[+@var{TYPE}...] 438This option specifies types of branches to align. @var{TYPE} is 439combination of @samp{jcc}, which aligns conditional jumps, 440@samp{fused}, which aligns fused conditional jumps, @samp{jmp}, 441which aligns unconditional jumps, @samp{call} which aligns calls, 442@samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect 443jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}. 444 445@cindex @samp{-malign-branch-prefix-size=} option, i386 446@cindex @samp{-malign-branch-prefix-size=} option, x86-64 447@item -malign-branch-prefix-size=@var{NUM} 448This option specifies the maximum number of prefixes on an instruction 449to align branches. @var{NUM} should be between 0 and 5. The default 450@var{NUM} is 5. 451 452@cindex @samp{-mbranches-within-32B-boundaries} option, i386 453@cindex @samp{-mbranches-within-32B-boundaries} option, x86-64 454@item -mbranches-within-32B-boundaries 455This option aligns conditional jumps, fused conditional jumps and 456unconditional jumps within 32 byte boundary with up to 5 segment prefixes 457on an instruction. It is equivalent to 458@option{-malign-branch-boundary=32} 459@option{-malign-branch=jcc+fused+jmp} 460@option{-malign-branch-prefix-size=5}. 461The default doesn't align branches. 462 463@cindex @samp{-mx86-used-note=} option, i386 464@cindex @samp{-mx86-used-note=} option, x86-64 465@item -mx86-used-note=@var{no} 466@itemx -mx86-used-note=@var{yes} 467These options control whether the assembler should generate 468GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED 469GNU property notes. The default can be controlled by the 470@option{--enable-x86-used-note} configure option. 471 472@cindex @samp{-mevexrcig=} option, i386 473@cindex @samp{-mevexrcig=} option, x86-64 474@item -mevexrcig=@var{rne} 475@itemx -mevexrcig=@var{rd} 476@itemx -mevexrcig=@var{ru} 477@itemx -mevexrcig=@var{rz} 478These options control how the assembler should encode SAE-only 479EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits 480of EVEX instruction with 00, which is the default. 481@option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} 482and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions 483with 01, 10 and 11 RC bits, respectively. 484 485@cindex @samp{-mamd64} option, x86-64 486@cindex @samp{-mintel64} option, x86-64 487@item -mamd64 488@itemx -mintel64 489This option specifies that the assembler should accept only AMD64 or 490Intel64 ISA in 64-bit mode. The default is to accept both. 491 492@cindex @samp{-O0} option, i386 493@cindex @samp{-O0} option, x86-64 494@cindex @samp{-O} option, i386 495@cindex @samp{-O} option, x86-64 496@cindex @samp{-O1} option, i386 497@cindex @samp{-O1} option, x86-64 498@cindex @samp{-O2} option, i386 499@cindex @samp{-O2} option, x86-64 500@cindex @samp{-Os} option, i386 501@cindex @samp{-Os} option, x86-64 502@item -O0 | -O | -O1 | -O2 | -Os 503Optimize instruction encoding with smaller instruction size. @samp{-O} 504and @samp{-O1} encode 64-bit register load instructions with 64-bit 505immediate as 32-bit register load instructions with 31-bit or 32-bits 506immediates, encode 64-bit register clearing instructions with 32-bit 507register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector 508register clearing instructions with 128-bit VEX vector register 509clearing instructions, encode 128-bit/256-bit EVEX vector 510register load/store instructions with VEX vector register load/store 511instructions, and encode 128-bit/256-bit EVEX packed integer logical 512instructions with 128-bit/256-bit VEX packed integer logical. 513 514@samp{-O2} includes @samp{-O1} optimization plus encodes 515256-bit/512-bit EVEX vector register clearing instructions with 128-bit 516EVEX vector register clearing instructions. In 64-bit mode VEX encoded 517instructions with commutative source operands will also have their 518source operands swapped if this allows using the 2-byte VEX prefix form 519instead of the 3-byte one. Certain forms of AND as well as OR with the 520same (register) operand specified twice will also be changed to TEST. 521 522@samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit 523and 64-bit register tests with immediate as 8-bit register test with 524immediate. @samp{-O0} turns off this optimization. 525 526@end table 527@c man end 528 529@node i386-Directives 530@section x86 specific Directives 531 532@cindex machine directives, x86 533@cindex x86 machine directives 534@table @code 535 536@cindex @code{lcomm} directive, COFF 537@item .lcomm @var{symbol} , @var{length}[, @var{alignment}] 538Reserve @var{length} (an absolute expression) bytes for a local common 539denoted by @var{symbol}. The section and value of @var{symbol} are 540those of the new local common. The addresses are allocated in the bss 541section, so that at run-time the bytes start off zeroed. Since 542@var{symbol} is not declared global, it is normally not visible to 543@code{@value{LD}}. The optional third parameter, @var{alignment}, 544specifies the desired alignment of the symbol in the bss section. 545 546This directive is only available for COFF based x86 targets. 547 548@cindex @code{largecomm} directive, ELF 549@item .largecomm @var{symbol} , @var{length}[, @var{alignment}] 550This directive behaves in the same way as the @code{comm} directive 551except that the data is placed into the @var{.lbss} section instead of 552the @var{.bss} section @ref{Comm}. 553 554The directive is intended to be used for data which requires a large 555amount of space, and it is only available for ELF based x86_64 556targets. 557 558@cindex @code{value} directive 559@item .value @var{expression} [, @var{expression}] 560This directive behaves in the same way as the @code{.short} directive, 561taking a series of comma separated expressions and storing them as 562two-byte wide values into the current section. 563 564@c FIXME: Document other x86 specific directives ? Eg: .code16gcc, 565 566@end table 567 568@node i386-Syntax 569@section i386 Syntactical Considerations 570@menu 571* i386-Variations:: AT&T Syntax versus Intel Syntax 572* i386-Chars:: Special Characters 573@end menu 574 575@node i386-Variations 576@subsection AT&T Syntax versus Intel Syntax 577 578@cindex i386 intel_syntax pseudo op 579@cindex intel_syntax pseudo op, i386 580@cindex i386 att_syntax pseudo op 581@cindex att_syntax pseudo op, i386 582@cindex i386 syntax compatibility 583@cindex syntax compatibility, i386 584@cindex x86-64 intel_syntax pseudo op 585@cindex intel_syntax pseudo op, x86-64 586@cindex x86-64 att_syntax pseudo op 587@cindex att_syntax pseudo op, x86-64 588@cindex x86-64 syntax compatibility 589@cindex syntax compatibility, x86-64 590 591@code{@value{AS}} now supports assembly using Intel assembler syntax. 592@code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches 593back to the usual AT&T mode for compatibility with the output of 594@code{@value{GCC}}. Either of these directives may have an optional 595argument, @code{prefix}, or @code{noprefix} specifying whether registers 596require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite 597different from Intel syntax. We mention these differences because 598almost all 80386 documents use Intel syntax. Notable differences 599between the two syntaxes are: 600 601@cindex immediate operands, i386 602@cindex i386 immediate operands 603@cindex register operands, i386 604@cindex i386 register operands 605@cindex jump/call operands, i386 606@cindex i386 jump/call operands 607@cindex operand delimiters, i386 608 609@cindex immediate operands, x86-64 610@cindex x86-64 immediate operands 611@cindex register operands, x86-64 612@cindex x86-64 register operands 613@cindex jump/call operands, x86-64 614@cindex x86-64 jump/call operands 615@cindex operand delimiters, x86-64 616@itemize @bullet 617@item 618AT&T immediate operands are preceded by @samp{$}; Intel immediate 619operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). 620AT&T register operands are preceded by @samp{%}; Intel register operands 621are undelimited. AT&T absolute (as opposed to PC relative) jump/call 622operands are prefixed by @samp{*}; they are undelimited in Intel syntax. 623 624@cindex i386 source, destination operands 625@cindex source, destination operands; i386 626@cindex x86-64 source, destination operands 627@cindex source, destination operands; x86-64 628@item 629AT&T and Intel syntax use the opposite order for source and destination 630operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The 631@samp{source, dest} convention is maintained for compatibility with 632previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and 633instructions with 2 immediate operands, such as the @samp{enter} 634instruction, do @emph{not} have reversed order. @ref{i386-Bugs}. 635 636@cindex mnemonic suffixes, i386 637@cindex sizes operands, i386 638@cindex i386 size suffixes 639@cindex mnemonic suffixes, x86-64 640@cindex sizes operands, x86-64 641@cindex x86-64 size suffixes 642@item 643In AT&T syntax the size of memory operands is determined from the last 644character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, 645@samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long 646(32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes 647of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm 648(256-bit vector) and zmm (512-bit vector) memory references, only when there's 649no other way to disambiguate an instruction. Intel syntax accomplishes this by 650prefixing memory operands (@emph{not} the instruction mnemonics) with 651@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr}, 652@samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel 653syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T 654syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and 655@samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references. 656 657In 64-bit code, @samp{movabs} can be used to encode the @samp{mov} 658instruction with the 64-bit displacement or immediate operand. 659 660@cindex return instructions, i386 661@cindex i386 jump, call, return 662@cindex return instructions, x86-64 663@cindex x86-64 jump, call, return 664@item 665Immediate form long jumps and calls are 666@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the 667Intel syntax is 668@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return 669instruction 670is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is 671@samp{ret far @var{stack-adjust}}. 672 673@cindex sections, i386 674@cindex i386 sections 675@cindex sections, x86-64 676@cindex x86-64 sections 677@item 678The AT&T assembler does not provide support for multiple section 679programs. Unix style systems expect all programs to be single sections. 680@end itemize 681 682@node i386-Chars 683@subsection Special Characters 684 685@cindex line comment character, i386 686@cindex i386 line comment character 687The presence of a @samp{#} appearing anywhere on a line indicates the 688start of a comment that extends to the end of that line. 689 690If a @samp{#} appears as the first character of a line then the whole 691line is treated as a comment, but in this case the line can also be a 692logical line number directive (@pxref{Comments}) or a preprocessor 693control command (@pxref{Preprocessing}). 694 695If the @option{--divide} command-line option has not been specified 696then the @samp{/} character appearing anywhere on a line also 697introduces a line comment. 698 699@cindex line separator, i386 700@cindex statement separator, i386 701@cindex i386 line separator 702The @samp{;} character can be used to separate statements on the same 703line. 704 705@node i386-Mnemonics 706@section i386-Mnemonics 707@subsection Instruction Naming 708 709@cindex i386 instruction naming 710@cindex instruction naming, i386 711@cindex x86-64 instruction naming 712@cindex instruction naming, x86-64 713 714Instruction mnemonics are suffixed with one character modifiers which 715specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l} 716and @samp{q} specify byte, word, long and quadruple word operands. If 717no suffix is specified by an instruction then @code{@value{AS}} tries to 718fill in the missing suffix based on the destination register operand 719(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent 720to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to 721@samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix 722assembler which assumes that a missing mnemonic suffix implies long 723operand size. (This incompatibility does not affect compiler output 724since compilers always explicitly specify the mnemonic suffix.) 725 726Almost all instructions have the same names in AT&T and Intel format. 727There are a few exceptions. The sign extend and zero extend 728instructions need two sizes to specify them. They need a size to 729sign/zero extend @emph{from} and a size to zero extend @emph{to}. This 730is accomplished by using two instruction mnemonic suffixes in AT&T 731syntax. Base names for sign extend and zero extend are 732@samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} 733and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes 734are tacked on to this base name, the @emph{from} suffix before the 735@emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for 736``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, 737thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), 738@samp{wl} (from word to long), @samp{bq} (from byte to quadruple word), 739@samp{wq} (from word to quadruple word), and @samp{lq} (from long to 740quadruple word). 741 742@cindex encoding options, i386 743@cindex encoding options, x86-64 744 745Different encoding options can be specified via pseudo prefixes: 746 747@itemize @bullet 748@item 749@samp{@{disp8@}} -- prefer 8-bit displacement. 750 751@item 752@samp{@{disp32@}} -- prefer 32-bit displacement. 753 754@item 755@samp{@{load@}} -- prefer load-form instruction. 756 757@item 758@samp{@{store@}} -- prefer store-form instruction. 759 760@item 761@samp{@{vex@}} -- encode with VEX prefix. 762 763@item 764@samp{@{vex3@}} -- encode with 3-byte VEX prefix. 765 766@item 767@samp{@{evex@}} -- encode with EVEX prefix. 768 769@item 770@samp{@{rex@}} -- prefer REX prefix for integer and legacy vector 771instructions (x86-64 only). Note that this differs from the @samp{rex} 772prefix which generates REX prefix unconditionally. 773 774@item 775@samp{@{nooptimize@}} -- disable instruction size optimization. 776@end itemize 777 778@cindex conversion instructions, i386 779@cindex i386 conversion instructions 780@cindex conversion instructions, x86-64 781@cindex x86-64 conversion instructions 782The Intel-syntax conversion instructions 783 784@itemize @bullet 785@item 786@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, 787 788@item 789@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, 790 791@item 792@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, 793 794@item 795@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, 796 797@item 798@samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax} 799(x86-64 only), 800 801@item 802@samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in 803@samp{%rdx:%rax} (x86-64 only), 804@end itemize 805 806@noindent 807are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and 808@samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these 809instructions. 810 811@cindex jump instructions, i386 812@cindex call instructions, i386 813@cindex jump instructions, x86-64 814@cindex call instructions, x86-64 815Far call/jump instructions are @samp{lcall} and @samp{ljmp} in 816AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel 817convention. 818 819@subsection AT&T Mnemonic versus Intel Mnemonic 820 821@cindex i386 mnemonic compatibility 822@cindex mnemonic compatibility, i386 823 824@code{@value{AS}} supports assembly using Intel mnemonic. 825@code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and 826@code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T 827syntax for compatibility with the output of @code{@value{GCC}}. 828Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, 829@samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp}, 830@samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386 831assembler with different mnemonics from those in Intel IA32 specification. 832@code{@value{GCC}} generates those instructions with AT&T mnemonic. 833 834@node i386-Regs 835@section Register Naming 836 837@cindex i386 registers 838@cindex registers, i386 839@cindex x86-64 registers 840@cindex registers, x86-64 841Register operands are always prefixed with @samp{%}. The 80386 registers 842consist of 843 844@itemize @bullet 845@item 846the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, 847@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the 848frame pointer), and @samp{%esp} (the stack pointer). 849 850@item 851the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, 852@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. 853 854@item 855the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, 856@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These 857are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, 858@samp{%cx}, and @samp{%dx}) 859 860@item 861the 6 section registers @samp{%cs} (code section), @samp{%ds} 862(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, 863and @samp{%gs}. 864 865@item 866the 5 processor control registers @samp{%cr0}, @samp{%cr2}, 867@samp{%cr3}, @samp{%cr4}, and @samp{%cr8}. 868 869@item 870the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, 871@samp{%db3}, @samp{%db6}, and @samp{%db7}. 872 873@item 874the 2 test registers @samp{%tr6} and @samp{%tr7}. 875 876@item 877the 8 floating point register stack @samp{%st} or equivalently 878@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, 879@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. 880These registers are overloaded by 8 MMX registers @samp{%mm0}, 881@samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5}, 882@samp{%mm6} and @samp{%mm7}. 883 884@item 885the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, 886@samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. 887@end itemize 888 889The AMD x86-64 architecture extends the register set by: 890 891@itemize @bullet 892@item 893enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the 894accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi}, 895@samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack 896pointer) 897 898@item 899the 8 extended registers @samp{%r8}--@samp{%r15}. 900 901@item 902the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}. 903 904@item 905the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}. 906 907@item 908the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}. 909 910@item 911the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. 912 913@item 914the 8 debug registers: @samp{%db8}--@samp{%db15}. 915 916@item 917the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}. 918@end itemize 919 920With the AVX extensions more registers were made available: 921 922@itemize @bullet 923 924@item 925the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8 926available in 32-bit mode). The bottom 128 bits are overlaid with the 927@samp{xmm0}--@samp{xmm15} registers. 928 929@end itemize 930 931The AVX2 extensions made in 64-bit mode more registers available: 932 933@itemize @bullet 934 935@item 936the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit 937registers @samp{%ymm16}--@samp{%ymm31}. 938 939@end itemize 940 941The AVX512 extensions added the following registers: 942 943@itemize @bullet 944 945@item 946the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8 947available in 32-bit mode). The bottom 128 bits are overlaid with the 948@samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are 949overlaid with the @samp{%ymm0}--@samp{%ymm31} registers. 950 951@item 952the 8 mask registers @samp{%k0}--@samp{%k7}. 953 954@end itemize 955 956@node i386-Prefixes 957@section Instruction Prefixes 958 959@cindex i386 instruction prefixes 960@cindex instruction prefixes, i386 961@cindex prefixes, i386 962Instruction prefixes are used to modify the following instruction. They 963are used to repeat string instructions, to provide section overrides, to 964perform bus lock operations, and to change operand and address sizes. 965(Most instructions that normally operate on 32-bit operands will use 96616-bit operands if the instruction has an ``operand size'' prefix.) 967Instruction prefixes are best written on the same line as the instruction 968they act upon. For example, the @samp{scas} (scan string) instruction is 969repeated with: 970 971@smallexample 972 repne scas %es:(%edi),%al 973@end smallexample 974 975You may also place prefixes on the lines immediately preceding the 976instruction, but this circumvents checks that @code{@value{AS}} does 977with prefixes, and will not work with all prefixes. 978 979Here is a list of instruction prefixes: 980 981@cindex section override prefixes, i386 982@itemize @bullet 983@item 984Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, 985@samp{fs}, @samp{gs}. These are automatically added by specifying 986using the @var{section}:@var{memory-operand} form for memory references. 987 988@cindex size prefixes, i386 989@item 990Operand/Address size prefixes @samp{data16} and @samp{addr16} 991change 32-bit operands/addresses into 16-bit operands/addresses, 992while @samp{data32} and @samp{addr32} change 16-bit ones (in a 993@code{.code16} section) into 32-bit operands/addresses. These prefixes 994@emph{must} appear on the same line of code as the instruction they 995modify. For example, in a 16-bit @code{.code16} section, you might 996write: 997 998@smallexample 999 addr32 jmpl *(%ebx) 1000@end smallexample 1001 1002@cindex bus lock prefixes, i386 1003@cindex inhibiting interrupts, i386 1004@item 1005The bus lock prefix @samp{lock} inhibits interrupts during execution of 1006the instruction it precedes. (This is only valid with certain 1007instructions; see a 80386 manual for details). 1008 1009@cindex coprocessor wait, i386 1010@item 1011The wait for coprocessor prefix @samp{wait} waits for the coprocessor to 1012complete the current instruction. This should never be needed for the 101380386/80387 combination. 1014 1015@cindex repeat prefixes, i386 1016@item 1017The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added 1018to string instructions to make them repeat @samp{%ecx} times (@samp{%cx} 1019times if the current address size is 16-bits). 1020@cindex REX prefixes, i386 1021@item 1022The @samp{rex} family of prefixes is used by x86-64 to encode 1023extensions to i386 instruction set. The @samp{rex} prefix has four 1024bits --- an operand size overwrite (@code{64}) used to change operand size 1025from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the 1026register set. 1027 1028You may write the @samp{rex} prefixes directly. The @samp{rex64xyz} 1029instruction emits @samp{rex} prefix with all the bits set. By omitting 1030the @code{64}, @code{x}, @code{y} or @code{z} you may write other 1031prefixes as well. Normally, there is no need to write the prefixes 1032explicitly, since gas will automatically generate them based on the 1033instruction operands. 1034@end itemize 1035 1036@node i386-Memory 1037@section Memory References 1038 1039@cindex i386 memory references 1040@cindex memory references, i386 1041@cindex x86-64 memory references 1042@cindex memory references, x86-64 1043An Intel syntax indirect memory reference of the form 1044 1045@smallexample 1046@var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] 1047@end smallexample 1048 1049@noindent 1050is translated into the AT&T syntax 1051 1052@smallexample 1053@var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) 1054@end smallexample 1055 1056@noindent 1057where @var{base} and @var{index} are the optional 32-bit base and 1058index registers, @var{disp} is the optional displacement, and 1059@var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} 1060to calculate the address of the operand. If no @var{scale} is 1061specified, @var{scale} is taken to be 1. @var{section} specifies the 1062optional section register for the memory operand, and may override the 1063default section register (see a 80386 manual for section register 1064defaults). Note that section overrides in AT&T syntax @emph{must} 1065be preceded by a @samp{%}. If you specify a section override which 1066coincides with the default section register, @code{@value{AS}} does @emph{not} 1067output any section register override prefixes to assemble the given 1068instruction. Thus, section overrides can be specified to emphasize which 1069section register is used for a given memory operand. 1070 1071Here are some examples of Intel and AT&T style memory references: 1072 1073@table @asis 1074@item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} 1075@var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is 1076missing, and the default section is used (@samp{%ss} for addressing with 1077@samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. 1078 1079@item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} 1080@var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is 1081@samp{foo}. All other fields are missing. The section register here 1082defaults to @samp{%ds}. 1083 1084@item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} 1085This uses the value pointed to by @samp{foo} as a memory operand. 1086Note that @var{base} and @var{index} are both missing, but there is only 1087@emph{one} @samp{,}. This is a syntactic exception. 1088 1089@item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} 1090This selects the contents of the variable @samp{foo} with section 1091register @var{section} being @samp{%gs}. 1092@end table 1093 1094Absolute (as opposed to PC relative) call and jump operands must be 1095prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} 1096always chooses PC relative addressing for jump/call labels. 1097 1098Any instruction that has a memory operand, but no register operand, 1099@emph{must} specify its size (byte, word, long, or quadruple) with an 1100instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q}, 1101respectively). 1102 1103The x86-64 architecture adds an RIP (instruction pointer relative) 1104addressing. This addressing mode is specified by using @samp{rip} as a 1105base register. Only constant offsets are valid. For example: 1106 1107@table @asis 1108@item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]} 1109Points to the address 1234 bytes past the end of the current 1110instruction. 1111 1112@item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]} 1113Points to the @code{symbol} in RIP relative way, this is shorter than 1114the default absolute addressing. 1115@end table 1116 1117Other addressing modes remain unchanged in x86-64 architecture, except 1118registers used are 64-bit instead of 32-bit. 1119 1120@node i386-Jumps 1121@section Handling of Jump Instructions 1122 1123@cindex jump optimization, i386 1124@cindex i386 jump optimization 1125@cindex jump optimization, x86-64 1126@cindex x86-64 jump optimization 1127Jump instructions are always optimized to use the smallest possible 1128displacements. This is accomplished by using byte (8-bit) displacement 1129jumps whenever the target is sufficiently close. If a byte displacement 1130is insufficient a long displacement is used. We do not support 1131word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 1132instruction with the @samp{data16} instruction prefix), since the 80386 1133insists upon masking @samp{%eip} to 16 bits after the word displacement 1134is added. (See also @pxref{i386-Arch}) 1135 1136Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, 1137@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte 1138displacements, so that if you use these instructions (@code{@value{GCC}} does 1139not use them) you may get an error message (and incorrect code). The AT&T 114080386 assembler tries to get around this problem by expanding @samp{jcxz foo} 1141to 1142 1143@smallexample 1144 jcxz cx_zero 1145 jmp cx_nonzero 1146cx_zero: jmp foo 1147cx_nonzero: 1148@end smallexample 1149 1150@node i386-Float 1151@section Floating Point 1152 1153@cindex i386 floating point 1154@cindex floating point, i386 1155@cindex x86-64 floating point 1156@cindex floating point, x86-64 1157All 80387 floating point types except packed BCD are supported. 1158(BCD support may be added without much difficulty). These data 1159types are 16-, 32-, and 64- bit integers, and single (32-bit), 1160double (64-bit), and extended (80-bit) precision floating point. 1161Each supported type has an instruction mnemonic suffix and a constructor 1162associated with it. Instruction mnemonic suffixes specify the operand's 1163data type. Constructors build these data types into memory. 1164 1165@cindex @code{float} directive, i386 1166@cindex @code{single} directive, i386 1167@cindex @code{double} directive, i386 1168@cindex @code{tfloat} directive, i386 1169@cindex @code{float} directive, x86-64 1170@cindex @code{single} directive, x86-64 1171@cindex @code{double} directive, x86-64 1172@cindex @code{tfloat} directive, x86-64 1173@itemize @bullet 1174@item 1175Floating point constructors are @samp{.float} or @samp{.single}, 1176@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. 1177These correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, 1178and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 1179only supports this format via the @samp{fldt} (load 80-bit real to stack 1180top) and @samp{fstpt} (store 80-bit real and pop stack) instructions. 1181 1182@cindex @code{word} directive, i386 1183@cindex @code{long} directive, i386 1184@cindex @code{int} directive, i386 1185@cindex @code{quad} directive, i386 1186@cindex @code{word} directive, x86-64 1187@cindex @code{long} directive, x86-64 1188@cindex @code{int} directive, x86-64 1189@cindex @code{quad} directive, x86-64 1190@item 1191Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and 1192@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The 1193corresponding instruction mnemonic suffixes are @samp{s} (single), 1194@samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, 1195the 64-bit @samp{q} format is only present in the @samp{fildq} (load 1196quad integer to stack top) and @samp{fistpq} (store quad integer and pop 1197stack) instructions. 1198@end itemize 1199 1200Register to register operations should not use instruction mnemonic suffixes. 1201@samp{fstl %st, %st(1)} will give a warning, and be assembled as if you 1202wrote @samp{fst %st, %st(1)}, since all register to register operations 1203use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, 1204which converts @samp{%st} from 80-bit to 64-bit floating point format, 1205then stores the result in the 4 byte location @samp{mem}) 1206 1207@node i386-SIMD 1208@section Intel's MMX and AMD's 3DNow! SIMD Operations 1209 1210@cindex MMX, i386 1211@cindex 3DNow!, i386 1212@cindex SIMD, i386 1213@cindex MMX, x86-64 1214@cindex 3DNow!, x86-64 1215@cindex SIMD, x86-64 1216 1217@code{@value{AS}} supports Intel's MMX instruction set (SIMD 1218instructions for integer data), available on Intel's Pentium MMX 1219processors and Pentium II processors, AMD's K6 and K6-2 processors, 1220Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: 1221instruction set (SIMD instructions for 32-bit floating point data) 1222available on AMD's K6-2 processor and possibly others in the future. 1223 1224Currently, @code{@value{AS}} does not support Intel's floating point 1225SIMD, Katmai (KNI). 1226 1227The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, 1228@samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four 122916-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 1230floating point values. The MMX registers cannot be used at the same time 1231as the floating point stack. 1232 1233See Intel and AMD documentation, keeping in mind that the operand order in 1234instructions is reversed from the Intel syntax. 1235 1236@node i386-LWP 1237@section AMD's Lightweight Profiling Instructions 1238 1239@cindex LWP, i386 1240@cindex LWP, x86-64 1241 1242@code{@value{AS}} supports AMD's Lightweight Profiling (LWP) 1243instruction set, available on AMD's Family 15h (Orochi) processors. 1244 1245LWP enables applications to collect and manage performance data, and 1246react to performance events. The collection of performance data 1247requires no context switches. LWP runs in the context of a thread and 1248so several counters can be used independently across multiple threads. 1249LWP can be used in both 64-bit and legacy 32-bit modes. 1250 1251For detailed information on the LWP instruction set, see the 1252@cite{AMD Lightweight Profiling Specification} available at 1253@uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}. 1254 1255@node i386-BMI 1256@section Bit Manipulation Instructions 1257 1258@cindex BMI, i386 1259@cindex BMI, x86-64 1260 1261@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set. 1262 1263BMI instructions provide several instructions implementing individual 1264bit manipulation operations such as isolation, masking, setting, or 1265resetting. 1266 1267@c Need to add a specification citation here when available. 1268 1269@node i386-TBM 1270@section AMD's Trailing Bit Manipulation Instructions 1271 1272@cindex TBM, i386 1273@cindex TBM, x86-64 1274 1275@code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM) 1276instruction set, available on AMD's BDVER2 processors (Trinity and 1277Viperfish). 1278 1279TBM instructions provide instructions implementing individual bit 1280manipulation operations such as isolating, masking, setting, resetting, 1281complementing, and operations on trailing zeros and ones. 1282 1283@c Need to add a specification citation here when available. 1284 1285@node i386-16bit 1286@section Writing 16-bit Code 1287 1288@cindex i386 16-bit code 1289@cindex 16-bit code, i386 1290@cindex real-mode code, i386 1291@cindex @code{code16gcc} directive, i386 1292@cindex @code{code16} directive, i386 1293@cindex @code{code32} directive, i386 1294@cindex @code{code64} directive, i386 1295@cindex @code{code64} directive, x86-64 1296While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code 1297or 64-bit x86-64 code depending on the default configuration, 1298it also supports writing code to run in real mode or in 16-bit protected 1299mode code segments. To do this, put a @samp{.code16} or 1300@samp{.code16gcc} directive before the assembly language instructions to 1301be run in 16-bit mode. You can switch @code{@value{AS}} to writing 130232-bit code with the @samp{.code32} directive or 64-bit code with the 1303@samp{.code64} directive. 1304 1305@samp{.code16gcc} provides experimental support for generating 16-bit 1306code from gcc, and differs from @samp{.code16} in that @samp{call}, 1307@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, 1308@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions 1309default to 32-bit size. This is so that the stack pointer is 1310manipulated in the same way over function calls, allowing access to 1311function parameters at the same stack offsets as in 32-bit mode. 1312@samp{.code16gcc} also automatically adds address size prefixes where 1313necessary to use the 32-bit addressing modes that gcc generates. 1314 1315The code which @code{@value{AS}} generates in 16-bit mode will not 1316necessarily run on a 16-bit pre-80386 processor. To write code that 1317runs on such a processor, you must refrain from using @emph{any} 32-bit 1318constructs which require @code{@value{AS}} to output address or operand 1319size prefixes. 1320 1321Note that writing 16-bit code instructions by explicitly specifying a 1322prefix or an instruction mnemonic suffix within a 32-bit code section 1323generates different machine instructions than those generated for a 132416-bit code segment. In a 32-bit code section, the following code 1325generates the machine opcode bytes @samp{66 6a 04}, which pushes the 1326value @samp{4} onto the stack, decrementing @samp{%esp} by 2. 1327 1328@smallexample 1329 pushw $4 1330@end smallexample 1331 1332The same code in a 16-bit code section would generate the machine 1333opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which 1334is correct since the processor default operand size is assumed to be 16 1335bits in a 16-bit code section. 1336 1337@node i386-Arch 1338@section Specifying CPU Architecture 1339 1340@cindex arch directive, i386 1341@cindex i386 arch directive 1342@cindex arch directive, x86-64 1343@cindex x86-64 arch directive 1344 1345@code{@value{AS}} may be told to assemble for a particular CPU 1346(sub-)architecture with the @code{.arch @var{cpu_type}} directive. This 1347directive enables a warning when gas detects an instruction that is not 1348supported on the CPU specified. The choices for @var{cpu_type} are: 1349 1350@multitable @columnfractions .20 .20 .20 .20 1351@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} 1352@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} 1353@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} 1354@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} 1355@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu} 1356@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} 1357@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} 1358@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1} 1359@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} 1360@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} 1361@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} 1362@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} 1363@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} 1364@item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} 1365@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase} 1366@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} 1367@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle} 1368@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} 1369@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} 1370@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} 1371@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} 1372@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} 1373@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw} 1374@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni} 1375@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} 1376@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt} 1377@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} 1378@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} 1379@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} 1380@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} 1381@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} 1382@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} 1383@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} 1384@item @samp{.mcommit} 1385@end multitable 1386 1387Apart from the warning, there are only two other effects on 1388@code{@value{AS}} operation; Firstly, if you specify a CPU other than 1389@samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} 1390will automatically use a two byte opcode sequence. The larger three 1391byte opcode sequence is used on the 486 (and when no architecture is 1392specified) because it executes faster on the 486. Note that you can 1393explicitly request the two byte opcode by writing @samp{sarl %eax}. 1394Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286}, 1395@emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset 1396conditional jumps will be promoted when necessary to a two instruction 1397sequence consisting of a conditional jump of the opposite sense around 1398an unconditional jump to the target. 1399 1400Following the CPU architecture (but not a sub-architecture, which are those 1401starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to 1402control automatic promotion of conditional jumps. @samp{jumps} is the 1403default, and enables jump promotion; All external jumps will be of the long 1404variety, and file-local jumps will be promoted as necessary. 1405(@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as 1406byte offset jumps, and warns about file-local conditional jumps that 1407@code{@value{AS}} promotes. 1408Unconditional jumps are treated as for @samp{jumps}. 1409 1410For example 1411 1412@smallexample 1413 .arch i8086,nojumps 1414@end smallexample 1415 1416@node i386-Bugs 1417@section AT&T Syntax bugs 1418 1419The UnixWare assembler, and probably other AT&T derived ix86 Unix 1420assemblers, generate floating point instructions with reversed source 1421and destination registers in certain cases. Unfortunately, gcc and 1422possibly many other programs use this reversed syntax, so we're stuck 1423with it. 1424 1425For example 1426 1427@smallexample 1428 fsub %st,%st(3) 1429@end smallexample 1430@noindent 1431results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather 1432than the expected @samp{%st(3) - %st}. This happens with all the 1433non-commutative arithmetic floating point operations with two register 1434operands where the source register is @samp{%st} and the destination 1435register is @samp{%st(i)}. 1436 1437@node i386-Notes 1438@section Notes 1439 1440@cindex i386 @code{mul}, @code{imul} instructions 1441@cindex @code{mul} instruction, i386 1442@cindex @code{imul} instruction, i386 1443@cindex @code{mul} instruction, x86-64 1444@cindex @code{imul} instruction, x86-64 1445There is some trickery concerning the @samp{mul} and @samp{imul} 1446instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding 1447multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 1448for @samp{imul}) can be output only in the one operand form. Thus, 1449@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; 1450the expanding multiply would clobber the @samp{%edx} register, and this 1451would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the 145264-bit product in @samp{%edx:%eax}. 1453 1454We have added a two operand form of @samp{imul} when the first operand 1455is an immediate mode expression and the second operand is a register. 1456This is just a shorthand, so that, multiplying @samp{%eax} by 69, for 1457example, can be done with @samp{imul $69, %eax} rather than @samp{imul 1458$69, %eax, %eax}. 1459 1460