1/* ARM ldm/stm instruction patterns. This file was automatically generated 2 using arm-ldmstm.ml. Please do not edit manually. 3 4 Copyright (C) 2010-2020 Free Software Foundation, Inc. 5 Contributed by CodeSourcery. 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify it 10 under the terms of the GNU General Public License as published 11 by the Free Software Foundation; either version 3, or (at your 12 option) any later version. 13 14 GCC is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License and 20 a copy of the GCC Runtime Library Exception along with this program; 21 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 22 <http://www.gnu.org/licenses/>. */ 23 24(define_insn "*ldm4_" 25 [(match_parallel 0 "load_multiple_operation" 26 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 27 (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))) 28 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 29 (mem:SI (plus:SI (match_dup 5) 30 (const_int 4)))) 31 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 32 (mem:SI (plus:SI (match_dup 5) 33 (const_int 8)))) 34 (set (match_operand:SI 4 "arm_hard_general_register_operand" "") 35 (mem:SI (plus:SI (match_dup 5) 36 (const_int 12))))])] 37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 38 "ldm%?\t%5, {%1, %2, %3, %4}" 39 [(set_attr "type" "load_16") 40 (set_attr "predicable" "yes")]) 41 42(define_insn "*thumb_ldm4_ia" 43 [(match_parallel 0 "load_multiple_operation" 44 [(set (match_operand:SI 1 "low_register_operand" "") 45 (mem:SI (match_operand:SI 5 "s_register_operand" "l"))) 46 (set (match_operand:SI 2 "low_register_operand" "") 47 (mem:SI (plus:SI (match_dup 5) 48 (const_int 4)))) 49 (set (match_operand:SI 3 "low_register_operand" "") 50 (mem:SI (plus:SI (match_dup 5) 51 (const_int 8)))) 52 (set (match_operand:SI 4 "low_register_operand" "") 53 (mem:SI (plus:SI (match_dup 5) 54 (const_int 12))))])] 55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" 56 "ldmia\t%5, {%1, %2, %3, %4}" 57 [(set_attr "type" "load_16")]) 58 59(define_insn "*ldm4_ia_update" 60 [(match_parallel 0 "load_multiple_operation" 61 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 62 (plus:SI (match_dup 5) (const_int 16))) 63 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 64 (mem:SI (match_dup 5))) 65 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 66 (mem:SI (plus:SI (match_dup 5) 67 (const_int 4)))) 68 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 69 (mem:SI (plus:SI (match_dup 5) 70 (const_int 8)))) 71 (set (match_operand:SI 4 "arm_hard_general_register_operand" "") 72 (mem:SI (plus:SI (match_dup 5) 73 (const_int 12))))])] 74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" 75 "ldmia%?\t%5!, {%1, %2, %3, %4}" 76 [(set_attr "type" "load_16") 77 (set_attr "predicable" "yes")]) 78 79(define_insn "*thumb_ldm4_ia_update" 80 [(match_parallel 0 "load_multiple_operation" 81 [(set (match_operand:SI 5 "s_register_operand" "+&l") 82 (plus:SI (match_dup 5) (const_int 16))) 83 (set (match_operand:SI 1 "low_register_operand" "") 84 (mem:SI (match_dup 5))) 85 (set (match_operand:SI 2 "low_register_operand" "") 86 (mem:SI (plus:SI (match_dup 5) 87 (const_int 4)))) 88 (set (match_operand:SI 3 "low_register_operand" "") 89 (mem:SI (plus:SI (match_dup 5) 90 (const_int 8)))) 91 (set (match_operand:SI 4 "low_register_operand" "") 92 (mem:SI (plus:SI (match_dup 5) 93 (const_int 12))))])] 94 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" 95 "ldmia\t%5!, {%1, %2, %3, %4}" 96 [(set_attr "type" "load_16")]) 97 98(define_insn "*stm4_" 99 [(match_parallel 0 "store_multiple_operation" 100 [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk")) 101 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 102 (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) 103 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 104 (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) 105 (match_operand:SI 3 "arm_hard_general_register_operand" "")) 106 (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) 107 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] 108 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 109 "stm%?\t%5, {%1, %2, %3, %4}" 110 [(set_attr "type" "store_16") 111 (set_attr "predicable" "yes")]) 112 113(define_insn "*stm4_ia_update" 114 [(match_parallel 0 "store_multiple_operation" 115 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 116 (plus:SI (match_dup 5) (const_int 16))) 117 (set (mem:SI (match_dup 5)) 118 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 119 (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) 120 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 121 (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) 122 (match_operand:SI 3 "arm_hard_general_register_operand" "")) 123 (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) 124 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] 125 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" 126 "stmia%?\t%5!, {%1, %2, %3, %4}" 127 [(set_attr "type" "store_16") 128 (set_attr "predicable" "yes")]) 129 130(define_insn "*thumb_stm4_ia_update" 131 [(match_parallel 0 "store_multiple_operation" 132 [(set (match_operand:SI 5 "s_register_operand" "+&l") 133 (plus:SI (match_dup 5) (const_int 16))) 134 (set (mem:SI (match_dup 5)) 135 (match_operand:SI 1 "low_register_operand" "")) 136 (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) 137 (match_operand:SI 2 "low_register_operand" "")) 138 (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) 139 (match_operand:SI 3 "low_register_operand" "")) 140 (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) 141 (match_operand:SI 4 "low_register_operand" ""))])] 142 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" 143 "stmia\t%5!, {%1, %2, %3, %4}" 144 [(set_attr "type" "store_16")]) 145 146(define_insn "*ldm4_ib" 147 [(match_parallel 0 "load_multiple_operation" 148 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 149 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") 150 (const_int 4)))) 151 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 152 (mem:SI (plus:SI (match_dup 5) 153 (const_int 8)))) 154 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 155 (mem:SI (plus:SI (match_dup 5) 156 (const_int 12)))) 157 (set (match_operand:SI 4 "arm_hard_general_register_operand" "") 158 (mem:SI (plus:SI (match_dup 5) 159 (const_int 16))))])] 160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 161 "ldmib%?\t%5, {%1, %2, %3, %4}" 162 [(set_attr "type" "load_16") 163 (set_attr "predicable" "yes")]) 164 165(define_insn "*ldm4_ib_update" 166 [(match_parallel 0 "load_multiple_operation" 167 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 168 (plus:SI (match_dup 5) (const_int 16))) 169 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 170 (mem:SI (plus:SI (match_dup 5) 171 (const_int 4)))) 172 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 173 (mem:SI (plus:SI (match_dup 5) 174 (const_int 8)))) 175 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 176 (mem:SI (plus:SI (match_dup 5) 177 (const_int 12)))) 178 (set (match_operand:SI 4 "arm_hard_general_register_operand" "") 179 (mem:SI (plus:SI (match_dup 5) 180 (const_int 16))))])] 181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5" 182 "ldmib%?\t%5!, {%1, %2, %3, %4}" 183 [(set_attr "type" "load_16") 184 (set_attr "predicable" "yes")]) 185 186(define_insn "*stm4_ib" 187 [(match_parallel 0 "store_multiple_operation" 188 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4))) 189 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 190 (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) 191 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 192 (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) 193 (match_operand:SI 3 "arm_hard_general_register_operand" "")) 194 (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) 195 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] 196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 197 "stmib%?\t%5, {%1, %2, %3, %4}" 198 [(set_attr "type" "store_16") 199 (set_attr "predicable" "yes")]) 200 201(define_insn "*stm4_ib_update" 202 [(match_parallel 0 "store_multiple_operation" 203 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 204 (plus:SI (match_dup 5) (const_int 16))) 205 (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) 206 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 207 (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) 208 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 209 (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) 210 (match_operand:SI 3 "arm_hard_general_register_operand" "")) 211 (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) 212 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] 213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5" 214 "stmib%?\t%5!, {%1, %2, %3, %4}" 215 [(set_attr "type" "store_16") 216 (set_attr "predicable" "yes")]) 217 218(define_insn "*ldm4_da" 219 [(match_parallel 0 "load_multiple_operation" 220 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 221 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") 222 (const_int -12)))) 223 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 224 (mem:SI (plus:SI (match_dup 5) 225 (const_int -8)))) 226 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 227 (mem:SI (plus:SI (match_dup 5) 228 (const_int -4)))) 229 (set (match_operand:SI 4 "arm_hard_general_register_operand" "") 230 (mem:SI (match_dup 5)))])] 231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 232 "ldmda%?\t%5, {%1, %2, %3, %4}" 233 [(set_attr "type" "load_16") 234 (set_attr "predicable" "yes")]) 235 236(define_insn "*ldm4_da_update" 237 [(match_parallel 0 "load_multiple_operation" 238 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 239 (plus:SI (match_dup 5) (const_int -16))) 240 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 241 (mem:SI (plus:SI (match_dup 5) 242 (const_int -12)))) 243 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 244 (mem:SI (plus:SI (match_dup 5) 245 (const_int -8)))) 246 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 247 (mem:SI (plus:SI (match_dup 5) 248 (const_int -4)))) 249 (set (match_operand:SI 4 "arm_hard_general_register_operand" "") 250 (mem:SI (match_dup 5)))])] 251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5" 252 "ldmda%?\t%5!, {%1, %2, %3, %4}" 253 [(set_attr "type" "load_16") 254 (set_attr "predicable" "yes")]) 255 256(define_insn "*stm4_da" 257 [(match_parallel 0 "store_multiple_operation" 258 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12))) 259 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 260 (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) 261 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 262 (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) 263 (match_operand:SI 3 "arm_hard_general_register_operand" "")) 264 (set (mem:SI (match_dup 5)) 265 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] 266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 267 "stmda%?\t%5, {%1, %2, %3, %4}" 268 [(set_attr "type" "store_16") 269 (set_attr "predicable" "yes")]) 270 271(define_insn "*stm4_da_update" 272 [(match_parallel 0 "store_multiple_operation" 273 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 274 (plus:SI (match_dup 5) (const_int -16))) 275 (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) 276 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 277 (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) 278 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 279 (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) 280 (match_operand:SI 3 "arm_hard_general_register_operand" "")) 281 (set (mem:SI (match_dup 5)) 282 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] 283 "TARGET_ARM && XVECLEN (operands[0], 0) == 5" 284 "stmda%?\t%5!, {%1, %2, %3, %4}" 285 [(set_attr "type" "store_16") 286 (set_attr "predicable" "yes")]) 287 288(define_insn "*ldm4_db" 289 [(match_parallel 0 "load_multiple_operation" 290 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 291 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") 292 (const_int -16)))) 293 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 294 (mem:SI (plus:SI (match_dup 5) 295 (const_int -12)))) 296 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 297 (mem:SI (plus:SI (match_dup 5) 298 (const_int -8)))) 299 (set (match_operand:SI 4 "arm_hard_general_register_operand" "") 300 (mem:SI (plus:SI (match_dup 5) 301 (const_int -4))))])] 302 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 303 "ldmdb%?\t%5, {%1, %2, %3, %4}" 304 [(set_attr "type" "load_16") 305 (set_attr "predicable" "yes")]) 306 307(define_insn "*ldm4_db_update" 308 [(match_parallel 0 "load_multiple_operation" 309 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 310 (plus:SI (match_dup 5) (const_int -16))) 311 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 312 (mem:SI (plus:SI (match_dup 5) 313 (const_int -16)))) 314 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 315 (mem:SI (plus:SI (match_dup 5) 316 (const_int -12)))) 317 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 318 (mem:SI (plus:SI (match_dup 5) 319 (const_int -8)))) 320 (set (match_operand:SI 4 "arm_hard_general_register_operand" "") 321 (mem:SI (plus:SI (match_dup 5) 322 (const_int -4))))])] 323 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" 324 "ldmdb%?\t%5!, {%1, %2, %3, %4}" 325 [(set_attr "type" "load_16") 326 (set_attr "predicable" "yes")]) 327 328(define_insn "*stm4_db" 329 [(match_parallel 0 "store_multiple_operation" 330 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16))) 331 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 332 (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) 333 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 334 (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) 335 (match_operand:SI 3 "arm_hard_general_register_operand" "")) 336 (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) 337 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] 338 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 339 "stmdb%?\t%5, {%1, %2, %3, %4}" 340 [(set_attr "type" "store_16") 341 (set_attr "predicable" "yes")]) 342 343(define_insn "*stm4_db_update" 344 [(match_parallel 0 "store_multiple_operation" 345 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 346 (plus:SI (match_dup 5) (const_int -16))) 347 (set (mem:SI (plus:SI (match_dup 5) (const_int -16))) 348 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 349 (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) 350 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 351 (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) 352 (match_operand:SI 3 "arm_hard_general_register_operand" "")) 353 (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) 354 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] 355 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" 356 "stmdb%?\t%5!, {%1, %2, %3, %4}" 357 [(set_attr "type" "store_16") 358 (set_attr "predicable" "yes")]) 359 360(define_peephole2 361 [(set (match_operand:SI 0 "s_register_operand" "") 362 (match_operand:SI 4 "memory_operand" "")) 363 (set (match_operand:SI 1 "s_register_operand" "") 364 (match_operand:SI 5 "memory_operand" "")) 365 (set (match_operand:SI 2 "s_register_operand" "") 366 (match_operand:SI 6 "memory_operand" "")) 367 (set (match_operand:SI 3 "s_register_operand" "") 368 (match_operand:SI 7 "memory_operand" ""))] 369 "" 370 [(const_int 0)] 371{ 372 if (gen_ldm_seq (operands, 4, false)) 373 DONE; 374 else 375 FAIL; 376}) 377 378(define_peephole2 379 [(set (match_operand:SI 0 "s_register_operand" "") 380 (match_operand:SI 4 "memory_operand" "")) 381 (parallel 382 [(set (match_operand:SI 1 "s_register_operand" "") 383 (match_operand:SI 5 "memory_operand" "")) 384 (set (match_operand:SI 2 "s_register_operand" "") 385 (match_operand:SI 6 "memory_operand" "")) 386 (set (match_operand:SI 3 "s_register_operand" "") 387 (match_operand:SI 7 "memory_operand" ""))])] 388 "" 389 [(const_int 0)] 390{ 391 if (gen_ldm_seq (operands, 4, false)) 392 DONE; 393 else 394 FAIL; 395}) 396 397(define_peephole2 398 [(set (match_operand:SI 0 "s_register_operand" "") 399 (match_operand:SI 8 "const_int_operand" "")) 400 (set (match_operand:SI 4 "memory_operand" "") 401 (match_dup 0)) 402 (set (match_operand:SI 1 "s_register_operand" "") 403 (match_operand:SI 9 "const_int_operand" "")) 404 (set (match_operand:SI 5 "memory_operand" "") 405 (match_dup 1)) 406 (set (match_operand:SI 2 "s_register_operand" "") 407 (match_operand:SI 10 "const_int_operand" "")) 408 (set (match_operand:SI 6 "memory_operand" "") 409 (match_dup 2)) 410 (set (match_operand:SI 3 "s_register_operand" "") 411 (match_operand:SI 11 "const_int_operand" "")) 412 (set (match_operand:SI 7 "memory_operand" "") 413 (match_dup 3))] 414 "" 415 [(const_int 0)] 416{ 417 if (gen_const_stm_seq (operands, 4)) 418 DONE; 419 else 420 FAIL; 421}) 422 423(define_peephole2 424 [(set (match_operand:SI 0 "s_register_operand" "") 425 (match_operand:SI 8 "const_int_operand" "")) 426 (set (match_operand:SI 1 "s_register_operand" "") 427 (match_operand:SI 9 "const_int_operand" "")) 428 (set (match_operand:SI 2 "s_register_operand" "") 429 (match_operand:SI 10 "const_int_operand" "")) 430 (set (match_operand:SI 3 "s_register_operand" "") 431 (match_operand:SI 11 "const_int_operand" "")) 432 (set (match_operand:SI 4 "memory_operand" "") 433 (match_dup 0)) 434 (set (match_operand:SI 5 "memory_operand" "") 435 (match_dup 1)) 436 (set (match_operand:SI 6 "memory_operand" "") 437 (match_dup 2)) 438 (set (match_operand:SI 7 "memory_operand" "") 439 (match_dup 3))] 440 "" 441 [(const_int 0)] 442{ 443 if (gen_const_stm_seq (operands, 4)) 444 DONE; 445 else 446 FAIL; 447}) 448 449(define_peephole2 450 [(set (match_operand:SI 4 "memory_operand" "") 451 (match_operand:SI 0 "s_register_operand" "")) 452 (set (match_operand:SI 5 "memory_operand" "") 453 (match_operand:SI 1 "s_register_operand" "")) 454 (set (match_operand:SI 6 "memory_operand" "") 455 (match_operand:SI 2 "s_register_operand" "")) 456 (set (match_operand:SI 7 "memory_operand" "") 457 (match_operand:SI 3 "s_register_operand" ""))] 458 "" 459 [(const_int 0)] 460{ 461 if (gen_stm_seq (operands, 4)) 462 DONE; 463 else 464 FAIL; 465}) 466 467(define_insn "*ldm3_" 468 [(match_parallel 0 "load_multiple_operation" 469 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 470 (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))) 471 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 472 (mem:SI (plus:SI (match_dup 4) 473 (const_int 4)))) 474 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 475 (mem:SI (plus:SI (match_dup 4) 476 (const_int 8))))])] 477 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 478 "ldm%?\t%4, {%1, %2, %3}" 479 [(set_attr "type" "load_12") 480 (set_attr "predicable" "yes")]) 481 482(define_insn "*thumb_ldm3_ia" 483 [(match_parallel 0 "load_multiple_operation" 484 [(set (match_operand:SI 1 "low_register_operand" "") 485 (mem:SI (match_operand:SI 4 "s_register_operand" "l"))) 486 (set (match_operand:SI 2 "low_register_operand" "") 487 (mem:SI (plus:SI (match_dup 4) 488 (const_int 4)))) 489 (set (match_operand:SI 3 "low_register_operand" "") 490 (mem:SI (plus:SI (match_dup 4) 491 (const_int 8))))])] 492 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" 493 "ldmia\t%4, {%1, %2, %3}" 494 [(set_attr "type" "load_12")]) 495 496(define_insn "*ldm3_ia_update" 497 [(match_parallel 0 "load_multiple_operation" 498 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 499 (plus:SI (match_dup 4) (const_int 12))) 500 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 501 (mem:SI (match_dup 4))) 502 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 503 (mem:SI (plus:SI (match_dup 4) 504 (const_int 4)))) 505 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 506 (mem:SI (plus:SI (match_dup 4) 507 (const_int 8))))])] 508 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 509 "ldmia%?\t%4!, {%1, %2, %3}" 510 [(set_attr "type" "load_12") 511 (set_attr "predicable" "yes")]) 512 513(define_insn "*thumb_ldm3_ia_update" 514 [(match_parallel 0 "load_multiple_operation" 515 [(set (match_operand:SI 4 "s_register_operand" "+&l") 516 (plus:SI (match_dup 4) (const_int 12))) 517 (set (match_operand:SI 1 "low_register_operand" "") 518 (mem:SI (match_dup 4))) 519 (set (match_operand:SI 2 "low_register_operand" "") 520 (mem:SI (plus:SI (match_dup 4) 521 (const_int 4)))) 522 (set (match_operand:SI 3 "low_register_operand" "") 523 (mem:SI (plus:SI (match_dup 4) 524 (const_int 8))))])] 525 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" 526 "ldmia\t%4!, {%1, %2, %3}" 527 [(set_attr "type" "load_12")]) 528 529(define_insn "*stm3_" 530 [(match_parallel 0 "store_multiple_operation" 531 [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk")) 532 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 533 (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) 534 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 535 (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) 536 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] 537 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 538 "stm%?\t%4, {%1, %2, %3}" 539 [(set_attr "type" "store_12") 540 (set_attr "predicable" "yes")]) 541 542(define_insn "*stm3_ia_update" 543 [(match_parallel 0 "store_multiple_operation" 544 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 545 (plus:SI (match_dup 4) (const_int 12))) 546 (set (mem:SI (match_dup 4)) 547 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 548 (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) 549 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 550 (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) 551 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] 552 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 553 "stmia%?\t%4!, {%1, %2, %3}" 554 [(set_attr "type" "store_12") 555 (set_attr "predicable" "yes")]) 556 557(define_insn "*thumb_stm3_ia_update" 558 [(match_parallel 0 "store_multiple_operation" 559 [(set (match_operand:SI 4 "s_register_operand" "+&l") 560 (plus:SI (match_dup 4) (const_int 12))) 561 (set (mem:SI (match_dup 4)) 562 (match_operand:SI 1 "low_register_operand" "")) 563 (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) 564 (match_operand:SI 2 "low_register_operand" "")) 565 (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) 566 (match_operand:SI 3 "low_register_operand" ""))])] 567 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" 568 "stmia\t%4!, {%1, %2, %3}" 569 [(set_attr "type" "store_12")]) 570 571(define_insn "*ldm3_ib" 572 [(match_parallel 0 "load_multiple_operation" 573 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 574 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") 575 (const_int 4)))) 576 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 577 (mem:SI (plus:SI (match_dup 4) 578 (const_int 8)))) 579 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 580 (mem:SI (plus:SI (match_dup 4) 581 (const_int 12))))])] 582 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 583 "ldmib%?\t%4, {%1, %2, %3}" 584 [(set_attr "type" "load_12") 585 (set_attr "predicable" "yes")]) 586 587(define_insn "*ldm3_ib_update" 588 [(match_parallel 0 "load_multiple_operation" 589 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 590 (plus:SI (match_dup 4) (const_int 12))) 591 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 592 (mem:SI (plus:SI (match_dup 4) 593 (const_int 4)))) 594 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 595 (mem:SI (plus:SI (match_dup 4) 596 (const_int 8)))) 597 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 598 (mem:SI (plus:SI (match_dup 4) 599 (const_int 12))))])] 600 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 601 "ldmib%?\t%4!, {%1, %2, %3}" 602 [(set_attr "type" "load_12") 603 (set_attr "predicable" "yes")]) 604 605(define_insn "*stm3_ib" 606 [(match_parallel 0 "store_multiple_operation" 607 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4))) 608 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 609 (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) 610 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 611 (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) 612 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] 613 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 614 "stmib%?\t%4, {%1, %2, %3}" 615 [(set_attr "type" "store_12") 616 (set_attr "predicable" "yes")]) 617 618(define_insn "*stm3_ib_update" 619 [(match_parallel 0 "store_multiple_operation" 620 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 621 (plus:SI (match_dup 4) (const_int 12))) 622 (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) 623 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 624 (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) 625 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 626 (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) 627 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] 628 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 629 "stmib%?\t%4!, {%1, %2, %3}" 630 [(set_attr "type" "store_12") 631 (set_attr "predicable" "yes")]) 632 633(define_insn "*ldm3_da" 634 [(match_parallel 0 "load_multiple_operation" 635 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 636 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") 637 (const_int -8)))) 638 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 639 (mem:SI (plus:SI (match_dup 4) 640 (const_int -4)))) 641 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 642 (mem:SI (match_dup 4)))])] 643 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 644 "ldmda%?\t%4, {%1, %2, %3}" 645 [(set_attr "type" "load_12") 646 (set_attr "predicable" "yes")]) 647 648(define_insn "*ldm3_da_update" 649 [(match_parallel 0 "load_multiple_operation" 650 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 651 (plus:SI (match_dup 4) (const_int -12))) 652 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 653 (mem:SI (plus:SI (match_dup 4) 654 (const_int -8)))) 655 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 656 (mem:SI (plus:SI (match_dup 4) 657 (const_int -4)))) 658 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 659 (mem:SI (match_dup 4)))])] 660 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 661 "ldmda%?\t%4!, {%1, %2, %3}" 662 [(set_attr "type" "load_12") 663 (set_attr "predicable" "yes")]) 664 665(define_insn "*stm3_da" 666 [(match_parallel 0 "store_multiple_operation" 667 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8))) 668 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 669 (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) 670 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 671 (set (mem:SI (match_dup 4)) 672 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] 673 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 674 "stmda%?\t%4, {%1, %2, %3}" 675 [(set_attr "type" "store_12") 676 (set_attr "predicable" "yes")]) 677 678(define_insn "*stm3_da_update" 679 [(match_parallel 0 "store_multiple_operation" 680 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 681 (plus:SI (match_dup 4) (const_int -12))) 682 (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) 683 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 684 (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) 685 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 686 (set (mem:SI (match_dup 4)) 687 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] 688 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 689 "stmda%?\t%4!, {%1, %2, %3}" 690 [(set_attr "type" "store_12") 691 (set_attr "predicable" "yes")]) 692 693(define_insn "*ldm3_db" 694 [(match_parallel 0 "load_multiple_operation" 695 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 696 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") 697 (const_int -12)))) 698 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 699 (mem:SI (plus:SI (match_dup 4) 700 (const_int -8)))) 701 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 702 (mem:SI (plus:SI (match_dup 4) 703 (const_int -4))))])] 704 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 705 "ldmdb%?\t%4, {%1, %2, %3}" 706 [(set_attr "type" "load_12") 707 (set_attr "predicable" "yes")]) 708 709(define_insn "*ldm3_db_update" 710 [(match_parallel 0 "load_multiple_operation" 711 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 712 (plus:SI (match_dup 4) (const_int -12))) 713 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 714 (mem:SI (plus:SI (match_dup 4) 715 (const_int -12)))) 716 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 717 (mem:SI (plus:SI (match_dup 4) 718 (const_int -8)))) 719 (set (match_operand:SI 3 "arm_hard_general_register_operand" "") 720 (mem:SI (plus:SI (match_dup 4) 721 (const_int -4))))])] 722 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 723 "ldmdb%?\t%4!, {%1, %2, %3}" 724 [(set_attr "type" "load_12") 725 (set_attr "predicable" "yes")]) 726 727(define_insn "*stm3_db" 728 [(match_parallel 0 "store_multiple_operation" 729 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12))) 730 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 731 (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) 732 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 733 (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) 734 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] 735 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 736 "stmdb%?\t%4, {%1, %2, %3}" 737 [(set_attr "type" "store_12") 738 (set_attr "predicable" "yes")]) 739 740(define_insn "*stm3_db_update" 741 [(match_parallel 0 "store_multiple_operation" 742 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 743 (plus:SI (match_dup 4) (const_int -12))) 744 (set (mem:SI (plus:SI (match_dup 4) (const_int -12))) 745 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 746 (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) 747 (match_operand:SI 2 "arm_hard_general_register_operand" "")) 748 (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) 749 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] 750 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 751 "stmdb%?\t%4!, {%1, %2, %3}" 752 [(set_attr "type" "store_12") 753 (set_attr "predicable" "yes")]) 754 755(define_peephole2 756 [(set (match_operand:SI 0 "s_register_operand" "") 757 (match_operand:SI 3 "memory_operand" "")) 758 (set (match_operand:SI 1 "s_register_operand" "") 759 (match_operand:SI 4 "memory_operand" "")) 760 (set (match_operand:SI 2 "s_register_operand" "") 761 (match_operand:SI 5 "memory_operand" ""))] 762 "" 763 [(const_int 0)] 764{ 765 if (gen_ldm_seq (operands, 3, false)) 766 DONE; 767 else 768 FAIL; 769}) 770 771(define_peephole2 772 [(set (match_operand:SI 0 "s_register_operand" "") 773 (match_operand:SI 3 "memory_operand" "")) 774 (parallel 775 [(set (match_operand:SI 1 "s_register_operand" "") 776 (match_operand:SI 4 "memory_operand" "")) 777 (set (match_operand:SI 2 "s_register_operand" "") 778 (match_operand:SI 5 "memory_operand" ""))])] 779 "" 780 [(const_int 0)] 781{ 782 if (gen_ldm_seq (operands, 3, false)) 783 DONE; 784 else 785 FAIL; 786}) 787 788(define_peephole2 789 [(set (match_operand:SI 0 "s_register_operand" "") 790 (match_operand:SI 6 "const_int_operand" "")) 791 (set (match_operand:SI 3 "memory_operand" "") 792 (match_dup 0)) 793 (set (match_operand:SI 1 "s_register_operand" "") 794 (match_operand:SI 7 "const_int_operand" "")) 795 (set (match_operand:SI 4 "memory_operand" "") 796 (match_dup 1)) 797 (set (match_operand:SI 2 "s_register_operand" "") 798 (match_operand:SI 8 "const_int_operand" "")) 799 (set (match_operand:SI 5 "memory_operand" "") 800 (match_dup 2))] 801 "" 802 [(const_int 0)] 803{ 804 if (gen_const_stm_seq (operands, 3)) 805 DONE; 806 else 807 FAIL; 808}) 809 810(define_peephole2 811 [(set (match_operand:SI 0 "s_register_operand" "") 812 (match_operand:SI 6 "const_int_operand" "")) 813 (set (match_operand:SI 1 "s_register_operand" "") 814 (match_operand:SI 7 "const_int_operand" "")) 815 (set (match_operand:SI 2 "s_register_operand" "") 816 (match_operand:SI 8 "const_int_operand" "")) 817 (set (match_operand:SI 3 "memory_operand" "") 818 (match_dup 0)) 819 (set (match_operand:SI 4 "memory_operand" "") 820 (match_dup 1)) 821 (set (match_operand:SI 5 "memory_operand" "") 822 (match_dup 2))] 823 "" 824 [(const_int 0)] 825{ 826 if (gen_const_stm_seq (operands, 3)) 827 DONE; 828 else 829 FAIL; 830}) 831 832(define_peephole2 833 [(set (match_operand:SI 3 "memory_operand" "") 834 (match_operand:SI 0 "s_register_operand" "")) 835 (set (match_operand:SI 4 "memory_operand" "") 836 (match_operand:SI 1 "s_register_operand" "")) 837 (set (match_operand:SI 5 "memory_operand" "") 838 (match_operand:SI 2 "s_register_operand" ""))] 839 "" 840 [(const_int 0)] 841{ 842 if (gen_stm_seq (operands, 3)) 843 DONE; 844 else 845 FAIL; 846}) 847 848(define_insn "*ldm2_" 849 [(match_parallel 0 "load_multiple_operation" 850 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 851 (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))) 852 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 853 (mem:SI (plus:SI (match_dup 3) 854 (const_int 4))))])] 855 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" 856 "ldm%?\t%3, {%1, %2}" 857 [(set_attr "type" "load_8") 858 (set_attr "predicable" "yes")]) 859 860(define_insn "*thumb_ldm2_ia" 861 [(match_parallel 0 "load_multiple_operation" 862 [(set (match_operand:SI 1 "low_register_operand" "") 863 (mem:SI (match_operand:SI 3 "s_register_operand" "l"))) 864 (set (match_operand:SI 2 "low_register_operand" "") 865 (mem:SI (plus:SI (match_dup 3) 866 (const_int 4))))])] 867 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" 868 "ldmia\t%3, {%1, %2}" 869 [(set_attr "type" "load_8")]) 870 871(define_insn "*ldm2_ia_update" 872 [(match_parallel 0 "load_multiple_operation" 873 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 874 (plus:SI (match_dup 3) (const_int 8))) 875 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 876 (mem:SI (match_dup 3))) 877 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 878 (mem:SI (plus:SI (match_dup 3) 879 (const_int 4))))])] 880 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 881 "ldmia%?\t%3!, {%1, %2}" 882 [(set_attr "type" "load_8") 883 (set_attr "predicable" "yes")]) 884 885(define_insn "*thumb_ldm2_ia_update" 886 [(match_parallel 0 "load_multiple_operation" 887 [(set (match_operand:SI 3 "s_register_operand" "+&l") 888 (plus:SI (match_dup 3) (const_int 8))) 889 (set (match_operand:SI 1 "low_register_operand" "") 890 (mem:SI (match_dup 3))) 891 (set (match_operand:SI 2 "low_register_operand" "") 892 (mem:SI (plus:SI (match_dup 3) 893 (const_int 4))))])] 894 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" 895 "ldmia\t%3!, {%1, %2}" 896 [(set_attr "type" "load_8")]) 897 898(define_insn "*stm2_" 899 [(match_parallel 0 "store_multiple_operation" 900 [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk")) 901 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 902 (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) 903 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] 904 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" 905 "stm%?\t%3, {%1, %2}" 906 [(set_attr "type" "store_8") 907 (set_attr "predicable" "yes")]) 908 909(define_insn "*stm2_ia_update" 910 [(match_parallel 0 "store_multiple_operation" 911 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 912 (plus:SI (match_dup 3) (const_int 8))) 913 (set (mem:SI (match_dup 3)) 914 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 915 (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) 916 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] 917 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 918 "stmia%?\t%3!, {%1, %2}" 919 [(set_attr "type" "store_8") 920 (set_attr "predicable" "yes")]) 921 922(define_insn "*thumb_stm2_ia_update" 923 [(match_parallel 0 "store_multiple_operation" 924 [(set (match_operand:SI 3 "s_register_operand" "+&l") 925 (plus:SI (match_dup 3) (const_int 8))) 926 (set (mem:SI (match_dup 3)) 927 (match_operand:SI 1 "low_register_operand" "")) 928 (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) 929 (match_operand:SI 2 "low_register_operand" ""))])] 930 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" 931 "stmia\t%3!, {%1, %2}" 932 [(set_attr "type" "store_8")]) 933 934(define_insn "*ldm2_ib" 935 [(match_parallel 0 "load_multiple_operation" 936 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 937 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") 938 (const_int 4)))) 939 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 940 (mem:SI (plus:SI (match_dup 3) 941 (const_int 8))))])] 942 "TARGET_ARM && XVECLEN (operands[0], 0) == 2" 943 "ldmib%?\t%3, {%1, %2}" 944 [(set_attr "type" "load_8") 945 (set_attr "predicable" "yes")]) 946 947(define_insn "*ldm2_ib_update" 948 [(match_parallel 0 "load_multiple_operation" 949 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 950 (plus:SI (match_dup 3) (const_int 8))) 951 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 952 (mem:SI (plus:SI (match_dup 3) 953 (const_int 4)))) 954 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 955 (mem:SI (plus:SI (match_dup 3) 956 (const_int 8))))])] 957 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 958 "ldmib%?\t%3!, {%1, %2}" 959 [(set_attr "type" "load_8") 960 (set_attr "predicable" "yes")]) 961 962(define_insn "*stm2_ib" 963 [(match_parallel 0 "store_multiple_operation" 964 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4))) 965 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 966 (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) 967 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] 968 "TARGET_ARM && XVECLEN (operands[0], 0) == 2" 969 "stmib%?\t%3, {%1, %2}" 970 [(set_attr "type" "store_8") 971 (set_attr "predicable" "yes")]) 972 973(define_insn "*stm2_ib_update" 974 [(match_parallel 0 "store_multiple_operation" 975 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 976 (plus:SI (match_dup 3) (const_int 8))) 977 (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) 978 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 979 (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) 980 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] 981 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 982 "stmib%?\t%3!, {%1, %2}" 983 [(set_attr "type" "store_8") 984 (set_attr "predicable" "yes")]) 985 986(define_insn "*ldm2_da" 987 [(match_parallel 0 "load_multiple_operation" 988 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 989 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") 990 (const_int -4)))) 991 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 992 (mem:SI (match_dup 3)))])] 993 "TARGET_ARM && XVECLEN (operands[0], 0) == 2" 994 "ldmda%?\t%3, {%1, %2}" 995 [(set_attr "type" "load_8") 996 (set_attr "predicable" "yes")]) 997 998(define_insn "*ldm2_da_update" 999 [(match_parallel 0 "load_multiple_operation" 1000 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 1001 (plus:SI (match_dup 3) (const_int -8))) 1002 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 1003 (mem:SI (plus:SI (match_dup 3) 1004 (const_int -4)))) 1005 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 1006 (mem:SI (match_dup 3)))])] 1007 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 1008 "ldmda%?\t%3!, {%1, %2}" 1009 [(set_attr "type" "load_8") 1010 (set_attr "predicable" "yes")]) 1011 1012(define_insn "*stm2_da" 1013 [(match_parallel 0 "store_multiple_operation" 1014 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4))) 1015 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 1016 (set (mem:SI (match_dup 3)) 1017 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] 1018 "TARGET_ARM && XVECLEN (operands[0], 0) == 2" 1019 "stmda%?\t%3, {%1, %2}" 1020 [(set_attr "type" "store_8") 1021 (set_attr "predicable" "yes")]) 1022 1023(define_insn "*stm2_da_update" 1024 [(match_parallel 0 "store_multiple_operation" 1025 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 1026 (plus:SI (match_dup 3) (const_int -8))) 1027 (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) 1028 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 1029 (set (mem:SI (match_dup 3)) 1030 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] 1031 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 1032 "stmda%?\t%3!, {%1, %2}" 1033 [(set_attr "type" "store_8") 1034 (set_attr "predicable" "yes")]) 1035 1036(define_insn "*ldm2_db" 1037 [(match_parallel 0 "load_multiple_operation" 1038 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") 1039 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") 1040 (const_int -8)))) 1041 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 1042 (mem:SI (plus:SI (match_dup 3) 1043 (const_int -4))))])] 1044 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" 1045 "ldmdb%?\t%3, {%1, %2}" 1046 [(set_attr "type" "load_8") 1047 (set_attr "predicable" "yes")]) 1048 1049(define_insn "*ldm2_db_update" 1050 [(match_parallel 0 "load_multiple_operation" 1051 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 1052 (plus:SI (match_dup 3) (const_int -8))) 1053 (set (match_operand:SI 1 "arm_hard_general_register_operand" "") 1054 (mem:SI (plus:SI (match_dup 3) 1055 (const_int -8)))) 1056 (set (match_operand:SI 2 "arm_hard_general_register_operand" "") 1057 (mem:SI (plus:SI (match_dup 3) 1058 (const_int -4))))])] 1059 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 1060 "ldmdb%?\t%3!, {%1, %2}" 1061 [(set_attr "type" "load_8") 1062 (set_attr "predicable" "yes")]) 1063 1064(define_insn "*stm2_db" 1065 [(match_parallel 0 "store_multiple_operation" 1066 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8))) 1067 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 1068 (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) 1069 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] 1070 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" 1071 "stmdb%?\t%3, {%1, %2}" 1072 [(set_attr "type" "store_8") 1073 (set_attr "predicable" "yes")]) 1074 1075(define_insn "*stm2_db_update" 1076 [(match_parallel 0 "store_multiple_operation" 1077 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 1078 (plus:SI (match_dup 3) (const_int -8))) 1079 (set (mem:SI (plus:SI (match_dup 3) (const_int -8))) 1080 (match_operand:SI 1 "arm_hard_general_register_operand" "")) 1081 (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) 1082 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] 1083 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 1084 "stmdb%?\t%3!, {%1, %2}" 1085 [(set_attr "type" "store_8") 1086 (set_attr "predicable" "yes")]) 1087 1088(define_peephole2 1089 [(set (match_operand:SI 0 "s_register_operand" "") 1090 (match_operand:SI 2 "memory_operand" "")) 1091 (set (match_operand:SI 1 "s_register_operand" "") 1092 (match_operand:SI 3 "memory_operand" ""))] 1093 "" 1094 [(const_int 0)] 1095{ 1096 if (gen_ldm_seq (operands, 2, false)) 1097 DONE; 1098 else 1099 FAIL; 1100}) 1101 1102(define_peephole2 1103 [(set (match_operand:SI 0 "s_register_operand" "") 1104 (match_operand:SI 4 "const_int_operand" "")) 1105 (set (match_operand:SI 2 "memory_operand" "") 1106 (match_dup 0)) 1107 (set (match_operand:SI 1 "s_register_operand" "") 1108 (match_operand:SI 5 "const_int_operand" "")) 1109 (set (match_operand:SI 3 "memory_operand" "") 1110 (match_dup 1))] 1111 "" 1112 [(const_int 0)] 1113{ 1114 if (gen_const_stm_seq (operands, 2)) 1115 DONE; 1116 else 1117 FAIL; 1118}) 1119 1120(define_peephole2 1121 [(set (match_operand:SI 0 "s_register_operand" "") 1122 (match_operand:SI 4 "const_int_operand" "")) 1123 (set (match_operand:SI 1 "s_register_operand" "") 1124 (match_operand:SI 5 "const_int_operand" "")) 1125 (set (match_operand:SI 2 "memory_operand" "") 1126 (match_dup 0)) 1127 (set (match_operand:SI 3 "memory_operand" "") 1128 (match_dup 1))] 1129 "" 1130 [(const_int 0)] 1131{ 1132 if (gen_const_stm_seq (operands, 2)) 1133 DONE; 1134 else 1135 FAIL; 1136}) 1137 1138(define_peephole2 1139 [(set (match_operand:SI 2 "memory_operand" "") 1140 (match_operand:SI 0 "s_register_operand" "")) 1141 (set (match_operand:SI 3 "memory_operand" "") 1142 (match_operand:SI 1 "s_register_operand" ""))] 1143 "" 1144 [(const_int 0)] 1145{ 1146 if (gen_stm_seq (operands, 2)) 1147 DONE; 1148 else 1149 FAIL; 1150}) 1151 1152(define_peephole2 1153 [(set (match_operand:SI 0 "s_register_operand" "") 1154 (match_operand:SI 2 "memory_operand" "")) 1155 (set (match_operand:SI 1 "s_register_operand" "") 1156 (match_operand:SI 3 "memory_operand" "")) 1157 (parallel 1158 [(set (match_operand:SI 4 "s_register_operand" "") 1159 (match_operator:SI 5 "commutative_binary_operator" 1160 [(match_operand:SI 6 "s_register_operand" "") 1161 (match_operand:SI 7 "s_register_operand" "")])) 1162 (clobber (reg:CC CC_REGNUM))])] 1163 "((((REGNO (operands[6]) == REGNO (operands[0])) 1164 && (REGNO (operands[7]) == REGNO (operands[1]))) 1165 || ((REGNO (operands[7]) == REGNO (operands[0])) 1166 && (REGNO (operands[6]) == REGNO (operands[1])))) 1167 && (peep2_regno_dead_p (3, REGNO (operands[0])) 1168 || (REGNO (operands[0]) == REGNO (operands[4]))) 1169 && (peep2_regno_dead_p (3, REGNO (operands[1])) 1170 || (REGNO (operands[1]) == REGNO (operands[4]))))" 1171 [(parallel 1172 [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)])) 1173 (clobber (reg:CC CC_REGNUM))])] 1174{ 1175 if (!gen_ldm_seq (operands, 2, true)) 1176 FAIL; 1177}) 1178 1179(define_peephole2 1180 [(set (match_operand:SI 0 "s_register_operand" "") 1181 (match_operand:SI 2 "memory_operand" "")) 1182 (set (match_operand:SI 1 "s_register_operand" "") 1183 (match_operand:SI 3 "memory_operand" "")) 1184 (set (match_operand:SI 4 "s_register_operand" "") 1185 (match_operator:SI 5 "commutative_binary_operator" 1186 [(match_operand:SI 6 "s_register_operand" "") 1187 (match_operand:SI 7 "s_register_operand" "")]))] 1188 "((((REGNO (operands[6]) == REGNO (operands[0])) 1189 && (REGNO (operands[7]) == REGNO (operands[1]))) 1190 || ((REGNO (operands[7]) == REGNO (operands[0])) 1191 && (REGNO (operands[6]) == REGNO (operands[1])))) 1192 && (peep2_regno_dead_p (3, REGNO (operands[0])) 1193 || (REGNO (operands[0]) == REGNO (operands[4]))) 1194 && (peep2_regno_dead_p (3, REGNO (operands[1])) 1195 || (REGNO (operands[1]) == REGNO (operands[4]))))" 1196 [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))] 1197{ 1198 if (!gen_ldm_seq (operands, 2, true)) 1199 FAIL; 1200}) 1201 1202