1;; GCC machine description for Renesas H8/300 2;; Copyright (C) 1992-2022 Free Software Foundation, Inc. 3 4;; Contributed by Steve Chamberlain (sac@cygnus.com), 5;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). 6 7;; This file is part of GCC. 8 9;; GCC is free software; you can redistribute it and/or modify 10;; it under the terms of the GNU General Public License as published by 11;; the Free Software Foundation; either version 3, or (at your option) 12;; any later version. 13 14;; GCC is distributed in the hope that it will be useful, 15;; but WITHOUT ANY WARRANTY; without even the implied warranty of 16;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17;; GNU General Public License for more details. 18 19;; You should have received a copy of the GNU General Public License 20;; along with GCC; see the file COPYING3. If not see 21;; <http://www.gnu.org/licenses/>. 22 23;; We compute exact length on each instruction for most of the time. 24;; In some case, most notably bit operations that may involve memory 25;; operands, the lengths in this file are "worst case". 26 27;; On the H8/300H and H8S, adds/subs operate on the 32bit "er" 28;; registers. Right now GCC doesn't expose the "e" half to the 29;; compiler, so using add/subs for addhi and subhi is safe. Long 30;; term, we want to expose the "e" half to the compiler (gives us 8 31;; more 16bit registers). At that point addhi and subhi can't use 32;; adds/subs. 33 34;; There's currently no way to have an insv/extzv expander for the H8/300H 35;; because word_mode is different for the H8/300 and H8/300H. 36 37;; Shifts/rotates by small constants should be handled by special 38;; patterns so we get the length and cc status correct. 39 40;; Bitfield operations no longer accept memory operands. We need 41;; to add variants which operate on memory back to the MD. 42 43;; ??? Implement remaining bit ops available on the h8300 44 45;; ---------------------------------------------------------------------- 46;; CONSTANTS 47;; ---------------------------------------------------------------------- 48 49(define_constants 50 [(UNSPEC_INCDEC 0) 51 (UNSPEC_MONITOR 1)]) 52 53(define_constants 54 [(UNSPEC_MOVMD 100) 55 (UNSPEC_STPCPY 101)]) 56 57(define_constants 58 [(R0_REG 0) 59 (SC_REG 3) 60 (COUNTER_REG 4) 61 (SOURCE_REG 5) 62 (DESTINATION_REG 6) 63 (HFP_REG 6) 64 (SP_REG 7) 65 (MAC_REG 8) 66 (AP_REG 9) 67 (RAP_REG 10) 68 (FP_REG 11) 69 (CC_REG 12)]) 70 71;; ---------------------------------------------------------------------- 72;; ATTRIBUTES 73;; ---------------------------------------------------------------------- 74 75(define_attr "cpu" "h8300,h8300h" 76 (const (symbol_ref "cpu_type"))) 77 78(define_attr "type" "branch,arith,bitbranch,call" 79 (const_string "arith")) 80 81(define_attr "length_table" "none,add,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch" 82 (const_string "none")) 83 84;; The size of instructions in bytes. 85 86(define_attr "length" "" 87 (cond [(eq_attr "type" "branch") 88 ;; In a forward delayed branch, (pc) represents the end of the 89 ;; delay sequence, not the end of the branch itself. 90 (if_then_else (and (ge (minus (match_dup 0) (pc)) 91 (const_int -126)) 92 (le (plus (minus (match_dup 0) (pc)) 93 (symbol_ref "DELAY_SLOT_LENGTH (insn)")) 94 (const_int 125))) 95 (const_int 2) 96 (if_then_else (and (eq_attr "cpu" "h8300h") 97 (and (ge (minus (pc) (match_dup 0)) 98 (const_int -32000)) 99 (le (minus (pc) (match_dup 0)) 100 (const_int 32000)))) 101 (const_int 4) 102 (const_int 6))) 103 (eq_attr "type" "bitbranch") 104 (if_then_else (and (ge (minus (match_dup 0) (pc)) 105 (const_int -126)) 106 (le (minus (match_dup 0) (pc)) 107 (const_int 126))) 108 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)") 109 (const_int 2)) 110 (if_then_else (and (eq_attr "cpu" "h8300h") 111 (and (ge (minus (pc) (match_dup 0)) 112 (const_int -32000)) 113 (le (minus (pc) (match_dup 0)) 114 (const_int 32000)))) 115 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)") 116 (const_int 4)) 117 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)") 118 (const_int 6)))) 119 (eq_attr "length_table" "!none") 120 (symbol_ref "h8300_insn_length_from_table (insn, operands)")] 121 (const_int 200))) 122 123;; Condition code settings. 124;; 125;; none - insn does not affect cc 126;; none_0hit - insn does not affect cc but it does modify operand 0 127;; This attribute is used to keep track of when operand 0 changes. 128;; See the description of NOTICE_UPDATE_CC for more info. 129;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown. 130;; set_zn - insn sets z,n to usable values; v,c are unknown. 131;; compare - compare instruction 132;; clobber - value of cc is unknown 133 134(define_attr "old_cc" "none,none_0hit,set_znv,set_zn,compare,clobber" 135 (const_string "clobber")) 136 137;; So the idea here is to define iterators and substitutions so that we 138;; can easily modify the patterns with CC clobbers into a pattern 139;; which sets appropriate condition codes 140 141;; The modes we're supporting. This is used when we want to generate 142;; multiple patterns where only the mode differs from a single template 143(define_mode_iterator H8cc [CC CCZN CCZ]) 144 145;; This is used to generate multiple define_substs from a single 146;; template for the different variants we might have. 147(define_mode_attr cc [(CC "cc") (CCZN "cczn") (CCZ "ccz")]) 148 149;; The primary substitution pattern. <cc> is used to create multiple 150;; substitutions based on the CC bits that are set. 151;; 152;; The mode iterator sets the actual mode on the condition code 153;; REG expression. 154(define_subst "subst_<cc>" 155 [(set (match_operand 0 "") 156 (match_operand 1 "")) 157 (clobber (reg:CC CC_REG))] 158 "" 159 [(set (reg:H8cc CC_REG) 160 (compare:H8cc (match_dup 1) (const_int 0))) 161 (set (match_dup 0) (match_dup 1))]) 162 163 164;; So when we see <cc> or <cczn> in a define_insn pattern, we'll 165;; apply the subst_cczn or subset_cc define_subst to generate a 166;; new pattern that compare-elim can use 167(define_subst_attr "cczn" "subst_cczn" "" "_cczn") 168(define_subst_attr "ccz" "subst_ccz" "" "_ccz") 169(define_subst_attr "cc" "subst_cc" "" "_cc") 170 171;; Type of delay slot. NONE means the instruction has no delay slot. 172;; JUMP means it is an unconditional jump that (if short enough) 173;; could be implemented using bra/s. 174 175(define_attr "delay_slot" "none,jump" 176 (const_string "none")) 177 178;; "yes" if the instruction can be put into a delay slot. It's not 179;; entirely clear that jsr is not valid in delay slots, but it 180;; definitely doesn't have the effect of causing the called function 181;; to return to the target of the delayed branch. 182 183(define_attr "can_delay" "no,yes" 184 (cond [(eq_attr "type" "branch,bitbranch,call") 185 (const_string "no") 186 (geu (symbol_ref "get_attr_length (insn)") (const_int 2)) 187 (const_string "no")] 188 (const_string "yes"))) 189 190;; Only allow jumps to have a delay slot if we think they might 191;; be short enough. This is just an optimization: we don't know 192;; for certain whether they will be or not. 193 194(define_delay (and (eq_attr "delay_slot" "jump") 195 (eq (symbol_ref "get_attr_length (insn)") (const_int 2))) 196 [(eq_attr "can_delay" "yes") 197 (nil) 198 (nil)]) 199 200;; Provide the maximum length of an assembly instruction in an asm 201;; statement. The maximum length of 14 bytes is achieved on H8SX. 202 203(define_asm_attributes 204 [(set (attr "length") 205 (cond [(match_test "TARGET_H8300H") (const_int 10) 206 (match_test "TARGET_H8300S") (const_int 10)] 207 (const_int 14)))]) 208 209(include "predicates.md") 210(include "constraints.md") 211 212;; ---------------------------------------------------------------------- 213;; MACRO DEFINITIONS 214;; ---------------------------------------------------------------------- 215 216;; This mode iterator allows :P to be used for patterns that operate on 217;; pointer-sized quantities. Exactly one of the two alternatives will match. 218 219(define_mode_iterator P [(HI "Pmode == HImode") (SI "Pmode == SImode")]) 220 221(define_mode_iterator QHI [QI HI]) 222 223(define_mode_iterator HSI [HI SI]) 224 225(define_mode_iterator QHSI [QI HI SI]) 226(define_mode_iterator QHSI2 [QI HI SI]) 227 228(define_mode_iterator QHSIF [QI HI SI SF]) 229 230(define_mode_iterator SFI [SF SI]) 231 232(define_code_iterator shifts [ashift ashiftrt lshiftrt]) 233 234(define_code_iterator logicals [ior xor and]) 235 236(define_code_iterator ors [ior xor]) 237 238(define_code_iterator eqne [eq ne]) 239 240;; For storing the C flag, map from the unsigned comparison to the right 241;; code for testing the C bit. 242(define_code_iterator geultu [geu ltu]) 243(define_code_attr geultu_to_c [(geu "eq") (ltu "ne")]) 244 245 246(include "movepush.md") 247(include "mova.md") 248(include "testcompare.md") 249(include "addsub.md") 250(include "multiply.md") 251(include "divmod.md") 252(include "logical.md") 253(include "other.md") 254(include "jumpcall.md") 255(include "proepi.md") 256(include "extensions.md") 257(include "shiftrotate.md") 258(include "bitfield.md") 259(include "combiner.md") 260;;(include "peepholes.md") 261