1 /* Subroutines used for code generation for RISC-V.
2 Copyright (C) 2011-2022 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #define IN_TARGET_CODE 1
23
24 #define INCLUDE_STRING
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "tm.h"
29 #include "rtl.h"
30 #include "regs.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
33 #include "recog.h"
34 #include "output.h"
35 #include "alias.h"
36 #include "tree.h"
37 #include "stringpool.h"
38 #include "attribs.h"
39 #include "varasm.h"
40 #include "stor-layout.h"
41 #include "calls.h"
42 #include "function.h"
43 #include "explow.h"
44 #include "memmodel.h"
45 #include "emit-rtl.h"
46 #include "reload.h"
47 #include "tm_p.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "basic-block.h"
51 #include "expr.h"
52 #include "optabs.h"
53 #include "bitmap.h"
54 #include "df.h"
55 #include "diagnostic.h"
56 #include "builtins.h"
57 #include "predict.h"
58 #include "tree-pass.h"
59 #include "opts.h"
60
61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
69 XVECEXP (X, 0, 0)
70
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74
75 /* True if bit BIT is set in VALUE. */
76 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
77
78 /* Classifies an address.
79
80 ADDRESS_REG
81 A natural register + offset address. The register satisfies
82 riscv_valid_base_register_p and the offset is a const_arith_operand.
83
84 ADDRESS_LO_SUM
85 A LO_SUM rtx. The first operand is a valid base register and
86 the second operand is a symbolic address.
87
88 ADDRESS_CONST_INT
89 A signed 16-bit constant address.
90
91 ADDRESS_SYMBOLIC:
92 A constant symbolic address. */
93 enum riscv_address_type {
94 ADDRESS_REG,
95 ADDRESS_LO_SUM,
96 ADDRESS_CONST_INT,
97 ADDRESS_SYMBOLIC
98 };
99
100 /* Information about a function's frame layout. */
101 struct GTY(()) riscv_frame_info {
102 /* The size of the frame in bytes. */
103 HOST_WIDE_INT total_size;
104
105 /* Bit X is set if the function saves or restores GPR X. */
106 unsigned int mask;
107
108 /* Likewise FPR X. */
109 unsigned int fmask;
110
111 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */
112 unsigned save_libcall_adjustment;
113
114 /* Offsets of fixed-point and floating-point save areas from frame bottom */
115 HOST_WIDE_INT gp_sp_offset;
116 HOST_WIDE_INT fp_sp_offset;
117
118 /* Offset of virtual frame pointer from stack pointer/frame bottom */
119 HOST_WIDE_INT frame_pointer_offset;
120
121 /* Offset of hard frame pointer from stack pointer/frame bottom */
122 HOST_WIDE_INT hard_frame_pointer_offset;
123
124 /* The offset of arg_pointer_rtx from the bottom of the frame. */
125 HOST_WIDE_INT arg_pointer_offset;
126 };
127
128 enum riscv_privilege_levels {
129 UNKNOWN_MODE, USER_MODE, SUPERVISOR_MODE, MACHINE_MODE
130 };
131
132 struct GTY(()) machine_function {
133 /* The number of extra stack bytes taken up by register varargs.
134 This area is allocated by the callee at the very top of the frame. */
135 int varargs_size;
136
137 /* True if current function is a naked function. */
138 bool naked_p;
139
140 /* True if current function is an interrupt function. */
141 bool interrupt_handler_p;
142 /* For an interrupt handler, indicates the privilege level. */
143 enum riscv_privilege_levels interrupt_mode;
144
145 /* True if attributes on current function have been checked. */
146 bool attributes_checked_p;
147
148 /* The current frame information, calculated by riscv_compute_frame_info. */
149 struct riscv_frame_info frame;
150 };
151
152 /* Information about a single argument. */
153 struct riscv_arg_info {
154 /* True if the argument is at least partially passed on the stack. */
155 bool stack_p;
156
157 /* The number of integer registers allocated to this argument. */
158 unsigned int num_gprs;
159
160 /* The offset of the first register used, provided num_gprs is nonzero.
161 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */
162 unsigned int gpr_offset;
163
164 /* The number of floating-point registers allocated to this argument. */
165 unsigned int num_fprs;
166
167 /* The offset of the first register used, provided num_fprs is nonzero. */
168 unsigned int fpr_offset;
169 };
170
171 /* Information about an address described by riscv_address_type.
172
173 ADDRESS_CONST_INT
174 No fields are used.
175
176 ADDRESS_REG
177 REG is the base register and OFFSET is the constant offset.
178
179 ADDRESS_LO_SUM
180 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
181 is the type of symbol it references.
182
183 ADDRESS_SYMBOLIC
184 SYMBOL_TYPE is the type of symbol that the address references. */
185 struct riscv_address_info {
186 enum riscv_address_type type;
187 rtx reg;
188 rtx offset;
189 enum riscv_symbol_type symbol_type;
190 };
191
192 /* One stage in a constant building sequence. These sequences have
193 the form:
194
195 A = VALUE[0]
196 A = A CODE[1] VALUE[1]
197 A = A CODE[2] VALUE[2]
198 ...
199
200 where A is an accumulator, each CODE[i] is a binary rtl operation
201 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
202 struct riscv_integer_op {
203 enum rtx_code code;
204 unsigned HOST_WIDE_INT value;
205 };
206
207 /* The largest number of operations needed to load an integer constant.
208 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
209 #define RISCV_MAX_INTEGER_OPS 8
210
211 /* Costs of various operations on the different architectures. */
212
213 struct riscv_tune_param
214 {
215 unsigned short fp_add[2];
216 unsigned short fp_mul[2];
217 unsigned short fp_div[2];
218 unsigned short int_mul[2];
219 unsigned short int_div[2];
220 unsigned short issue_rate;
221 unsigned short branch_cost;
222 unsigned short memory_cost;
223 unsigned short fmv_cost;
224 bool slow_unaligned_access;
225 };
226
227 /* Information about one micro-arch we know about. */
228 struct riscv_tune_info {
229 /* This micro-arch canonical name. */
230 const char *name;
231
232 /* Which automaton to use for tuning. */
233 enum riscv_microarchitecture_type microarchitecture;
234
235 /* Tuning parameters for this micro-arch. */
236 const struct riscv_tune_param *tune_param;
237 };
238
239 /* Global variables for machine-dependent things. */
240
241 /* Whether unaligned accesses execute very slowly. */
242 bool riscv_slow_unaligned_access_p;
243
244 /* Stack alignment to assume/maintain. */
245 unsigned riscv_stack_boundary;
246
247 /* If non-zero, this is an offset to be added to SP to redefine the CFA
248 when restoring the FP register from the stack. Only valid when generating
249 the epilogue. */
250 static int epilogue_cfa_sp_offset;
251
252 /* Which tuning parameters to use. */
253 static const struct riscv_tune_param *tune_param;
254
255 /* Which automaton to use for tuning. */
256 enum riscv_microarchitecture_type riscv_microarchitecture;
257
258 /* Index R is the smallest register class that contains register R. */
259 const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
260 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
261 GR_REGS, GR_REGS, SIBCALL_REGS, SIBCALL_REGS,
262 JALR_REGS, JALR_REGS, SIBCALL_REGS, SIBCALL_REGS,
263 SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS,
264 SIBCALL_REGS, SIBCALL_REGS, JALR_REGS, JALR_REGS,
265 JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS,
266 JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS,
267 SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS,
268 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
269 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
270 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
271 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
272 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
273 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
274 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
275 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
276 FRAME_REGS, FRAME_REGS,
277 };
278
279 /* Costs to use when optimizing for rocket. */
280 static const struct riscv_tune_param rocket_tune_info = {
281 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
282 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
283 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
284 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
285 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
286 1, /* issue_rate */
287 3, /* branch_cost */
288 5, /* memory_cost */
289 8, /* fmv_cost */
290 true, /* slow_unaligned_access */
291 };
292
293 /* Costs to use when optimizing for Sifive 7 Series. */
294 static const struct riscv_tune_param sifive_7_tune_info = {
295 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
296 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
297 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
298 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
299 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
300 2, /* issue_rate */
301 4, /* branch_cost */
302 3, /* memory_cost */
303 8, /* fmv_cost */
304 true, /* slow_unaligned_access */
305 };
306
307 /* Costs to use when optimizing for T-HEAD c906. */
308 static const struct riscv_tune_param thead_c906_tune_info = {
309 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
310 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
311 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
312 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
313 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
314 1, /* issue_rate */
315 3, /* branch_cost */
316 5, /* memory_cost */
317 8, /* fmv_cost */
318 false, /* slow_unaligned_access */
319 };
320
321 /* Costs to use when optimizing for size. */
322 static const struct riscv_tune_param optimize_size_tune_info = {
323 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */
324 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */
325 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */
326 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */
327 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */
328 1, /* issue_rate */
329 1, /* branch_cost */
330 2, /* memory_cost */
331 8, /* fmv_cost */
332 false, /* slow_unaligned_access */
333 };
334
335 static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
336 static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
337
338 /* Defining target-specific uses of __attribute__. */
339 static const struct attribute_spec riscv_attribute_table[] =
340 {
341 /* Syntax: { name, min_len, max_len, decl_required, type_required,
342 function_type_required, affects_type_identity, handler,
343 exclude } */
344
345 /* The attribute telling no prologue/epilogue. */
346 { "naked", 0, 0, true, false, false, false,
347 riscv_handle_fndecl_attribute, NULL },
348 /* This attribute generates prologue/epilogue for interrupt handlers. */
349 { "interrupt", 0, 1, false, true, true, false,
350 riscv_handle_type_attribute, NULL },
351
352 /* The last attribute spec is set to be NULL. */
353 { NULL, 0, 0, false, false, false, false, NULL, NULL }
354 };
355
356 /* Order for the CLOBBERs/USEs of gpr_save. */
357 static const unsigned gpr_save_reg_order[] = {
358 INVALID_REGNUM, T0_REGNUM, T1_REGNUM, RETURN_ADDR_REGNUM,
359 S0_REGNUM, S1_REGNUM, S2_REGNUM, S3_REGNUM, S4_REGNUM,
360 S5_REGNUM, S6_REGNUM, S7_REGNUM, S8_REGNUM, S9_REGNUM,
361 S10_REGNUM, S11_REGNUM
362 };
363
364 /* A table describing all the processors GCC knows about. */
365 static const struct riscv_tune_info riscv_tune_info_table[] = {
366 { "rocket", generic, &rocket_tune_info },
367 { "sifive-3-series", generic, &rocket_tune_info },
368 { "sifive-5-series", generic, &rocket_tune_info },
369 { "sifive-7-series", sifive_7, &sifive_7_tune_info },
370 { "thead-c906", generic, &thead_c906_tune_info },
371 { "size", generic, &optimize_size_tune_info },
372 };
373
374 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
375
376 static unsigned int
riscv_min_arithmetic_precision(void)377 riscv_min_arithmetic_precision (void)
378 {
379 return 32;
380 }
381
382 /* Return the riscv_tune_info entry for the given name string. */
383
384 static const struct riscv_tune_info *
riscv_parse_tune(const char * tune_string)385 riscv_parse_tune (const char *tune_string)
386 {
387 const riscv_cpu_info *cpu = riscv_find_cpu (tune_string);
388
389 if (cpu)
390 tune_string = cpu->tune;
391
392 for (unsigned i = 0; i < ARRAY_SIZE (riscv_tune_info_table); i++)
393 if (strcmp (riscv_tune_info_table[i].name, tune_string) == 0)
394 return riscv_tune_info_table + i;
395
396 error ("unknown cpu %qs for %<-mtune%>", tune_string);
397 return riscv_tune_info_table;
398 }
399
400 /* Helper function for riscv_build_integer; arguments are as for
401 riscv_build_integer. */
402
403 static int
riscv_build_integer_1(struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],HOST_WIDE_INT value,machine_mode mode)404 riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
405 HOST_WIDE_INT value, machine_mode mode)
406 {
407 HOST_WIDE_INT low_part = CONST_LOW_PART (value);
408 int cost = RISCV_MAX_INTEGER_OPS + 1, alt_cost;
409 struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS];
410
411 if (SMALL_OPERAND (value) || LUI_OPERAND (value))
412 {
413 /* Simply ADDI or LUI. */
414 codes[0].code = UNKNOWN;
415 codes[0].value = value;
416 return 1;
417 }
418 if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (value))
419 {
420 /* Simply BSETI. */
421 codes[0].code = UNKNOWN;
422 codes[0].value = value;
423
424 /* RISC-V sign-extends all 32bit values that live in a 32bit
425 register. To avoid paradoxes, we thus need to use the
426 sign-extended (negative) representation (-1 << 31) for the
427 value, if we want to build (1 << 31) in SImode. This will
428 then expand to an LUI instruction. */
429 if (mode == SImode && value == (HOST_WIDE_INT_1U << 31))
430 codes[0].value = (HOST_WIDE_INT_M1U << 31);
431
432 return 1;
433 }
434
435 /* End with ADDI. When constructing HImode constants, do not generate any
436 intermediate value that is not itself a valid HImode constant. The
437 XORI case below will handle those remaining HImode constants. */
438 if (low_part != 0
439 && (mode != HImode
440 || value - low_part <= ((1 << (GET_MODE_BITSIZE (HImode) - 1)) - 1)))
441 {
442 alt_cost = 1 + riscv_build_integer_1 (alt_codes, value - low_part, mode);
443 if (alt_cost < cost)
444 {
445 alt_codes[alt_cost-1].code = PLUS;
446 alt_codes[alt_cost-1].value = low_part;
447 memcpy (codes, alt_codes, sizeof (alt_codes));
448 cost = alt_cost;
449 }
450 }
451
452 /* End with XORI. */
453 if (cost > 2 && (low_part < 0 || mode == HImode))
454 {
455 alt_cost = 1 + riscv_build_integer_1 (alt_codes, value ^ low_part, mode);
456 if (alt_cost < cost)
457 {
458 alt_codes[alt_cost-1].code = XOR;
459 alt_codes[alt_cost-1].value = low_part;
460 memcpy (codes, alt_codes, sizeof (alt_codes));
461 cost = alt_cost;
462 }
463 }
464
465 /* Eliminate trailing zeros and end with SLLI. */
466 if (cost > 2 && (value & 1) == 0)
467 {
468 int shift = ctz_hwi (value);
469 unsigned HOST_WIDE_INT x = value;
470 x = sext_hwi (x >> shift, HOST_BITS_PER_WIDE_INT - shift);
471
472 /* Don't eliminate the lower 12 bits if LUI might apply. */
473 if (shift > IMM_BITS && !SMALL_OPERAND (x) && LUI_OPERAND (x << IMM_BITS))
474 shift -= IMM_BITS, x <<= IMM_BITS;
475
476 alt_cost = 1 + riscv_build_integer_1 (alt_codes, x, mode);
477 if (alt_cost < cost)
478 {
479 alt_codes[alt_cost-1].code = ASHIFT;
480 alt_codes[alt_cost-1].value = shift;
481 memcpy (codes, alt_codes, sizeof (alt_codes));
482 cost = alt_cost;
483 }
484 }
485
486 if (cost > 2 && TARGET_64BIT && TARGET_ZBB)
487 {
488 int leading_ones = clz_hwi (~value);
489 int trailing_ones = ctz_hwi (~value);
490
491 /* If all bits are one except a few that are zero, and the zero bits
492 are within a range of 11 bits, and at least one of the upper 32-bits
493 is a zero, then we can generate a constant by loading a small
494 negative constant and rotating. */
495 if (leading_ones < 32
496 && ((64 - leading_ones - trailing_ones) < 12))
497 {
498 codes[0].code = UNKNOWN;
499 /* The sign-bit might be zero, so just rotate to be safe. */
500 codes[0].value = (((unsigned HOST_WIDE_INT) value >> trailing_ones)
501 | (value << (64 - trailing_ones)));
502 codes[1].code = ROTATERT;
503 codes[1].value = 64 - trailing_ones;
504 cost = 2;
505 }
506 /* Handle the case where the 11 bit range of zero bits wraps around. */
507 else
508 {
509 int upper_trailing_ones = ctz_hwi (~value >> 32);
510 int lower_leading_ones = clz_hwi (~value << 32);
511
512 if (upper_trailing_ones < 32 && lower_leading_ones < 32
513 && ((64 - upper_trailing_ones - lower_leading_ones) < 12))
514 {
515 codes[0].code = UNKNOWN;
516 /* The sign-bit might be zero, so just rotate to be safe. */
517 codes[0].value = ((value << (32 - upper_trailing_ones))
518 | ((unsigned HOST_WIDE_INT) value
519 >> (32 + upper_trailing_ones)));
520 codes[1].code = ROTATERT;
521 codes[1].value = 32 - upper_trailing_ones;
522 cost = 2;
523 }
524 }
525 }
526
527 gcc_assert (cost <= RISCV_MAX_INTEGER_OPS);
528 return cost;
529 }
530
531 /* Fill CODES with a sequence of rtl operations to load VALUE.
532 Return the number of operations needed. */
533
534 static int
riscv_build_integer(struct riscv_integer_op * codes,HOST_WIDE_INT value,machine_mode mode)535 riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value,
536 machine_mode mode)
537 {
538 int cost = riscv_build_integer_1 (codes, value, mode);
539
540 /* Eliminate leading zeros and end with SRLI. */
541 if (value > 0 && cost > 2)
542 {
543 struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS];
544 int alt_cost, shift = clz_hwi (value);
545 HOST_WIDE_INT shifted_val;
546
547 /* Try filling trailing bits with 1s. */
548 shifted_val = (value << shift) | ((((HOST_WIDE_INT) 1) << shift) - 1);
549 alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode);
550 if (alt_cost < cost)
551 {
552 alt_codes[alt_cost-1].code = LSHIFTRT;
553 alt_codes[alt_cost-1].value = shift;
554 memcpy (codes, alt_codes, sizeof (alt_codes));
555 cost = alt_cost;
556 }
557
558 /* Try filling trailing bits with 0s. */
559 shifted_val = value << shift;
560 alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode);
561 if (alt_cost < cost)
562 {
563 alt_codes[alt_cost-1].code = LSHIFTRT;
564 alt_codes[alt_cost-1].value = shift;
565 memcpy (codes, alt_codes, sizeof (alt_codes));
566 cost = alt_cost;
567 }
568 }
569
570 return cost;
571 }
572
573 /* Return the cost of constructing VAL in the event that a scratch
574 register is available. */
575
576 static int
riscv_split_integer_cost(HOST_WIDE_INT val)577 riscv_split_integer_cost (HOST_WIDE_INT val)
578 {
579 int cost;
580 unsigned HOST_WIDE_INT loval = sext_hwi (val, 32);
581 unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32);
582 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS];
583
584 cost = 2 + riscv_build_integer (codes, loval, VOIDmode);
585 if (loval != hival)
586 cost += riscv_build_integer (codes, hival, VOIDmode);
587
588 return cost;
589 }
590
591 /* Return the cost of constructing the integer constant VAL. */
592
593 static int
riscv_integer_cost(HOST_WIDE_INT val)594 riscv_integer_cost (HOST_WIDE_INT val)
595 {
596 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS];
597 return MIN (riscv_build_integer (codes, val, VOIDmode),
598 riscv_split_integer_cost (val));
599 }
600
601 /* Try to split a 64b integer into 32b parts, then reassemble. */
602
603 static rtx
riscv_split_integer(HOST_WIDE_INT val,machine_mode mode)604 riscv_split_integer (HOST_WIDE_INT val, machine_mode mode)
605 {
606 unsigned HOST_WIDE_INT loval = sext_hwi (val, 32);
607 unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32);
608 rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode);
609
610 riscv_move_integer (hi, hi, hival, mode, FALSE);
611 riscv_move_integer (lo, lo, loval, mode, FALSE);
612
613 hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32));
614 hi = force_reg (mode, hi);
615
616 return gen_rtx_fmt_ee (PLUS, mode, hi, lo);
617 }
618
619 /* Return true if X is a thread-local symbol. */
620
621 static bool
riscv_tls_symbol_p(const_rtx x)622 riscv_tls_symbol_p (const_rtx x)
623 {
624 return SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0;
625 }
626
627 /* Return true if symbol X binds locally. */
628
629 static bool
riscv_symbol_binds_local_p(const_rtx x)630 riscv_symbol_binds_local_p (const_rtx x)
631 {
632 if (SYMBOL_REF_P (x))
633 return (SYMBOL_REF_DECL (x)
634 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
635 : SYMBOL_REF_LOCAL_P (x));
636 else
637 return false;
638 }
639
640 /* Return the method that should be used to access SYMBOL_REF or
641 LABEL_REF X. */
642
643 static enum riscv_symbol_type
riscv_classify_symbol(const_rtx x)644 riscv_classify_symbol (const_rtx x)
645 {
646 if (riscv_tls_symbol_p (x))
647 return SYMBOL_TLS;
648
649 if (GET_CODE (x) == SYMBOL_REF && flag_pic && !riscv_symbol_binds_local_p (x))
650 return SYMBOL_GOT_DISP;
651
652 return riscv_cmodel == CM_MEDLOW ? SYMBOL_ABSOLUTE : SYMBOL_PCREL;
653 }
654
655 /* Classify the base of symbolic expression X. */
656
657 enum riscv_symbol_type
riscv_classify_symbolic_expression(rtx x)658 riscv_classify_symbolic_expression (rtx x)
659 {
660 rtx offset;
661
662 split_const (x, &x, &offset);
663 if (UNSPEC_ADDRESS_P (x))
664 return UNSPEC_ADDRESS_TYPE (x);
665
666 return riscv_classify_symbol (x);
667 }
668
669 /* Return true if X is a symbolic constant. If it is, store the type of
670 the symbol in *SYMBOL_TYPE. */
671
672 bool
riscv_symbolic_constant_p(rtx x,enum riscv_symbol_type * symbol_type)673 riscv_symbolic_constant_p (rtx x, enum riscv_symbol_type *symbol_type)
674 {
675 rtx offset;
676
677 split_const (x, &x, &offset);
678 if (UNSPEC_ADDRESS_P (x))
679 {
680 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
681 x = UNSPEC_ADDRESS (x);
682 }
683 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
684 *symbol_type = riscv_classify_symbol (x);
685 else
686 return false;
687
688 if (offset == const0_rtx)
689 return true;
690
691 /* Nonzero offsets are only valid for references that don't use the GOT. */
692 switch (*symbol_type)
693 {
694 case SYMBOL_ABSOLUTE:
695 case SYMBOL_PCREL:
696 case SYMBOL_TLS_LE:
697 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
698 return sext_hwi (INTVAL (offset), 32) == INTVAL (offset);
699
700 default:
701 return false;
702 }
703 }
704
705 /* Returns the number of instructions necessary to reference a symbol. */
706
riscv_symbol_insns(enum riscv_symbol_type type)707 static int riscv_symbol_insns (enum riscv_symbol_type type)
708 {
709 switch (type)
710 {
711 case SYMBOL_TLS: return 0; /* Depends on the TLS model. */
712 case SYMBOL_ABSOLUTE: return 2; /* LUI + the reference. */
713 case SYMBOL_PCREL: return 2; /* AUIPC + the reference. */
714 case SYMBOL_TLS_LE: return 3; /* LUI + ADD TP + the reference. */
715 case SYMBOL_GOT_DISP: return 3; /* AUIPC + LD GOT + the reference. */
716 default: gcc_unreachable ();
717 }
718 }
719
720 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
721
722 static bool
riscv_legitimate_constant_p(machine_mode mode ATTRIBUTE_UNUSED,rtx x)723 riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
724 {
725 return riscv_const_insns (x) > 0;
726 }
727
728 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
729
730 static bool
riscv_cannot_force_const_mem(machine_mode mode ATTRIBUTE_UNUSED,rtx x)731 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
732 {
733 enum riscv_symbol_type type;
734 rtx base, offset;
735
736 /* There is no assembler syntax for expressing an address-sized
737 high part. */
738 if (GET_CODE (x) == HIGH)
739 return true;
740
741 split_const (x, &base, &offset);
742 if (riscv_symbolic_constant_p (base, &type))
743 {
744 /* As an optimization, don't spill symbolic constants that are as
745 cheap to rematerialize as to access in the constant pool. */
746 if (SMALL_OPERAND (INTVAL (offset)) && riscv_symbol_insns (type) > 0)
747 return true;
748
749 /* As an optimization, avoid needlessly generate dynamic relocations. */
750 if (flag_pic)
751 return true;
752 }
753
754 /* TLS symbols must be computed by riscv_legitimize_move. */
755 if (tls_referenced_p (x))
756 return true;
757
758 return false;
759 }
760
761 /* Return true if register REGNO is a valid base register for mode MODE.
762 STRICT_P is true if REG_OK_STRICT is in effect. */
763
764 int
riscv_regno_mode_ok_for_base_p(int regno,machine_mode mode ATTRIBUTE_UNUSED,bool strict_p)765 riscv_regno_mode_ok_for_base_p (int regno,
766 machine_mode mode ATTRIBUTE_UNUSED,
767 bool strict_p)
768 {
769 if (!HARD_REGISTER_NUM_P (regno))
770 {
771 if (!strict_p)
772 return true;
773 regno = reg_renumber[regno];
774 }
775
776 /* These fake registers will be eliminated to either the stack or
777 hard frame pointer, both of which are usually valid base registers.
778 Reload deals with the cases where the eliminated form isn't valid. */
779 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
780 return true;
781
782 return GP_REG_P (regno);
783 }
784
785 /* Return true if X is a valid base register for mode MODE.
786 STRICT_P is true if REG_OK_STRICT is in effect. */
787
788 static bool
riscv_valid_base_register_p(rtx x,machine_mode mode,bool strict_p)789 riscv_valid_base_register_p (rtx x, machine_mode mode, bool strict_p)
790 {
791 if (!strict_p && GET_CODE (x) == SUBREG)
792 x = SUBREG_REG (x);
793
794 return (REG_P (x)
795 && riscv_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
796 }
797
798 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
799 can address a value of mode MODE. */
800
801 static bool
riscv_valid_offset_p(rtx x,machine_mode mode)802 riscv_valid_offset_p (rtx x, machine_mode mode)
803 {
804 /* Check that X is a signed 12-bit number. */
805 if (!const_arith_operand (x, Pmode))
806 return false;
807
808 /* We may need to split multiword moves, so make sure that every word
809 is accessible. */
810 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
811 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
812 return false;
813
814 return true;
815 }
816
817 /* Should a symbol of type SYMBOL_TYPE should be split in two? */
818
819 bool
riscv_split_symbol_type(enum riscv_symbol_type symbol_type)820 riscv_split_symbol_type (enum riscv_symbol_type symbol_type)
821 {
822 if (symbol_type == SYMBOL_TLS_LE)
823 return true;
824
825 if (!TARGET_EXPLICIT_RELOCS)
826 return false;
827
828 return symbol_type == SYMBOL_ABSOLUTE || symbol_type == SYMBOL_PCREL;
829 }
830
831 /* Return true if a LO_SUM can address a value of mode MODE when the
832 LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which
833 is used when the mode is BLKmode. */
834
835 static bool
riscv_valid_lo_sum_p(enum riscv_symbol_type sym_type,machine_mode mode,rtx x)836 riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode,
837 rtx x)
838 {
839 int align, size;
840
841 /* Check that symbols of type SYMBOL_TYPE can be used to access values
842 of mode MODE. */
843 if (riscv_symbol_insns (sym_type) == 0)
844 return false;
845
846 /* Check that there is a known low-part relocation. */
847 if (!riscv_split_symbol_type (sym_type))
848 return false;
849
850 /* We can't tell size or alignment when we have BLKmode, so try extracing a
851 decl from the symbol if possible. */
852 if (mode == BLKmode)
853 {
854 rtx offset;
855
856 /* Extract the symbol from the LO_SUM operand, if any. */
857 split_const (x, &x, &offset);
858
859 /* Might be a CODE_LABEL. We can compute align but not size for that,
860 so don't bother trying to handle it. */
861 if (!SYMBOL_REF_P (x))
862 return false;
863
864 /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */
865 align = (SYMBOL_REF_DECL (x)
866 ? DECL_ALIGN (SYMBOL_REF_DECL (x))
867 : 1);
868 size = (SYMBOL_REF_DECL (x) && DECL_SIZE (SYMBOL_REF_DECL (x))
869 ? tree_to_uhwi (DECL_SIZE (SYMBOL_REF_DECL (x)))
870 : 2*BITS_PER_WORD);
871 }
872 else
873 {
874 align = GET_MODE_ALIGNMENT (mode);
875 size = GET_MODE_BITSIZE (mode);
876 }
877
878 /* We may need to split multiword moves, so make sure that each word
879 can be accessed without inducing a carry. */
880 if (size > BITS_PER_WORD
881 && (!TARGET_STRICT_ALIGN || size > align))
882 return false;
883
884 return true;
885 }
886
887 /* Return true if X is a valid address for machine mode MODE. If it is,
888 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
889 effect. */
890
891 static bool
riscv_classify_address(struct riscv_address_info * info,rtx x,machine_mode mode,bool strict_p)892 riscv_classify_address (struct riscv_address_info *info, rtx x,
893 machine_mode mode, bool strict_p)
894 {
895 switch (GET_CODE (x))
896 {
897 case REG:
898 case SUBREG:
899 info->type = ADDRESS_REG;
900 info->reg = x;
901 info->offset = const0_rtx;
902 return riscv_valid_base_register_p (info->reg, mode, strict_p);
903
904 case PLUS:
905 info->type = ADDRESS_REG;
906 info->reg = XEXP (x, 0);
907 info->offset = XEXP (x, 1);
908 return (riscv_valid_base_register_p (info->reg, mode, strict_p)
909 && riscv_valid_offset_p (info->offset, mode));
910
911 case LO_SUM:
912 info->type = ADDRESS_LO_SUM;
913 info->reg = XEXP (x, 0);
914 info->offset = XEXP (x, 1);
915 /* We have to trust the creator of the LO_SUM to do something vaguely
916 sane. Target-independent code that creates a LO_SUM should also
917 create and verify the matching HIGH. Target-independent code that
918 adds an offset to a LO_SUM must prove that the offset will not
919 induce a carry. Failure to do either of these things would be
920 a bug, and we are not required to check for it here. The RISC-V
921 backend itself should only create LO_SUMs for valid symbolic
922 constants, with the high part being either a HIGH or a copy
923 of _gp. */
924 info->symbol_type
925 = riscv_classify_symbolic_expression (info->offset);
926 return (riscv_valid_base_register_p (info->reg, mode, strict_p)
927 && riscv_valid_lo_sum_p (info->symbol_type, mode, info->offset));
928
929 case CONST_INT:
930 /* Small-integer addresses don't occur very often, but they
931 are legitimate if x0 is a valid base register. */
932 info->type = ADDRESS_CONST_INT;
933 return SMALL_OPERAND (INTVAL (x));
934
935 default:
936 return false;
937 }
938 }
939
940 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
941
942 static bool
riscv_legitimate_address_p(machine_mode mode,rtx x,bool strict_p)943 riscv_legitimate_address_p (machine_mode mode, rtx x, bool strict_p)
944 {
945 struct riscv_address_info addr;
946
947 return riscv_classify_address (&addr, x, mode, strict_p);
948 }
949
950 /* Return true if hard reg REGNO can be used in compressed instructions. */
951
952 static bool
riscv_compressed_reg_p(int regno)953 riscv_compressed_reg_p (int regno)
954 {
955 /* x8-x15/f8-f15 are compressible registers. */
956 return (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
957 || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)));
958 }
959
960 /* Return true if x is an unsigned 5-bit immediate scaled by 4. */
961
962 static bool
riscv_compressed_lw_offset_p(rtx x)963 riscv_compressed_lw_offset_p (rtx x)
964 {
965 return (CONST_INT_P (x)
966 && (INTVAL (x) & 3) == 0
967 && IN_RANGE (INTVAL (x), 0, CSW_MAX_OFFSET));
968 }
969
970 /* Return true if load/store from/to address x can be compressed. */
971
972 static bool
riscv_compressed_lw_address_p(rtx x)973 riscv_compressed_lw_address_p (rtx x)
974 {
975 struct riscv_address_info addr;
976 bool result = riscv_classify_address (&addr, x, GET_MODE (x),
977 reload_completed);
978
979 /* Return false if address is not compressed_reg + small_offset. */
980 if (!result
981 || addr.type != ADDRESS_REG
982 /* Before reload, assume all registers are OK. */
983 || (reload_completed
984 && !riscv_compressed_reg_p (REGNO (addr.reg))
985 && addr.reg != stack_pointer_rtx)
986 || !riscv_compressed_lw_offset_p (addr.offset))
987 return false;
988
989 return result;
990 }
991
992 /* Return the number of instructions needed to load or store a value
993 of mode MODE at address X. Return 0 if X isn't valid for MODE.
994 Assume that multiword moves may need to be split into word moves
995 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
996 enough. */
997
998 int
riscv_address_insns(rtx x,machine_mode mode,bool might_split_p)999 riscv_address_insns (rtx x, machine_mode mode, bool might_split_p)
1000 {
1001 struct riscv_address_info addr = {};
1002 int n = 1;
1003
1004 if (!riscv_classify_address (&addr, x, mode, false))
1005 {
1006 /* This could be a pattern from the pic.md file. In which case we want
1007 this address to always have a cost of 3 to make it as expensive as the
1008 most expensive symbol. This prevents constant propagation from
1009 preferring symbols over register plus offset. */
1010 return 3;
1011 }
1012
1013 /* BLKmode is used for single unaligned loads and stores and should
1014 not count as a multiword mode. */
1015 if (mode != BLKmode && might_split_p)
1016 n += (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1017
1018 if (addr.type == ADDRESS_LO_SUM)
1019 n += riscv_symbol_insns (addr.symbol_type) - 1;
1020
1021 return n;
1022 }
1023
1024 /* Return the number of instructions needed to load constant X.
1025 Return 0 if X isn't a valid constant. */
1026
1027 int
riscv_const_insns(rtx x)1028 riscv_const_insns (rtx x)
1029 {
1030 enum riscv_symbol_type symbol_type;
1031 rtx offset;
1032
1033 switch (GET_CODE (x))
1034 {
1035 case HIGH:
1036 if (!riscv_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1037 || !riscv_split_symbol_type (symbol_type))
1038 return 0;
1039
1040 /* This is simply an LUI. */
1041 return 1;
1042
1043 case CONST_INT:
1044 {
1045 int cost = riscv_integer_cost (INTVAL (x));
1046 /* Force complicated constants to memory. */
1047 return cost < 4 ? cost : 0;
1048 }
1049
1050 case CONST_DOUBLE:
1051 case CONST_VECTOR:
1052 /* We can use x0 to load floating-point zero. */
1053 return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
1054
1055 case CONST:
1056 /* See if we can refer to X directly. */
1057 if (riscv_symbolic_constant_p (x, &symbol_type))
1058 return riscv_symbol_insns (symbol_type);
1059
1060 /* Otherwise try splitting the constant into a base and offset. */
1061 split_const (x, &x, &offset);
1062 if (offset != 0)
1063 {
1064 int n = riscv_const_insns (x);
1065 if (n != 0)
1066 return n + riscv_integer_cost (INTVAL (offset));
1067 }
1068 return 0;
1069
1070 case SYMBOL_REF:
1071 case LABEL_REF:
1072 return riscv_symbol_insns (riscv_classify_symbol (x));
1073
1074 default:
1075 return 0;
1076 }
1077 }
1078
1079 /* X is a doubleword constant that can be handled by splitting it into
1080 two words and loading each word separately. Return the number of
1081 instructions required to do this. */
1082
1083 int
riscv_split_const_insns(rtx x)1084 riscv_split_const_insns (rtx x)
1085 {
1086 unsigned int low, high;
1087
1088 low = riscv_const_insns (riscv_subword (x, false));
1089 high = riscv_const_insns (riscv_subword (x, true));
1090 gcc_assert (low > 0 && high > 0);
1091 return low + high;
1092 }
1093
1094 /* Return the number of instructions needed to implement INSN,
1095 given that it loads from or stores to MEM. */
1096
1097 int
riscv_load_store_insns(rtx mem,rtx_insn * insn)1098 riscv_load_store_insns (rtx mem, rtx_insn *insn)
1099 {
1100 machine_mode mode;
1101 bool might_split_p;
1102 rtx set;
1103
1104 gcc_assert (MEM_P (mem));
1105 mode = GET_MODE (mem);
1106
1107 /* Try to prove that INSN does not need to be split. */
1108 might_split_p = true;
1109 if (GET_MODE_BITSIZE (mode) <= 32)
1110 might_split_p = false;
1111 else if (GET_MODE_BITSIZE (mode) == 64)
1112 {
1113 set = single_set (insn);
1114 if (set && !riscv_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
1115 might_split_p = false;
1116 }
1117
1118 return riscv_address_insns (XEXP (mem, 0), mode, might_split_p);
1119 }
1120
1121 /* Emit a move from SRC to DEST. Assume that the move expanders can
1122 handle all moves if !can_create_pseudo_p (). The distinction is
1123 important because, unlike emit_move_insn, the move expanders know
1124 how to force Pmode objects into the constant pool even when the
1125 constant pool address is not itself legitimate. */
1126
1127 rtx
riscv_emit_move(rtx dest,rtx src)1128 riscv_emit_move (rtx dest, rtx src)
1129 {
1130 return (can_create_pseudo_p ()
1131 ? emit_move_insn (dest, src)
1132 : emit_move_insn_1 (dest, src));
1133 }
1134
1135 /* Emit an instruction of the form (set TARGET SRC). */
1136
1137 static rtx
riscv_emit_set(rtx target,rtx src)1138 riscv_emit_set (rtx target, rtx src)
1139 {
1140 emit_insn (gen_rtx_SET (target, src));
1141 return target;
1142 }
1143
1144 /* Emit an instruction of the form (set DEST (CODE X Y)). */
1145
1146 static rtx
riscv_emit_binary(enum rtx_code code,rtx dest,rtx x,rtx y)1147 riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y)
1148 {
1149 return riscv_emit_set (dest, gen_rtx_fmt_ee (code, GET_MODE (dest), x, y));
1150 }
1151
1152 /* Compute (CODE X Y) and store the result in a new register
1153 of mode MODE. Return that new register. */
1154
1155 static rtx
riscv_force_binary(machine_mode mode,enum rtx_code code,rtx x,rtx y)1156 riscv_force_binary (machine_mode mode, enum rtx_code code, rtx x, rtx y)
1157 {
1158 return riscv_emit_binary (code, gen_reg_rtx (mode), x, y);
1159 }
1160
1161 static rtx
riscv_swap_instruction(rtx inst)1162 riscv_swap_instruction (rtx inst)
1163 {
1164 gcc_assert (GET_MODE (inst) == SImode);
1165 if (BYTES_BIG_ENDIAN)
1166 inst = expand_unop (SImode, bswap_optab, inst, gen_reg_rtx (SImode), 1);
1167 return inst;
1168 }
1169
1170 /* Copy VALUE to a register and return that register. If new pseudos
1171 are allowed, copy it into a new register, otherwise use DEST. */
1172
1173 static rtx
riscv_force_temporary(rtx dest,rtx value,bool in_splitter)1174 riscv_force_temporary (rtx dest, rtx value, bool in_splitter)
1175 {
1176 /* We can't call gen_reg_rtx from a splitter, because this might realloc
1177 the regno_reg_rtx array, which would invalidate reg rtx pointers in the
1178 combine undo buffer. */
1179 if (can_create_pseudo_p () && !in_splitter)
1180 return force_reg (Pmode, value);
1181 else
1182 {
1183 riscv_emit_move (dest, value);
1184 return dest;
1185 }
1186 }
1187
1188 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
1189 then add CONST_INT OFFSET to the result. */
1190
1191 static rtx
riscv_unspec_address_offset(rtx base,rtx offset,enum riscv_symbol_type symbol_type)1192 riscv_unspec_address_offset (rtx base, rtx offset,
1193 enum riscv_symbol_type symbol_type)
1194 {
1195 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1196 UNSPEC_ADDRESS_FIRST + symbol_type);
1197 if (offset != const0_rtx)
1198 base = gen_rtx_PLUS (Pmode, base, offset);
1199 return gen_rtx_CONST (Pmode, base);
1200 }
1201
1202 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1203 type SYMBOL_TYPE. */
1204
1205 rtx
riscv_unspec_address(rtx address,enum riscv_symbol_type symbol_type)1206 riscv_unspec_address (rtx address, enum riscv_symbol_type symbol_type)
1207 {
1208 rtx base, offset;
1209
1210 split_const (address, &base, &offset);
1211 return riscv_unspec_address_offset (base, offset, symbol_type);
1212 }
1213
1214 /* If OP is an UNSPEC address, return the address to which it refers,
1215 otherwise return OP itself. */
1216
1217 static rtx
riscv_strip_unspec_address(rtx op)1218 riscv_strip_unspec_address (rtx op)
1219 {
1220 rtx base, offset;
1221
1222 split_const (op, &base, &offset);
1223 if (UNSPEC_ADDRESS_P (base))
1224 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
1225 return op;
1226 }
1227
1228 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1229 high part to BASE and return the result. Just return BASE otherwise.
1230 TEMP is as for riscv_force_temporary.
1231
1232 The returned expression can be used as the first operand to a LO_SUM. */
1233
1234 static rtx
riscv_unspec_offset_high(rtx temp,rtx addr,enum riscv_symbol_type symbol_type)1235 riscv_unspec_offset_high (rtx temp, rtx addr, enum riscv_symbol_type symbol_type)
1236 {
1237 addr = gen_rtx_HIGH (Pmode, riscv_unspec_address (addr, symbol_type));
1238 return riscv_force_temporary (temp, addr, FALSE);
1239 }
1240
1241 /* Load an entry from the GOT for a TLS GD access. */
1242
riscv_got_load_tls_gd(rtx dest,rtx sym)1243 static rtx riscv_got_load_tls_gd (rtx dest, rtx sym)
1244 {
1245 if (Pmode == DImode)
1246 return gen_got_load_tls_gddi (dest, sym);
1247 else
1248 return gen_got_load_tls_gdsi (dest, sym);
1249 }
1250
1251 /* Load an entry from the GOT for a TLS IE access. */
1252
riscv_got_load_tls_ie(rtx dest,rtx sym)1253 static rtx riscv_got_load_tls_ie (rtx dest, rtx sym)
1254 {
1255 if (Pmode == DImode)
1256 return gen_got_load_tls_iedi (dest, sym);
1257 else
1258 return gen_got_load_tls_iesi (dest, sym);
1259 }
1260
1261 /* Add in the thread pointer for a TLS LE access. */
1262
riscv_tls_add_tp_le(rtx dest,rtx base,rtx sym)1263 static rtx riscv_tls_add_tp_le (rtx dest, rtx base, rtx sym)
1264 {
1265 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
1266 if (Pmode == DImode)
1267 return gen_tls_add_tp_ledi (dest, base, tp, sym);
1268 else
1269 return gen_tls_add_tp_lesi (dest, base, tp, sym);
1270 }
1271
1272 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
1273 it appears in a MEM of that mode. Return true if ADDR is a legitimate
1274 constant in that context and can be split into high and low parts.
1275 If so, and if LOW_OUT is nonnull, emit the high part and store the
1276 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
1277
1278 TEMP is as for riscv_force_temporary and is used to load the high
1279 part into a register.
1280
1281 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
1282 a legitimize SET_SRC for an .md pattern, otherwise the low part
1283 is guaranteed to be a legitimate address for mode MODE. */
1284
1285 bool
riscv_split_symbol(rtx temp,rtx addr,machine_mode mode,rtx * low_out,bool in_splitter)1286 riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out,
1287 bool in_splitter)
1288 {
1289 enum riscv_symbol_type symbol_type;
1290
1291 if ((GET_CODE (addr) == HIGH && mode == MAX_MACHINE_MODE)
1292 || !riscv_symbolic_constant_p (addr, &symbol_type)
1293 || riscv_symbol_insns (symbol_type) == 0
1294 || !riscv_split_symbol_type (symbol_type))
1295 return false;
1296
1297 if (low_out)
1298 switch (symbol_type)
1299 {
1300 case SYMBOL_ABSOLUTE:
1301 {
1302 rtx high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
1303 high = riscv_force_temporary (temp, high, in_splitter);
1304 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
1305 }
1306 break;
1307
1308 case SYMBOL_PCREL:
1309 {
1310 static unsigned seqno;
1311 char buf[32];
1312 rtx label;
1313
1314 ssize_t bytes = snprintf (buf, sizeof (buf), ".LA%u", seqno);
1315 gcc_assert ((size_t) bytes < sizeof (buf));
1316
1317 label = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
1318 SYMBOL_REF_FLAGS (label) |= SYMBOL_FLAG_LOCAL;
1319 /* ??? Ugly hack to make weak symbols work. May need to change the
1320 RTL for the auipc and/or low patterns to get a better fix for
1321 this. */
1322 if (! nonzero_address_p (addr))
1323 SYMBOL_REF_WEAK (label) = 1;
1324
1325 if (temp == NULL)
1326 temp = gen_reg_rtx (Pmode);
1327
1328 if (Pmode == DImode)
1329 emit_insn (gen_auipcdi (temp, copy_rtx (addr), GEN_INT (seqno)));
1330 else
1331 emit_insn (gen_auipcsi (temp, copy_rtx (addr), GEN_INT (seqno)));
1332
1333 *low_out = gen_rtx_LO_SUM (Pmode, temp, label);
1334
1335 seqno++;
1336 }
1337 break;
1338
1339 default:
1340 gcc_unreachable ();
1341 }
1342
1343 return true;
1344 }
1345
1346 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1347 riscv_force_temporary; it is only needed when OFFSET is not a
1348 SMALL_OPERAND. */
1349
1350 static rtx
riscv_add_offset(rtx temp,rtx reg,HOST_WIDE_INT offset)1351 riscv_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1352 {
1353 if (!SMALL_OPERAND (offset))
1354 {
1355 rtx high;
1356
1357 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
1358 The addition inside the macro CONST_HIGH_PART may cause an
1359 overflow, so we need to force a sign-extension check. */
1360 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
1361 offset = CONST_LOW_PART (offset);
1362 high = riscv_force_temporary (temp, high, FALSE);
1363 reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg),
1364 FALSE);
1365 }
1366 return plus_constant (Pmode, reg, offset);
1367 }
1368
1369 /* The __tls_get_attr symbol. */
1370 static GTY(()) rtx riscv_tls_symbol;
1371
1372 /* Return an instruction sequence that calls __tls_get_addr. SYM is
1373 the TLS symbol we are referencing and TYPE is the symbol type to use
1374 (either global dynamic or local dynamic). RESULT is an RTX for the
1375 return value location. */
1376
1377 static rtx_insn *
riscv_call_tls_get_addr(rtx sym,rtx result)1378 riscv_call_tls_get_addr (rtx sym, rtx result)
1379 {
1380 rtx a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST), func;
1381 rtx_insn *insn;
1382
1383 if (!riscv_tls_symbol)
1384 riscv_tls_symbol = init_one_libfunc ("__tls_get_addr");
1385 func = gen_rtx_MEM (FUNCTION_MODE, riscv_tls_symbol);
1386
1387 start_sequence ();
1388
1389 emit_insn (riscv_got_load_tls_gd (a0, sym));
1390 insn = emit_call_insn (gen_call_value (result, func, const0_rtx, NULL));
1391 RTL_CONST_CALL_P (insn) = 1;
1392 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
1393 insn = get_insns ();
1394
1395 end_sequence ();
1396
1397 return insn;
1398 }
1399
1400 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
1401 its address. The return value will be both a valid address and a valid
1402 SET_SRC (either a REG or a LO_SUM). */
1403
1404 static rtx
riscv_legitimize_tls_address(rtx loc)1405 riscv_legitimize_tls_address (rtx loc)
1406 {
1407 rtx dest, tp, tmp;
1408 enum tls_model model = SYMBOL_REF_TLS_MODEL (loc);
1409
1410 #if 0
1411 /* TLS copy relocs are now deprecated and should not be used. */
1412 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
1413 if (!flag_pic)
1414 model = TLS_MODEL_LOCAL_EXEC;
1415 #endif
1416
1417 switch (model)
1418 {
1419 case TLS_MODEL_LOCAL_DYNAMIC:
1420 /* Rely on section anchors for the optimization that LDM TLS
1421 provides. The anchor's address is loaded with GD TLS. */
1422 case TLS_MODEL_GLOBAL_DYNAMIC:
1423 tmp = gen_rtx_REG (Pmode, GP_RETURN);
1424 dest = gen_reg_rtx (Pmode);
1425 emit_libcall_block (riscv_call_tls_get_addr (loc, tmp), dest, tmp, loc);
1426 break;
1427
1428 case TLS_MODEL_INITIAL_EXEC:
1429 /* la.tls.ie; tp-relative add */
1430 tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
1431 tmp = gen_reg_rtx (Pmode);
1432 emit_insn (riscv_got_load_tls_ie (tmp, loc));
1433 dest = gen_reg_rtx (Pmode);
1434 emit_insn (gen_add3_insn (dest, tmp, tp));
1435 break;
1436
1437 case TLS_MODEL_LOCAL_EXEC:
1438 tmp = riscv_unspec_offset_high (NULL, loc, SYMBOL_TLS_LE);
1439 dest = gen_reg_rtx (Pmode);
1440 emit_insn (riscv_tls_add_tp_le (dest, tmp, loc));
1441 dest = gen_rtx_LO_SUM (Pmode, dest,
1442 riscv_unspec_address (loc, SYMBOL_TLS_LE));
1443 break;
1444
1445 default:
1446 gcc_unreachable ();
1447 }
1448 return dest;
1449 }
1450
1451 /* If X is not a valid address for mode MODE, force it into a register. */
1452
1453 static rtx
riscv_force_address(rtx x,machine_mode mode)1454 riscv_force_address (rtx x, machine_mode mode)
1455 {
1456 if (!riscv_legitimate_address_p (mode, x, false))
1457 x = force_reg (Pmode, x);
1458 return x;
1459 }
1460
1461 /* Modify base + offset so that offset fits within a compressed load/store insn
1462 and the excess is added to base. */
1463
1464 static rtx
riscv_shorten_lw_offset(rtx base,HOST_WIDE_INT offset)1465 riscv_shorten_lw_offset (rtx base, HOST_WIDE_INT offset)
1466 {
1467 rtx addr, high;
1468 /* Leave OFFSET as an unsigned 5-bit offset scaled by 4 and put the excess
1469 into HIGH. */
1470 high = GEN_INT (offset & ~CSW_MAX_OFFSET);
1471 offset &= CSW_MAX_OFFSET;
1472 if (!SMALL_OPERAND (INTVAL (high)))
1473 high = force_reg (Pmode, high);
1474 base = force_reg (Pmode, gen_rtx_PLUS (Pmode, high, base));
1475 addr = plus_constant (Pmode, base, offset);
1476 return addr;
1477 }
1478
1479 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
1480 be legitimized in a way that the generic machinery might not expect,
1481 return a new address, otherwise return NULL. MODE is the mode of
1482 the memory being accessed. */
1483
1484 static rtx
riscv_legitimize_address(rtx x,rtx oldx ATTRIBUTE_UNUSED,machine_mode mode)1485 riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1486 machine_mode mode)
1487 {
1488 rtx addr;
1489
1490 if (riscv_tls_symbol_p (x))
1491 return riscv_legitimize_tls_address (x);
1492
1493 /* See if the address can split into a high part and a LO_SUM. */
1494 if (riscv_split_symbol (NULL, x, mode, &addr, FALSE))
1495 return riscv_force_address (addr, mode);
1496
1497 /* Handle BASE + OFFSET. */
1498 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))
1499 && INTVAL (XEXP (x, 1)) != 0)
1500 {
1501 rtx base = XEXP (x, 0);
1502 HOST_WIDE_INT offset = INTVAL (XEXP (x, 1));
1503
1504 if (!riscv_valid_base_register_p (base, mode, false))
1505 base = copy_to_mode_reg (Pmode, base);
1506 if (optimize_function_for_size_p (cfun)
1507 && (strcmp (current_pass->name, "shorten_memrefs") == 0)
1508 && mode == SImode)
1509 /* Convert BASE + LARGE_OFFSET into NEW_BASE + SMALL_OFFSET to allow
1510 possible compressed load/store. */
1511 addr = riscv_shorten_lw_offset (base, offset);
1512 else
1513 addr = riscv_add_offset (NULL, base, offset);
1514 return riscv_force_address (addr, mode);
1515 }
1516
1517 return x;
1518 }
1519
1520 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. ORIG_MODE
1521 is the original src mode before promotion. */
1522
1523 void
riscv_move_integer(rtx temp,rtx dest,HOST_WIDE_INT value,machine_mode orig_mode,bool in_splitter)1524 riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value,
1525 machine_mode orig_mode, bool in_splitter)
1526 {
1527 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS];
1528 machine_mode mode;
1529 int i, num_ops;
1530 rtx x;
1531
1532 /* We can't call gen_reg_rtx from a splitter, because this might realloc
1533 the regno_reg_rtx array, which would invalidate reg rtx pointers in the
1534 combine undo buffer. */
1535 bool can_create_pseudo = can_create_pseudo_p () && ! in_splitter;
1536
1537 mode = GET_MODE (dest);
1538 /* We use the original mode for the riscv_build_integer call, because HImode
1539 values are given special treatment. */
1540 num_ops = riscv_build_integer (codes, value, orig_mode);
1541
1542 if (can_create_pseudo && num_ops > 2 /* not a simple constant */
1543 && num_ops >= riscv_split_integer_cost (value))
1544 x = riscv_split_integer (value, mode);
1545 else
1546 {
1547 /* Apply each binary operation to X. */
1548 x = GEN_INT (codes[0].value);
1549
1550 for (i = 1; i < num_ops; i++)
1551 {
1552 if (!can_create_pseudo)
1553 x = riscv_emit_set (temp, x);
1554 else
1555 x = force_reg (mode, x);
1556
1557 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
1558 }
1559 }
1560
1561 riscv_emit_set (dest, x);
1562 }
1563
1564 /* Subroutine of riscv_legitimize_move. Move constant SRC into register
1565 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1566 move_operand. */
1567
1568 static void
riscv_legitimize_const_move(machine_mode mode,rtx dest,rtx src)1569 riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
1570 {
1571 rtx base, offset;
1572
1573 /* Split moves of big integers into smaller pieces. */
1574 if (splittable_const_int_operand (src, mode))
1575 {
1576 riscv_move_integer (dest, dest, INTVAL (src), mode, FALSE);
1577 return;
1578 }
1579
1580 /* Split moves of symbolic constants into high/low pairs. */
1581 if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src, FALSE))
1582 {
1583 riscv_emit_set (dest, src);
1584 return;
1585 }
1586
1587 /* Generate the appropriate access sequences for TLS symbols. */
1588 if (riscv_tls_symbol_p (src))
1589 {
1590 riscv_emit_move (dest, riscv_legitimize_tls_address (src));
1591 return;
1592 }
1593
1594 /* If we have (const (plus symbol offset)), and that expression cannot
1595 be forced into memory, load the symbol first and add in the offset. Also
1596 prefer to do this even if the constant _can_ be forced into memory, as it
1597 usually produces better code. */
1598 split_const (src, &base, &offset);
1599 if (offset != const0_rtx
1600 && (targetm.cannot_force_const_mem (mode, src) || can_create_pseudo_p ()))
1601 {
1602 base = riscv_force_temporary (dest, base, FALSE);
1603 riscv_emit_move (dest, riscv_add_offset (NULL, base, INTVAL (offset)));
1604 return;
1605 }
1606
1607 src = force_const_mem (mode, src);
1608
1609 /* When using explicit relocs, constant pool references are sometimes
1610 not legitimate addresses. */
1611 riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0), FALSE);
1612 riscv_emit_move (dest, src);
1613 }
1614
1615 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
1616 sequence that is valid. */
1617
1618 bool
riscv_legitimize_move(machine_mode mode,rtx dest,rtx src)1619 riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
1620 {
1621 /* Expand
1622 (set (reg:QI target) (mem:QI (address)))
1623 to
1624 (set (reg:DI temp) (zero_extend:DI (mem:QI (address))))
1625 (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
1626 with auto-sign/zero extend. */
1627 if (GET_MODE_CLASS (mode) == MODE_INT
1628 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
1629 && can_create_pseudo_p ()
1630 && MEM_P (src))
1631 {
1632 rtx temp_reg;
1633 int zero_extend_p;
1634
1635 temp_reg = gen_reg_rtx (word_mode);
1636 zero_extend_p = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
1637 emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode,
1638 zero_extend_p));
1639 riscv_emit_move (dest, gen_lowpart (mode, temp_reg));
1640 return true;
1641 }
1642
1643 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1644 {
1645 rtx reg;
1646
1647 if (GET_CODE (src) == CONST_INT)
1648 {
1649 /* Apply the equivalent of PROMOTE_MODE here for constants to
1650 improve cse. */
1651 machine_mode promoted_mode = mode;
1652 if (GET_MODE_CLASS (mode) == MODE_INT
1653 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
1654 promoted_mode = word_mode;
1655
1656 if (splittable_const_int_operand (src, mode))
1657 {
1658 reg = gen_reg_rtx (promoted_mode);
1659 riscv_move_integer (reg, reg, INTVAL (src), mode, FALSE);
1660 }
1661 else
1662 reg = force_reg (promoted_mode, src);
1663
1664 if (promoted_mode != mode)
1665 reg = gen_lowpart (mode, reg);
1666 }
1667 else
1668 reg = force_reg (mode, src);
1669 riscv_emit_move (dest, reg);
1670 return true;
1671 }
1672
1673 /* We need to deal with constants that would be legitimate
1674 immediate_operands but aren't legitimate move_operands. */
1675 if (CONSTANT_P (src) && !move_operand (src, mode))
1676 {
1677 riscv_legitimize_const_move (mode, dest, src);
1678 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
1679 return true;
1680 }
1681
1682 /* RISC-V GCC may generate non-legitimate address due to we provide some
1683 pattern for optimize access PIC local symbol and it's make GCC generate
1684 unrecognizable instruction during optmizing. */
1685
1686 if (MEM_P (dest) && !riscv_legitimate_address_p (mode, XEXP (dest, 0),
1687 reload_completed))
1688 {
1689 XEXP (dest, 0) = riscv_force_address (XEXP (dest, 0), mode);
1690 }
1691
1692 if (MEM_P (src) && !riscv_legitimate_address_p (mode, XEXP (src, 0),
1693 reload_completed))
1694 {
1695 XEXP (src, 0) = riscv_force_address (XEXP (src, 0), mode);
1696 }
1697
1698 return false;
1699 }
1700
1701 /* Return true if there is an instruction that implements CODE and accepts
1702 X as an immediate operand. */
1703
1704 static int
riscv_immediate_operand_p(int code,HOST_WIDE_INT x)1705 riscv_immediate_operand_p (int code, HOST_WIDE_INT x)
1706 {
1707 switch (code)
1708 {
1709 case ASHIFT:
1710 case ASHIFTRT:
1711 case LSHIFTRT:
1712 /* All shift counts are truncated to a valid constant. */
1713 return true;
1714
1715 case AND:
1716 case IOR:
1717 case XOR:
1718 case PLUS:
1719 case LT:
1720 case LTU:
1721 /* These instructions take 12-bit signed immediates. */
1722 return SMALL_OPERAND (x);
1723
1724 case LE:
1725 /* We add 1 to the immediate and use SLT. */
1726 return SMALL_OPERAND (x + 1);
1727
1728 case LEU:
1729 /* Likewise SLTU, but reject the always-true case. */
1730 return SMALL_OPERAND (x + 1) && x + 1 != 0;
1731
1732 case GE:
1733 case GEU:
1734 /* We can emulate an immediate of 1 by using GT/GTU against x0. */
1735 return x == 1;
1736
1737 default:
1738 /* By default assume that x0 can be used for 0. */
1739 return x == 0;
1740 }
1741 }
1742
1743 /* Return the cost of binary operation X, given that the instruction
1744 sequence for a word-sized or smaller operation takes SIGNLE_INSNS
1745 instructions and that the sequence of a double-word operation takes
1746 DOUBLE_INSNS instructions. */
1747
1748 static int
riscv_binary_cost(rtx x,int single_insns,int double_insns)1749 riscv_binary_cost (rtx x, int single_insns, int double_insns)
1750 {
1751 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
1752 return COSTS_N_INSNS (double_insns);
1753 return COSTS_N_INSNS (single_insns);
1754 }
1755
1756 /* Return the cost of sign- or zero-extending OP. */
1757
1758 static int
riscv_extend_cost(rtx op,bool unsigned_p)1759 riscv_extend_cost (rtx op, bool unsigned_p)
1760 {
1761 if (MEM_P (op))
1762 return 0;
1763
1764 if (unsigned_p && GET_MODE (op) == QImode)
1765 /* We can use ANDI. */
1766 return COSTS_N_INSNS (1);
1767
1768 /* ZBA provide zext.w. */
1769 if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode)
1770 return COSTS_N_INSNS (1);
1771
1772 /* ZBB provide zext.h, sext.b and sext.h. */
1773 if (TARGET_ZBB)
1774 {
1775 if (!unsigned_p && GET_MODE (op) == QImode)
1776 return COSTS_N_INSNS (1);
1777
1778 if (GET_MODE (op) == HImode)
1779 return COSTS_N_INSNS (1);
1780 }
1781
1782 if (!unsigned_p && GET_MODE (op) == SImode)
1783 /* We can use SEXT.W. */
1784 return COSTS_N_INSNS (1);
1785
1786 /* We need to use a shift left and a shift right. */
1787 return COSTS_N_INSNS (2);
1788 }
1789
1790 /* Implement TARGET_RTX_COSTS. */
1791
1792 #define SINGLE_SHIFT_COST 1
1793
1794 static bool
riscv_rtx_costs(rtx x,machine_mode mode,int outer_code,int opno ATTRIBUTE_UNUSED,int * total,bool speed)1795 riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UNUSED,
1796 int *total, bool speed)
1797 {
1798 bool float_mode_p = FLOAT_MODE_P (mode);
1799 int cost;
1800
1801 switch (GET_CODE (x))
1802 {
1803 case CONST_INT:
1804 if (riscv_immediate_operand_p (outer_code, INTVAL (x)))
1805 {
1806 *total = 0;
1807 return true;
1808 }
1809 /* Fall through. */
1810
1811 case SYMBOL_REF:
1812 case LABEL_REF:
1813 case CONST_DOUBLE:
1814 case CONST:
1815 if ((cost = riscv_const_insns (x)) > 0)
1816 {
1817 /* If the constant is likely to be stored in a GPR, SETs of
1818 single-insn constants are as cheap as register sets; we
1819 never want to CSE them. */
1820 if (cost == 1 && outer_code == SET)
1821 *total = 0;
1822 /* When we load a constant more than once, it usually is better
1823 to duplicate the last operation in the sequence than to CSE
1824 the constant itself. */
1825 else if (outer_code == SET || GET_MODE (x) == VOIDmode)
1826 *total = COSTS_N_INSNS (1);
1827 }
1828 else /* The instruction will be fetched from the constant pool. */
1829 *total = COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE));
1830 return true;
1831
1832 case MEM:
1833 /* If the address is legitimate, return the number of
1834 instructions it needs. */
1835 if ((cost = riscv_address_insns (XEXP (x, 0), mode, true)) > 0)
1836 {
1837 /* When optimizing for size, make uncompressible 32-bit addresses
1838 more expensive so that compressible 32-bit addresses are
1839 preferred. */
1840 if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
1841 && !riscv_compressed_lw_address_p (XEXP (x, 0)))
1842 cost++;
1843
1844 *total = COSTS_N_INSNS (cost + tune_param->memory_cost);
1845 return true;
1846 }
1847 /* Otherwise use the default handling. */
1848 return false;
1849
1850 case NOT:
1851 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
1852 return false;
1853
1854 case AND:
1855 /* slli.uw pattern for zba. */
1856 if (TARGET_ZBA && TARGET_64BIT && mode == DImode
1857 && GET_CODE (XEXP (x, 0)) == ASHIFT)
1858 {
1859 rtx and_rhs = XEXP (x, 1);
1860 rtx ashift_lhs = XEXP (XEXP (x, 0), 0);
1861 rtx ashift_rhs = XEXP (XEXP (x, 0), 1);
1862 if (REG_P (ashift_lhs)
1863 && CONST_INT_P (ashift_rhs)
1864 && CONST_INT_P (and_rhs)
1865 && ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))
1866 *total = COSTS_N_INSNS (1);
1867 return true;
1868 }
1869 /* bclri pattern for zbs. */
1870 if (TARGET_ZBS
1871 && not_single_bit_mask_operand (XEXP (x, 1), VOIDmode))
1872 {
1873 *total = COSTS_N_INSNS (1);
1874 return true;
1875 }
1876 /* bclr pattern for zbs. */
1877 if (TARGET_ZBS
1878 && REG_P (XEXP (x, 1))
1879 && GET_CODE (XEXP (x, 0)) == ROTATE
1880 && CONST_INT_P (XEXP ((XEXP (x, 0)), 0))
1881 && INTVAL (XEXP ((XEXP (x, 0)), 0)) == -2)
1882 {
1883 *total = COSTS_N_INSNS (1);
1884 return true;
1885 }
1886
1887 gcc_fallthrough ();
1888 case IOR:
1889 case XOR:
1890 /* orn, andn and xorn pattern for zbb. */
1891 if (TARGET_ZBB
1892 && GET_CODE (XEXP (x, 0)) == NOT)
1893 {
1894 *total = riscv_binary_cost (x, 1, 2);
1895 return true;
1896 }
1897
1898 /* bset[i] and binv[i] pattern for zbs. */
1899 if ((GET_CODE (x) == IOR || GET_CODE (x) == XOR)
1900 && TARGET_ZBS
1901 && ((GET_CODE (XEXP (x, 0)) == ASHIFT
1902 && CONST_INT_P (XEXP (XEXP (x, 0), 0)))
1903 || single_bit_mask_operand (XEXP (x, 1), VOIDmode)))
1904 {
1905 *total = COSTS_N_INSNS (1);
1906 return true;
1907 }
1908
1909 /* Double-word operations use two single-word operations. */
1910 *total = riscv_binary_cost (x, 1, 2);
1911 return false;
1912
1913 case ZERO_EXTRACT:
1914 /* This is an SImode shift. */
1915 if (outer_code == SET
1916 && CONST_INT_P (XEXP (x, 1))
1917 && CONST_INT_P (XEXP (x, 2))
1918 && (INTVAL (XEXP (x, 2)) > 0)
1919 && (INTVAL (XEXP (x, 1)) + INTVAL (XEXP (x, 2)) == 32))
1920 {
1921 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
1922 return true;
1923 }
1924 /* bext pattern for zbs. */
1925 if (TARGET_ZBS && outer_code == SET
1926 && GET_CODE (XEXP (x, 1)) == CONST_INT
1927 && INTVAL (XEXP (x, 1)) == 1)
1928 {
1929 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
1930 return true;
1931 }
1932 return false;
1933
1934 case ASHIFT:
1935 /* bset pattern for zbs. */
1936 if (TARGET_ZBS
1937 && CONST_INT_P (XEXP (x, 0))
1938 && INTVAL (XEXP (x, 0)) == 1)
1939 {
1940 *total = COSTS_N_INSNS (1);
1941 return true;
1942 }
1943 gcc_fallthrough ();
1944 case ASHIFTRT:
1945 case LSHIFTRT:
1946 *total = riscv_binary_cost (x, SINGLE_SHIFT_COST,
1947 CONSTANT_P (XEXP (x, 1)) ? 4 : 9);
1948 return false;
1949
1950 case ABS:
1951 *total = COSTS_N_INSNS (float_mode_p ? 1 : 3);
1952 return false;
1953
1954 case LO_SUM:
1955 *total = set_src_cost (XEXP (x, 0), mode, speed);
1956 return true;
1957
1958 case LT:
1959 /* This is an SImode shift. */
1960 if (outer_code == SET && GET_MODE (x) == DImode
1961 && GET_MODE (XEXP (x, 0)) == SImode)
1962 {
1963 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
1964 return true;
1965 }
1966 /* Fall through. */
1967 case LTU:
1968 case LE:
1969 case LEU:
1970 case GT:
1971 case GTU:
1972 case GE:
1973 case GEU:
1974 case EQ:
1975 case NE:
1976 /* Branch comparisons have VOIDmode, so use the first operand's
1977 mode instead. */
1978 mode = GET_MODE (XEXP (x, 0));
1979 if (float_mode_p)
1980 *total = tune_param->fp_add[mode == DFmode];
1981 else
1982 *total = riscv_binary_cost (x, 1, 3);
1983 return false;
1984
1985 case UNORDERED:
1986 case ORDERED:
1987 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */
1988 mode = GET_MODE (XEXP (x, 0));
1989 *total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (2);
1990 return false;
1991
1992 case UNEQ:
1993 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */
1994 mode = GET_MODE (XEXP (x, 0));
1995 *total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (3);
1996 return false;
1997
1998 case LTGT:
1999 /* (FLT(A, A) || FGT(B, B)). */
2000 mode = GET_MODE (XEXP (x, 0));
2001 *total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (2);
2002 return false;
2003
2004 case UNGE:
2005 case UNGT:
2006 case UNLE:
2007 case UNLT:
2008 /* FLT or FLE, but guarded by an FFLAGS read and write. */
2009 mode = GET_MODE (XEXP (x, 0));
2010 *total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (4);
2011 return false;
2012
2013 case MINUS:
2014 case PLUS:
2015 /* add.uw pattern for zba. */
2016 if (TARGET_ZBA
2017 && (TARGET_64BIT && (mode == DImode))
2018 && GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2019 && REG_P (XEXP (XEXP (x, 0), 0))
2020 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
2021 {
2022 *total = COSTS_N_INSNS (1);
2023 return true;
2024 }
2025 /* shNadd pattern for zba. */
2026 if (TARGET_ZBA
2027 && ((!TARGET_64BIT && (mode == SImode)) ||
2028 (TARGET_64BIT && (mode == DImode)))
2029 && (GET_CODE (XEXP (x, 0)) == ASHIFT)
2030 && REG_P (XEXP (XEXP (x, 0), 0))
2031 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
2032 && IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1)), 1, 3))
2033 {
2034 *total = COSTS_N_INSNS (1);
2035 return true;
2036 }
2037 /* shNadd.uw pattern for zba.
2038 [(set (match_operand:DI 0 "register_operand" "=r")
2039 (plus:DI
2040 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2041 (match_operand:QI 2 "immediate_operand" "I"))
2042 (match_operand 3 "immediate_operand" ""))
2043 (match_operand:DI 4 "register_operand" "r")))]
2044 "TARGET_64BIT && TARGET_ZBA
2045 && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
2046 && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
2047 */
2048 if (TARGET_ZBA
2049 && (TARGET_64BIT && (mode == DImode))
2050 && (GET_CODE (XEXP (x, 0)) == AND)
2051 && (REG_P (XEXP (x, 1))))
2052 {
2053 do {
2054 rtx and_lhs = XEXP (XEXP (x, 0), 0);
2055 rtx and_rhs = XEXP (XEXP (x, 0), 1);
2056 if (GET_CODE (and_lhs) != ASHIFT)
2057 break;
2058 if (!CONST_INT_P (and_rhs))
2059 break;
2060
2061 rtx ashift_rhs = XEXP (and_lhs, 1);
2062
2063 if (!CONST_INT_P (ashift_rhs)
2064 || !IN_RANGE (INTVAL (ashift_rhs), 1, 3))
2065 break;
2066
2067 if (CONST_INT_P (and_rhs)
2068 && ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))
2069 {
2070 *total = COSTS_N_INSNS (1);
2071 return true;
2072 }
2073 } while (false);
2074 }
2075
2076 if (float_mode_p)
2077 *total = tune_param->fp_add[mode == DFmode];
2078 else
2079 *total = riscv_binary_cost (x, 1, 4);
2080 return false;
2081
2082 case NEG:
2083 {
2084 rtx op = XEXP (x, 0);
2085 if (GET_CODE (op) == FMA && !HONOR_SIGNED_ZEROS (mode))
2086 {
2087 *total = (tune_param->fp_mul[mode == DFmode]
2088 + set_src_cost (XEXP (op, 0), mode, speed)
2089 + set_src_cost (XEXP (op, 1), mode, speed)
2090 + set_src_cost (XEXP (op, 2), mode, speed));
2091 return true;
2092 }
2093 }
2094
2095 if (float_mode_p)
2096 *total = tune_param->fp_add[mode == DFmode];
2097 else
2098 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
2099 return false;
2100
2101 case MULT:
2102 if (float_mode_p)
2103 *total = tune_param->fp_mul[mode == DFmode];
2104 else if (!TARGET_MUL)
2105 /* Estimate the cost of a library call. */
2106 *total = COSTS_N_INSNS (speed ? 32 : 6);
2107 else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2108 *total = 3 * tune_param->int_mul[0] + COSTS_N_INSNS (2);
2109 else if (!speed)
2110 *total = COSTS_N_INSNS (1);
2111 else
2112 *total = tune_param->int_mul[mode == DImode];
2113 return false;
2114
2115 case DIV:
2116 case SQRT:
2117 case MOD:
2118 if (float_mode_p)
2119 {
2120 *total = tune_param->fp_div[mode == DFmode];
2121 return false;
2122 }
2123 /* Fall through. */
2124
2125 case UDIV:
2126 case UMOD:
2127 if (!TARGET_DIV)
2128 /* Estimate the cost of a library call. */
2129 *total = COSTS_N_INSNS (speed ? 32 : 6);
2130 else if (speed)
2131 *total = tune_param->int_div[mode == DImode];
2132 else
2133 *total = COSTS_N_INSNS (1);
2134 return false;
2135
2136 case ZERO_EXTEND:
2137 /* This is an SImode shift. */
2138 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT)
2139 {
2140 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
2141 return true;
2142 }
2143 /* Fall through. */
2144 case SIGN_EXTEND:
2145 *total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND);
2146 return false;
2147
2148 case FLOAT:
2149 case UNSIGNED_FLOAT:
2150 case FIX:
2151 case FLOAT_EXTEND:
2152 case FLOAT_TRUNCATE:
2153 *total = tune_param->fp_add[mode == DFmode];
2154 return false;
2155
2156 case FMA:
2157 *total = (tune_param->fp_mul[mode == DFmode]
2158 + set_src_cost (XEXP (x, 0), mode, speed)
2159 + set_src_cost (XEXP (x, 1), mode, speed)
2160 + set_src_cost (XEXP (x, 2), mode, speed));
2161 return true;
2162
2163 case UNSPEC:
2164 if (XINT (x, 1) == UNSPEC_AUIPC)
2165 {
2166 /* Make AUIPC cheap to avoid spilling its result to the stack. */
2167 *total = 1;
2168 return true;
2169 }
2170 return false;
2171
2172 default:
2173 return false;
2174 }
2175 }
2176
2177 /* Implement TARGET_ADDRESS_COST. */
2178
2179 static int
riscv_address_cost(rtx addr,machine_mode mode,addr_space_t as ATTRIBUTE_UNUSED,bool speed ATTRIBUTE_UNUSED)2180 riscv_address_cost (rtx addr, machine_mode mode,
2181 addr_space_t as ATTRIBUTE_UNUSED,
2182 bool speed ATTRIBUTE_UNUSED)
2183 {
2184 /* When optimizing for size, make uncompressible 32-bit addresses more
2185 * expensive so that compressible 32-bit addresses are preferred. */
2186 if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
2187 && !riscv_compressed_lw_address_p (addr))
2188 return riscv_address_insns (addr, mode, false) + 1;
2189 return riscv_address_insns (addr, mode, false);
2190 }
2191
2192 /* Return one word of double-word value OP. HIGH_P is true to select the
2193 high part or false to select the low part. */
2194
2195 rtx
riscv_subword(rtx op,bool high_p)2196 riscv_subword (rtx op, bool high_p)
2197 {
2198 unsigned int byte = (high_p != BYTES_BIG_ENDIAN) ? UNITS_PER_WORD : 0;
2199 machine_mode mode = GET_MODE (op);
2200
2201 if (mode == VOIDmode)
2202 mode = TARGET_64BIT ? TImode : DImode;
2203
2204 if (MEM_P (op))
2205 return adjust_address (op, word_mode, byte);
2206
2207 if (REG_P (op))
2208 gcc_assert (!FP_REG_RTX_P (op));
2209
2210 return simplify_gen_subreg (word_mode, op, mode, byte);
2211 }
2212
2213 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2214
2215 bool
riscv_split_64bit_move_p(rtx dest,rtx src)2216 riscv_split_64bit_move_p (rtx dest, rtx src)
2217 {
2218 if (TARGET_64BIT)
2219 return false;
2220
2221 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case
2222 of zeroing an FPR with FCVT.D.W. */
2223 if (TARGET_DOUBLE_FLOAT
2224 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2225 || (FP_REG_RTX_P (dest) && MEM_P (src))
2226 || (FP_REG_RTX_P (src) && MEM_P (dest))
2227 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src)))))
2228 return false;
2229
2230 return true;
2231 }
2232
2233 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
2234 this function handles 64-bit moves for which riscv_split_64bit_move_p
2235 holds. For 64-bit targets, this function handles 128-bit moves. */
2236
2237 void
riscv_split_doubleword_move(rtx dest,rtx src)2238 riscv_split_doubleword_move (rtx dest, rtx src)
2239 {
2240 rtx low_dest;
2241
2242 /* The operation can be split into two normal moves. Decide in
2243 which order to do them. */
2244 low_dest = riscv_subword (dest, false);
2245 if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src))
2246 {
2247 riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true));
2248 riscv_emit_move (low_dest, riscv_subword (src, false));
2249 }
2250 else
2251 {
2252 riscv_emit_move (low_dest, riscv_subword (src, false));
2253 riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true));
2254 }
2255 }
2256
2257 /* Return the appropriate instructions to move SRC into DEST. Assume
2258 that SRC is operand 1 and DEST is operand 0. */
2259
2260 const char *
riscv_output_move(rtx dest,rtx src)2261 riscv_output_move (rtx dest, rtx src)
2262 {
2263 enum rtx_code dest_code, src_code;
2264 machine_mode mode;
2265 bool dbl_p;
2266
2267 dest_code = GET_CODE (dest);
2268 src_code = GET_CODE (src);
2269 mode = GET_MODE (dest);
2270 dbl_p = (GET_MODE_SIZE (mode) == 8);
2271
2272 if (dbl_p && riscv_split_64bit_move_p (dest, src))
2273 return "#";
2274
2275 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2276 {
2277 if (src_code == REG && FP_REG_P (REGNO (src)))
2278 return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1";
2279
2280 if (src_code == MEM)
2281 switch (GET_MODE_SIZE (mode))
2282 {
2283 case 1: return "lbu\t%0,%1";
2284 case 2: return "lhu\t%0,%1";
2285 case 4: return "lw\t%0,%1";
2286 case 8: return "ld\t%0,%1";
2287 }
2288
2289 if (src_code == CONST_INT)
2290 {
2291 if (SMALL_OPERAND (INTVAL (src)) || LUI_OPERAND (INTVAL (src)))
2292 return "li\t%0,%1";
2293
2294 if (TARGET_ZBS
2295 && SINGLE_BIT_MASK_OPERAND (INTVAL (src)))
2296 return "bseti\t%0,zero,%S1";
2297
2298 /* Should never reach here. */
2299 abort ();
2300 }
2301
2302 if (src_code == HIGH)
2303 return "lui\t%0,%h1";
2304
2305 if (symbolic_operand (src, VOIDmode))
2306 switch (riscv_classify_symbolic_expression (src))
2307 {
2308 case SYMBOL_GOT_DISP: return "la\t%0,%1";
2309 case SYMBOL_ABSOLUTE: return "lla\t%0,%1";
2310 case SYMBOL_PCREL: return "lla\t%0,%1";
2311 default: gcc_unreachable ();
2312 }
2313 }
2314 if ((src_code == REG && GP_REG_P (REGNO (src)))
2315 || (src == CONST0_RTX (mode)))
2316 {
2317 if (dest_code == REG)
2318 {
2319 if (GP_REG_P (REGNO (dest)))
2320 return "mv\t%0,%z1";
2321
2322 if (FP_REG_P (REGNO (dest)))
2323 {
2324 if (!dbl_p)
2325 return "fmv.w.x\t%0,%z1";
2326 if (TARGET_64BIT)
2327 return "fmv.d.x\t%0,%z1";
2328 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
2329 gcc_assert (src == CONST0_RTX (mode));
2330 return "fcvt.d.w\t%0,x0";
2331 }
2332 }
2333 if (dest_code == MEM)
2334 switch (GET_MODE_SIZE (mode))
2335 {
2336 case 1: return "sb\t%z1,%0";
2337 case 2: return "sh\t%z1,%0";
2338 case 4: return "sw\t%z1,%0";
2339 case 8: return "sd\t%z1,%0";
2340 }
2341 }
2342 if (src_code == REG && FP_REG_P (REGNO (src)))
2343 {
2344 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2345 return dbl_p ? "fmv.d\t%0,%1" : "fmv.s\t%0,%1";
2346
2347 if (dest_code == MEM)
2348 return dbl_p ? "fsd\t%1,%0" : "fsw\t%1,%0";
2349 }
2350 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2351 {
2352 if (src_code == MEM)
2353 return dbl_p ? "fld\t%0,%1" : "flw\t%0,%1";
2354 }
2355 gcc_unreachable ();
2356 }
2357
2358 const char *
riscv_output_return()2359 riscv_output_return ()
2360 {
2361 if (cfun->machine->naked_p)
2362 return "";
2363
2364 return "ret";
2365 }
2366
2367
2368 /* Return true if CMP1 is a suitable second operand for integer ordering
2369 test CODE. See also the *sCC patterns in riscv.md. */
2370
2371 static bool
riscv_int_order_operand_ok_p(enum rtx_code code,rtx cmp1)2372 riscv_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
2373 {
2374 switch (code)
2375 {
2376 case GT:
2377 case GTU:
2378 return reg_or_0_operand (cmp1, VOIDmode);
2379
2380 case GE:
2381 case GEU:
2382 return cmp1 == const1_rtx;
2383
2384 case LT:
2385 case LTU:
2386 return arith_operand (cmp1, VOIDmode);
2387
2388 case LE:
2389 return sle_operand (cmp1, VOIDmode);
2390
2391 case LEU:
2392 return sleu_operand (cmp1, VOIDmode);
2393
2394 default:
2395 gcc_unreachable ();
2396 }
2397 }
2398
2399 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
2400 integer ordering test *CODE, or if an equivalent combination can
2401 be formed by adjusting *CODE and *CMP1. When returning true, update
2402 *CODE and *CMP1 with the chosen code and operand, otherwise leave
2403 them alone. */
2404
2405 static bool
riscv_canonicalize_int_order_test(enum rtx_code * code,rtx * cmp1,machine_mode mode)2406 riscv_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
2407 machine_mode mode)
2408 {
2409 HOST_WIDE_INT plus_one;
2410
2411 if (riscv_int_order_operand_ok_p (*code, *cmp1))
2412 return true;
2413
2414 if (CONST_INT_P (*cmp1))
2415 switch (*code)
2416 {
2417 case LE:
2418 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
2419 if (INTVAL (*cmp1) < plus_one)
2420 {
2421 *code = LT;
2422 *cmp1 = force_reg (mode, GEN_INT (plus_one));
2423 return true;
2424 }
2425 break;
2426
2427 case LEU:
2428 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
2429 if (plus_one != 0)
2430 {
2431 *code = LTU;
2432 *cmp1 = force_reg (mode, GEN_INT (plus_one));
2433 return true;
2434 }
2435 break;
2436
2437 default:
2438 break;
2439 }
2440 return false;
2441 }
2442
2443 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
2444 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
2445 is nonnull, it's OK to set TARGET to the inverse of the result and
2446 flip *INVERT_PTR instead. */
2447
2448 static void
riscv_emit_int_order_test(enum rtx_code code,bool * invert_ptr,rtx target,rtx cmp0,rtx cmp1)2449 riscv_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
2450 rtx target, rtx cmp0, rtx cmp1)
2451 {
2452 machine_mode mode;
2453
2454 /* First see if there is a RISCV instruction that can do this operation.
2455 If not, try doing the same for the inverse operation. If that also
2456 fails, force CMP1 into a register and try again. */
2457 mode = GET_MODE (cmp0);
2458 if (riscv_canonicalize_int_order_test (&code, &cmp1, mode))
2459 riscv_emit_binary (code, target, cmp0, cmp1);
2460 else
2461 {
2462 enum rtx_code inv_code = reverse_condition (code);
2463 if (!riscv_canonicalize_int_order_test (&inv_code, &cmp1, mode))
2464 {
2465 cmp1 = force_reg (mode, cmp1);
2466 riscv_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
2467 }
2468 else if (invert_ptr == 0)
2469 {
2470 rtx inv_target = riscv_force_binary (GET_MODE (target),
2471 inv_code, cmp0, cmp1);
2472 riscv_emit_binary (XOR, target, inv_target, const1_rtx);
2473 }
2474 else
2475 {
2476 *invert_ptr = !*invert_ptr;
2477 riscv_emit_binary (inv_code, target, cmp0, cmp1);
2478 }
2479 }
2480 }
2481
2482 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2483 The register will have the same mode as CMP0. */
2484
2485 static rtx
riscv_zero_if_equal(rtx cmp0,rtx cmp1)2486 riscv_zero_if_equal (rtx cmp0, rtx cmp1)
2487 {
2488 if (cmp1 == const0_rtx)
2489 return cmp0;
2490
2491 return expand_binop (GET_MODE (cmp0), sub_optab,
2492 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
2493 }
2494
2495 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */
2496
2497 static void
riscv_extend_comparands(rtx_code code,rtx * op0,rtx * op1)2498 riscv_extend_comparands (rtx_code code, rtx *op0, rtx *op1)
2499 {
2500 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */
2501 if (GET_MODE_SIZE (word_mode) > GET_MODE_SIZE (GET_MODE (*op0)))
2502 {
2503 /* It is more profitable to zero-extend QImode values. But not if the
2504 first operand has already been sign-extended, and the second one is
2505 is a constant or has already been sign-extended also. */
2506 if (unsigned_condition (code) == code
2507 && (GET_MODE (*op0) == QImode
2508 && ! (GET_CODE (*op0) == SUBREG
2509 && SUBREG_PROMOTED_VAR_P (*op0)
2510 && SUBREG_PROMOTED_SIGNED_P (*op0)
2511 && (CONST_INT_P (*op1)
2512 || (GET_CODE (*op1) == SUBREG
2513 && SUBREG_PROMOTED_VAR_P (*op1)
2514 && SUBREG_PROMOTED_SIGNED_P (*op1))))))
2515 {
2516 *op0 = gen_rtx_ZERO_EXTEND (word_mode, *op0);
2517 if (CONST_INT_P (*op1))
2518 *op1 = GEN_INT ((uint8_t) INTVAL (*op1));
2519 else
2520 *op1 = gen_rtx_ZERO_EXTEND (word_mode, *op1);
2521 }
2522 else
2523 {
2524 *op0 = gen_rtx_SIGN_EXTEND (word_mode, *op0);
2525 if (*op1 != const0_rtx)
2526 *op1 = gen_rtx_SIGN_EXTEND (word_mode, *op1);
2527 }
2528 }
2529 }
2530
2531 /* Convert a comparison into something that can be used in a branch. On
2532 entry, *OP0 and *OP1 are the values being compared and *CODE is the code
2533 used to compare them. Update them to describe the final comparison. */
2534
2535 static void
riscv_emit_int_compare(enum rtx_code * code,rtx * op0,rtx * op1)2536 riscv_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1)
2537 {
2538 if (splittable_const_int_operand (*op1, VOIDmode))
2539 {
2540 HOST_WIDE_INT rhs = INTVAL (*op1);
2541
2542 if (*code == EQ || *code == NE)
2543 {
2544 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */
2545 if (SMALL_OPERAND (-rhs))
2546 {
2547 *op0 = riscv_force_binary (GET_MODE (*op0), PLUS, *op0,
2548 GEN_INT (-rhs));
2549 *op1 = const0_rtx;
2550 }
2551 }
2552 else
2553 {
2554 static const enum rtx_code mag_comparisons[][2] = {
2555 {LEU, LTU}, {GTU, GEU}, {LE, LT}, {GT, GE}
2556 };
2557
2558 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */
2559 for (size_t i = 0; i < ARRAY_SIZE (mag_comparisons); i++)
2560 {
2561 HOST_WIDE_INT new_rhs;
2562 bool increment = *code == mag_comparisons[i][0];
2563 bool decrement = *code == mag_comparisons[i][1];
2564 if (!increment && !decrement)
2565 continue;
2566
2567 new_rhs = rhs + (increment ? 1 : -1);
2568 if (riscv_integer_cost (new_rhs) < riscv_integer_cost (rhs)
2569 && (rhs < 0) == (new_rhs < 0))
2570 {
2571 *op1 = GEN_INT (new_rhs);
2572 *code = mag_comparisons[i][increment];
2573 }
2574 break;
2575 }
2576 }
2577 }
2578
2579 riscv_extend_comparands (*code, op0, op1);
2580
2581 *op0 = force_reg (word_mode, *op0);
2582 if (*op1 != const0_rtx)
2583 *op1 = force_reg (word_mode, *op1);
2584 }
2585
2586 /* Like riscv_emit_int_compare, but for floating-point comparisons. */
2587
2588 static void
riscv_emit_float_compare(enum rtx_code * code,rtx * op0,rtx * op1)2589 riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1)
2590 {
2591 rtx tmp0, tmp1, cmp_op0 = *op0, cmp_op1 = *op1;
2592 enum rtx_code fp_code = *code;
2593 *code = NE;
2594
2595 switch (fp_code)
2596 {
2597 case UNORDERED:
2598 *code = EQ;
2599 /* Fall through. */
2600
2601 case ORDERED:
2602 /* a == a && b == b */
2603 tmp0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op0);
2604 tmp1 = riscv_force_binary (word_mode, EQ, cmp_op1, cmp_op1);
2605 *op0 = riscv_force_binary (word_mode, AND, tmp0, tmp1);
2606 *op1 = const0_rtx;
2607 break;
2608
2609 case UNEQ:
2610 /* ordered(a, b) > (a == b) */
2611 *code = EQ;
2612 tmp0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op0);
2613 tmp1 = riscv_force_binary (word_mode, EQ, cmp_op1, cmp_op1);
2614 *op0 = riscv_force_binary (word_mode, AND, tmp0, tmp1);
2615 *op1 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op1);
2616 break;
2617
2618 #define UNORDERED_COMPARISON(CODE, CMP) \
2619 case CODE: \
2620 *code = EQ; \
2621 *op0 = gen_reg_rtx (word_mode); \
2622 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \
2623 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \
2624 else if (GET_MODE (cmp_op0) == SFmode) \
2625 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \
2626 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \
2627 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \
2628 else if (GET_MODE (cmp_op0) == DFmode) \
2629 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \
2630 else \
2631 gcc_unreachable (); \
2632 *op1 = const0_rtx; \
2633 break;
2634
2635 case UNLT:
2636 std::swap (cmp_op0, cmp_op1);
2637 gcc_fallthrough ();
2638
2639 UNORDERED_COMPARISON(UNGT, le)
2640
2641 case UNLE:
2642 std::swap (cmp_op0, cmp_op1);
2643 gcc_fallthrough ();
2644
2645 UNORDERED_COMPARISON(UNGE, lt)
2646 #undef UNORDERED_COMPARISON
2647
2648 case NE:
2649 fp_code = EQ;
2650 *code = EQ;
2651 /* Fall through. */
2652
2653 case EQ:
2654 case LE:
2655 case LT:
2656 case GE:
2657 case GT:
2658 /* We have instructions for these cases. */
2659 *op0 = riscv_force_binary (word_mode, fp_code, cmp_op0, cmp_op1);
2660 *op1 = const0_rtx;
2661 break;
2662
2663 case LTGT:
2664 /* (a < b) | (a > b) */
2665 tmp0 = riscv_force_binary (word_mode, LT, cmp_op0, cmp_op1);
2666 tmp1 = riscv_force_binary (word_mode, GT, cmp_op0, cmp_op1);
2667 *op0 = riscv_force_binary (word_mode, IOR, tmp0, tmp1);
2668 *op1 = const0_rtx;
2669 break;
2670
2671 default:
2672 gcc_unreachable ();
2673 }
2674 }
2675
2676 /* CODE-compare OP0 and OP1. Store the result in TARGET. */
2677
2678 void
riscv_expand_int_scc(rtx target,enum rtx_code code,rtx op0,rtx op1)2679 riscv_expand_int_scc (rtx target, enum rtx_code code, rtx op0, rtx op1)
2680 {
2681 riscv_extend_comparands (code, &op0, &op1);
2682 op0 = force_reg (word_mode, op0);
2683
2684 if (code == EQ || code == NE)
2685 {
2686 rtx zie = riscv_zero_if_equal (op0, op1);
2687 riscv_emit_binary (code, target, zie, const0_rtx);
2688 }
2689 else
2690 riscv_emit_int_order_test (code, 0, target, op0, op1);
2691 }
2692
2693 /* Like riscv_expand_int_scc, but for floating-point comparisons. */
2694
2695 void
riscv_expand_float_scc(rtx target,enum rtx_code code,rtx op0,rtx op1)2696 riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1)
2697 {
2698 riscv_emit_float_compare (&code, &op0, &op1);
2699
2700 rtx cmp = riscv_force_binary (word_mode, code, op0, op1);
2701 riscv_emit_set (target, lowpart_subreg (SImode, cmp, word_mode));
2702 }
2703
2704 /* Jump to LABEL if (CODE OP0 OP1) holds. */
2705
2706 void
riscv_expand_conditional_branch(rtx label,rtx_code code,rtx op0,rtx op1)2707 riscv_expand_conditional_branch (rtx label, rtx_code code, rtx op0, rtx op1)
2708 {
2709 if (FLOAT_MODE_P (GET_MODE (op1)))
2710 riscv_emit_float_compare (&code, &op0, &op1);
2711 else
2712 riscv_emit_int_compare (&code, &op0, &op1);
2713
2714 rtx condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
2715 emit_jump_insn (gen_condjump (condition, label));
2716 }
2717
2718 /* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */
2719
2720 void
riscv_expand_conditional_move(rtx dest,rtx cons,rtx alt,rtx_code code,rtx op0,rtx op1)2721 riscv_expand_conditional_move (rtx dest, rtx cons, rtx alt, rtx_code code,
2722 rtx op0, rtx op1)
2723 {
2724 riscv_emit_int_compare (&code, &op0, &op1);
2725 rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
2726 emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest), cond,
2727 cons, alt)));
2728 }
2729
2730 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
2731 least PARM_BOUNDARY bits of alignment, but will be given anything up
2732 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
2733
2734 static unsigned int
riscv_function_arg_boundary(machine_mode mode,const_tree type)2735 riscv_function_arg_boundary (machine_mode mode, const_tree type)
2736 {
2737 unsigned int alignment;
2738
2739 /* Use natural alignment if the type is not aggregate data. */
2740 if (type && !AGGREGATE_TYPE_P (type))
2741 alignment = TYPE_ALIGN (TYPE_MAIN_VARIANT (type));
2742 else
2743 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
2744
2745 return MIN (PREFERRED_STACK_BOUNDARY, MAX (PARM_BOUNDARY, alignment));
2746 }
2747
2748 /* If MODE represents an argument that can be passed or returned in
2749 floating-point registers, return the number of registers, else 0. */
2750
2751 static unsigned
riscv_pass_mode_in_fpr_p(machine_mode mode)2752 riscv_pass_mode_in_fpr_p (machine_mode mode)
2753 {
2754 if (GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FP_ARG)
2755 {
2756 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2757 return 1;
2758
2759 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
2760 return 2;
2761 }
2762
2763 return 0;
2764 }
2765
2766 typedef struct {
2767 const_tree type;
2768 HOST_WIDE_INT offset;
2769 } riscv_aggregate_field;
2770
2771 /* Identify subfields of aggregates that are candidates for passing in
2772 floating-point registers. */
2773
2774 static int
riscv_flatten_aggregate_field(const_tree type,riscv_aggregate_field fields[2],int n,HOST_WIDE_INT offset,bool ignore_zero_width_bit_field_p)2775 riscv_flatten_aggregate_field (const_tree type,
2776 riscv_aggregate_field fields[2],
2777 int n, HOST_WIDE_INT offset,
2778 bool ignore_zero_width_bit_field_p)
2779 {
2780 switch (TREE_CODE (type))
2781 {
2782 case RECORD_TYPE:
2783 /* Can't handle incomplete types nor sizes that are not fixed. */
2784 if (!COMPLETE_TYPE_P (type)
2785 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST
2786 || !tree_fits_uhwi_p (TYPE_SIZE (type)))
2787 return -1;
2788
2789 for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
2790 if (TREE_CODE (f) == FIELD_DECL)
2791 {
2792 if (!TYPE_P (TREE_TYPE (f)))
2793 return -1;
2794
2795 /* The C++ front end strips zero-length bit-fields from structs.
2796 So we need to ignore them in the C front end to make C code
2797 compatible with C++ code. */
2798 if (ignore_zero_width_bit_field_p
2799 && DECL_BIT_FIELD (f)
2800 && (DECL_SIZE (f) == NULL_TREE
2801 || integer_zerop (DECL_SIZE (f))))
2802 ;
2803 else
2804 {
2805 HOST_WIDE_INT pos = offset + int_byte_position (f);
2806 n = riscv_flatten_aggregate_field (TREE_TYPE (f),
2807 fields, n, pos,
2808 ignore_zero_width_bit_field_p);
2809 }
2810 if (n < 0)
2811 return -1;
2812 }
2813 return n;
2814
2815 case ARRAY_TYPE:
2816 {
2817 HOST_WIDE_INT n_elts;
2818 riscv_aggregate_field subfields[2];
2819 tree index = TYPE_DOMAIN (type);
2820 tree elt_size = TYPE_SIZE_UNIT (TREE_TYPE (type));
2821 int n_subfields = riscv_flatten_aggregate_field (TREE_TYPE (type),
2822 subfields, 0, offset,
2823 ignore_zero_width_bit_field_p);
2824
2825 /* Can't handle incomplete types nor sizes that are not fixed. */
2826 if (n_subfields <= 0
2827 || !COMPLETE_TYPE_P (type)
2828 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST
2829 || !index
2830 || !TYPE_MAX_VALUE (index)
2831 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
2832 || !TYPE_MIN_VALUE (index)
2833 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
2834 || !tree_fits_uhwi_p (elt_size))
2835 return -1;
2836
2837 n_elts = 1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
2838 - tree_to_uhwi (TYPE_MIN_VALUE (index));
2839 gcc_assert (n_elts >= 0);
2840
2841 for (HOST_WIDE_INT i = 0; i < n_elts; i++)
2842 for (int j = 0; j < n_subfields; j++)
2843 {
2844 if (n >= 2)
2845 return -1;
2846
2847 fields[n] = subfields[j];
2848 fields[n++].offset += i * tree_to_uhwi (elt_size);
2849 }
2850
2851 return n;
2852 }
2853
2854 case COMPLEX_TYPE:
2855 {
2856 /* Complex type need consume 2 field, so n must be 0. */
2857 if (n != 0)
2858 return -1;
2859
2860 HOST_WIDE_INT elt_size = GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type)));
2861
2862 if (elt_size <= UNITS_PER_FP_ARG)
2863 {
2864 fields[0].type = TREE_TYPE (type);
2865 fields[0].offset = offset;
2866 fields[1].type = TREE_TYPE (type);
2867 fields[1].offset = offset + elt_size;
2868
2869 return 2;
2870 }
2871
2872 return -1;
2873 }
2874
2875 default:
2876 if (n < 2
2877 && ((SCALAR_FLOAT_TYPE_P (type)
2878 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FP_ARG)
2879 || (INTEGRAL_TYPE_P (type)
2880 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_WORD)))
2881 {
2882 fields[n].type = type;
2883 fields[n].offset = offset;
2884 return n + 1;
2885 }
2886 else
2887 return -1;
2888 }
2889 }
2890
2891 /* Identify candidate aggregates for passing in floating-point registers.
2892 Candidates have at most two fields after flattening. */
2893
2894 static int
riscv_flatten_aggregate_argument(const_tree type,riscv_aggregate_field fields[2],bool ignore_zero_width_bit_field_p)2895 riscv_flatten_aggregate_argument (const_tree type,
2896 riscv_aggregate_field fields[2],
2897 bool ignore_zero_width_bit_field_p)
2898 {
2899 if (!type || TREE_CODE (type) != RECORD_TYPE)
2900 return -1;
2901
2902 return riscv_flatten_aggregate_field (type, fields, 0, 0,
2903 ignore_zero_width_bit_field_p);
2904 }
2905
2906 /* See whether TYPE is a record whose fields should be returned in one or
2907 two floating-point registers. If so, populate FIELDS accordingly. */
2908
2909 static unsigned
riscv_pass_aggregate_in_fpr_pair_p(const_tree type,riscv_aggregate_field fields[2])2910 riscv_pass_aggregate_in_fpr_pair_p (const_tree type,
2911 riscv_aggregate_field fields[2])
2912 {
2913 static int warned = 0;
2914
2915 /* This is the old ABI, which differs for C++ and C. */
2916 int n_old = riscv_flatten_aggregate_argument (type, fields, false);
2917 for (int i = 0; i < n_old; i++)
2918 if (!SCALAR_FLOAT_TYPE_P (fields[i].type))
2919 {
2920 n_old = -1;
2921 break;
2922 }
2923
2924 /* This is the new ABI, which is the same for C++ and C. */
2925 int n_new = riscv_flatten_aggregate_argument (type, fields, true);
2926 for (int i = 0; i < n_new; i++)
2927 if (!SCALAR_FLOAT_TYPE_P (fields[i].type))
2928 {
2929 n_new = -1;
2930 break;
2931 }
2932
2933 if ((n_old != n_new) && (warned == 0))
2934 {
2935 warning (OPT_Wpsabi, "ABI for flattened struct with zero-length "
2936 "bit-fields changed in GCC 10");
2937 warned = 1;
2938 }
2939
2940 return n_new > 0 ? n_new : 0;
2941 }
2942
2943 /* See whether TYPE is a record whose fields should be returned in one or
2944 floating-point register and one integer register. If so, populate
2945 FIELDS accordingly. */
2946
2947 static bool
riscv_pass_aggregate_in_fpr_and_gpr_p(const_tree type,riscv_aggregate_field fields[2])2948 riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type,
2949 riscv_aggregate_field fields[2])
2950 {
2951 static int warned = 0;
2952
2953 /* This is the old ABI, which differs for C++ and C. */
2954 unsigned num_int_old = 0, num_float_old = 0;
2955 int n_old = riscv_flatten_aggregate_argument (type, fields, false);
2956 for (int i = 0; i < n_old; i++)
2957 {
2958 num_float_old += SCALAR_FLOAT_TYPE_P (fields[i].type);
2959 num_int_old += INTEGRAL_TYPE_P (fields[i].type);
2960 }
2961
2962 /* This is the new ABI, which is the same for C++ and C. */
2963 unsigned num_int_new = 0, num_float_new = 0;
2964 int n_new = riscv_flatten_aggregate_argument (type, fields, true);
2965 for (int i = 0; i < n_new; i++)
2966 {
2967 num_float_new += SCALAR_FLOAT_TYPE_P (fields[i].type);
2968 num_int_new += INTEGRAL_TYPE_P (fields[i].type);
2969 }
2970
2971 if (((num_int_old == 1 && num_float_old == 1
2972 && (num_int_old != num_int_new || num_float_old != num_float_new))
2973 || (num_int_new == 1 && num_float_new == 1
2974 && (num_int_old != num_int_new || num_float_old != num_float_new)))
2975 && (warned == 0))
2976 {
2977 warning (OPT_Wpsabi, "ABI for flattened struct with zero-length "
2978 "bit-fields changed in GCC 10");
2979 warned = 1;
2980 }
2981
2982 return num_int_new == 1 && num_float_new == 1;
2983 }
2984
2985 /* Return the representation of an argument passed or returned in an FPR
2986 when the value has mode VALUE_MODE and the type has TYPE_MODE. The
2987 two modes may be different for structures like:
2988
2989 struct __attribute__((packed)) foo { float f; }
2990
2991 where the SFmode value "f" is passed in REGNO but the struct itself
2992 has mode BLKmode. */
2993
2994 static rtx
riscv_pass_fpr_single(machine_mode type_mode,unsigned regno,machine_mode value_mode,HOST_WIDE_INT offset)2995 riscv_pass_fpr_single (machine_mode type_mode, unsigned regno,
2996 machine_mode value_mode,
2997 HOST_WIDE_INT offset)
2998 {
2999 rtx x = gen_rtx_REG (value_mode, regno);
3000
3001 if (type_mode != value_mode)
3002 {
3003 x = gen_rtx_EXPR_LIST (VOIDmode, x, GEN_INT (offset));
3004 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
3005 }
3006 return x;
3007 }
3008
3009 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1.
3010 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and
3011 byte offset for the first value, likewise MODE2 and OFFSET2 for the
3012 second value. */
3013
3014 static rtx
riscv_pass_fpr_pair(machine_mode mode,unsigned regno1,machine_mode mode1,HOST_WIDE_INT offset1,unsigned regno2,machine_mode mode2,HOST_WIDE_INT offset2)3015 riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
3016 machine_mode mode1, HOST_WIDE_INT offset1,
3017 unsigned regno2, machine_mode mode2,
3018 HOST_WIDE_INT offset2)
3019 {
3020 return gen_rtx_PARALLEL
3021 (mode,
3022 gen_rtvec (2,
3023 gen_rtx_EXPR_LIST (VOIDmode,
3024 gen_rtx_REG (mode1, regno1),
3025 GEN_INT (offset1)),
3026 gen_rtx_EXPR_LIST (VOIDmode,
3027 gen_rtx_REG (mode2, regno2),
3028 GEN_INT (offset2))));
3029 }
3030
3031 /* Fill INFO with information about a single argument, and return an
3032 RTL pattern to pass or return the argument. CUM is the cumulative
3033 state for earlier arguments. MODE is the mode of this argument and
3034 TYPE is its type (if known). NAMED is true if this is a named
3035 (fixed) argument rather than a variable one. RETURN_P is true if
3036 returning the argument, or false if passing the argument. */
3037
3038 static rtx
riscv_get_arg_info(struct riscv_arg_info * info,const CUMULATIVE_ARGS * cum,machine_mode mode,const_tree type,bool named,bool return_p)3039 riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
3040 machine_mode mode, const_tree type, bool named,
3041 bool return_p)
3042 {
3043 unsigned num_bytes, num_words;
3044 unsigned fpr_base = return_p ? FP_RETURN : FP_ARG_FIRST;
3045 unsigned gpr_base = return_p ? GP_RETURN : GP_ARG_FIRST;
3046 unsigned alignment = riscv_function_arg_boundary (mode, type);
3047
3048 memset (info, 0, sizeof (*info));
3049 info->gpr_offset = cum->num_gprs;
3050 info->fpr_offset = cum->num_fprs;
3051
3052 if (named)
3053 {
3054 riscv_aggregate_field fields[2];
3055 unsigned fregno = fpr_base + info->fpr_offset;
3056 unsigned gregno = gpr_base + info->gpr_offset;
3057
3058 /* Pass one- or two-element floating-point aggregates in FPRs. */
3059 if ((info->num_fprs = riscv_pass_aggregate_in_fpr_pair_p (type, fields))
3060 && info->fpr_offset + info->num_fprs <= MAX_ARGS_IN_REGISTERS)
3061 switch (info->num_fprs)
3062 {
3063 case 1:
3064 return riscv_pass_fpr_single (mode, fregno,
3065 TYPE_MODE (fields[0].type),
3066 fields[0].offset);
3067
3068 case 2:
3069 return riscv_pass_fpr_pair (mode, fregno,
3070 TYPE_MODE (fields[0].type),
3071 fields[0].offset,
3072 fregno + 1,
3073 TYPE_MODE (fields[1].type),
3074 fields[1].offset);
3075
3076 default:
3077 gcc_unreachable ();
3078 }
3079
3080 /* Pass real and complex floating-point numbers in FPRs. */
3081 if ((info->num_fprs = riscv_pass_mode_in_fpr_p (mode))
3082 && info->fpr_offset + info->num_fprs <= MAX_ARGS_IN_REGISTERS)
3083 switch (GET_MODE_CLASS (mode))
3084 {
3085 case MODE_FLOAT:
3086 return gen_rtx_REG (mode, fregno);
3087
3088 case MODE_COMPLEX_FLOAT:
3089 return riscv_pass_fpr_pair (mode, fregno, GET_MODE_INNER (mode), 0,
3090 fregno + 1, GET_MODE_INNER (mode),
3091 GET_MODE_UNIT_SIZE (mode));
3092
3093 default:
3094 gcc_unreachable ();
3095 }
3096
3097 /* Pass structs with one float and one integer in an FPR and a GPR. */
3098 if (riscv_pass_aggregate_in_fpr_and_gpr_p (type, fields)
3099 && info->gpr_offset < MAX_ARGS_IN_REGISTERS
3100 && info->fpr_offset < MAX_ARGS_IN_REGISTERS)
3101 {
3102 info->num_gprs = 1;
3103 info->num_fprs = 1;
3104
3105 if (!SCALAR_FLOAT_TYPE_P (fields[0].type))
3106 std::swap (fregno, gregno);
3107
3108 return riscv_pass_fpr_pair (mode, fregno, TYPE_MODE (fields[0].type),
3109 fields[0].offset,
3110 gregno, TYPE_MODE (fields[1].type),
3111 fields[1].offset);
3112 }
3113 }
3114
3115 /* Work out the size of the argument. */
3116 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3117 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3118
3119 /* Doubleword-aligned varargs start on an even register boundary. */
3120 if (!named && num_bytes != 0 && alignment > BITS_PER_WORD)
3121 info->gpr_offset += info->gpr_offset & 1;
3122
3123 /* Partition the argument between registers and stack. */
3124 info->num_fprs = 0;
3125 info->num_gprs = MIN (num_words, MAX_ARGS_IN_REGISTERS - info->gpr_offset);
3126 info->stack_p = (num_words - info->num_gprs) != 0;
3127
3128 if (info->num_gprs || return_p)
3129 return gen_rtx_REG (mode, gpr_base + info->gpr_offset);
3130
3131 return NULL_RTX;
3132 }
3133
3134 /* Implement TARGET_FUNCTION_ARG. */
3135
3136 static rtx
riscv_function_arg(cumulative_args_t cum_v,const function_arg_info & arg)3137 riscv_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
3138 {
3139 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
3140 struct riscv_arg_info info;
3141
3142 if (arg.end_marker_p ())
3143 return NULL;
3144
3145 return riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false);
3146 }
3147
3148 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
3149
3150 static void
riscv_function_arg_advance(cumulative_args_t cum_v,const function_arg_info & arg)3151 riscv_function_arg_advance (cumulative_args_t cum_v,
3152 const function_arg_info &arg)
3153 {
3154 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
3155 struct riscv_arg_info info;
3156
3157 riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false);
3158
3159 /* Advance the register count. This has the effect of setting
3160 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
3161 argument required us to skip the final GPR and pass the whole
3162 argument on the stack. */
3163 cum->num_fprs = info.fpr_offset + info.num_fprs;
3164 cum->num_gprs = info.gpr_offset + info.num_gprs;
3165 }
3166
3167 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3168
3169 static int
riscv_arg_partial_bytes(cumulative_args_t cum,const function_arg_info & generic_arg)3170 riscv_arg_partial_bytes (cumulative_args_t cum,
3171 const function_arg_info &generic_arg)
3172 {
3173 struct riscv_arg_info arg;
3174
3175 riscv_get_arg_info (&arg, get_cumulative_args (cum), generic_arg.mode,
3176 generic_arg.type, generic_arg.named, false);
3177 return arg.stack_p ? arg.num_gprs * UNITS_PER_WORD : 0;
3178 }
3179
3180 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
3181 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
3182 VALTYPE is null and MODE is the mode of the return value. */
3183
3184 rtx
riscv_function_value(const_tree type,const_tree func,machine_mode mode)3185 riscv_function_value (const_tree type, const_tree func, machine_mode mode)
3186 {
3187 struct riscv_arg_info info;
3188 CUMULATIVE_ARGS args;
3189
3190 if (type)
3191 {
3192 int unsigned_p = TYPE_UNSIGNED (type);
3193
3194 mode = TYPE_MODE (type);
3195
3196 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
3197 return values, promote the mode here too. */
3198 mode = promote_function_mode (type, mode, &unsigned_p, func, 1);
3199 }
3200
3201 memset (&args, 0, sizeof args);
3202 return riscv_get_arg_info (&info, &args, mode, type, true, true);
3203 }
3204
3205 /* Implement TARGET_PASS_BY_REFERENCE. */
3206
3207 static bool
riscv_pass_by_reference(cumulative_args_t cum_v,const function_arg_info & arg)3208 riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg)
3209 {
3210 HOST_WIDE_INT size = arg.type_size_in_bytes ();
3211 struct riscv_arg_info info;
3212 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
3213
3214 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we
3215 never pass variadic arguments in floating-point registers, so we can
3216 avoid the call to riscv_get_arg_info in this case. */
3217 if (cum != NULL)
3218 {
3219 /* Don't pass by reference if we can use a floating-point register. */
3220 riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false);
3221 if (info.num_fprs)
3222 return false;
3223 }
3224
3225 /* Pass by reference if the data do not fit in two integer registers. */
3226 return !IN_RANGE (size, 0, 2 * UNITS_PER_WORD);
3227 }
3228
3229 /* Implement TARGET_RETURN_IN_MEMORY. */
3230
3231 static bool
riscv_return_in_memory(const_tree type,const_tree fndecl ATTRIBUTE_UNUSED)3232 riscv_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
3233 {
3234 CUMULATIVE_ARGS args;
3235 cumulative_args_t cum = pack_cumulative_args (&args);
3236
3237 /* The rules for returning in memory are the same as for passing the
3238 first named argument by reference. */
3239 memset (&args, 0, sizeof args);
3240 function_arg_info arg (const_cast<tree> (type), /*named=*/true);
3241 return riscv_pass_by_reference (cum, arg);
3242 }
3243
3244 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
3245
3246 static void
riscv_setup_incoming_varargs(cumulative_args_t cum,const function_arg_info & arg,int * pretend_size ATTRIBUTE_UNUSED,int no_rtl)3247 riscv_setup_incoming_varargs (cumulative_args_t cum,
3248 const function_arg_info &arg,
3249 int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
3250 {
3251 CUMULATIVE_ARGS local_cum;
3252 int gp_saved;
3253
3254 /* The caller has advanced CUM up to, but not beyond, the last named
3255 argument. Advance a local copy of CUM past the last "real" named
3256 argument, to find out how many registers are left over. */
3257 local_cum = *get_cumulative_args (cum);
3258 riscv_function_arg_advance (pack_cumulative_args (&local_cum), arg);
3259
3260 /* Found out how many registers we need to save. */
3261 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3262
3263 if (!no_rtl && gp_saved > 0)
3264 {
3265 rtx ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
3266 REG_PARM_STACK_SPACE (cfun->decl)
3267 - gp_saved * UNITS_PER_WORD);
3268 rtx mem = gen_frame_mem (BLKmode, ptr);
3269 set_mem_alias_set (mem, get_varargs_alias_set ());
3270
3271 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3272 mem, gp_saved);
3273 }
3274 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
3275 cfun->machine->varargs_size = gp_saved * UNITS_PER_WORD;
3276 }
3277
3278 /* Handle an attribute requiring a FUNCTION_DECL;
3279 arguments as in struct attribute_spec.handler. */
3280 static tree
riscv_handle_fndecl_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)3281 riscv_handle_fndecl_attribute (tree *node, tree name,
3282 tree args ATTRIBUTE_UNUSED,
3283 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
3284 {
3285 if (TREE_CODE (*node) != FUNCTION_DECL)
3286 {
3287 warning (OPT_Wattributes, "%qE attribute only applies to functions",
3288 name);
3289 *no_add_attrs = true;
3290 }
3291
3292 return NULL_TREE;
3293 }
3294
3295 /* Verify type based attributes. NODE is the what the attribute is being
3296 applied to. NAME is the attribute name. ARGS are the attribute args.
3297 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if
3298 the attribute should be ignored. */
3299
3300 static tree
riscv_handle_type_attribute(tree * node ATTRIBUTE_UNUSED,tree name,tree args,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)3301 riscv_handle_type_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args,
3302 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
3303 {
3304 /* Check for an argument. */
3305 if (is_attribute_p ("interrupt", name))
3306 {
3307 if (args)
3308 {
3309 tree cst = TREE_VALUE (args);
3310 const char *string;
3311
3312 if (TREE_CODE (cst) != STRING_CST)
3313 {
3314 warning (OPT_Wattributes,
3315 "%qE attribute requires a string argument",
3316 name);
3317 *no_add_attrs = true;
3318 return NULL_TREE;
3319 }
3320
3321 string = TREE_STRING_POINTER (cst);
3322 if (strcmp (string, "user") && strcmp (string, "supervisor")
3323 && strcmp (string, "machine"))
3324 {
3325 warning (OPT_Wattributes,
3326 "argument to %qE attribute is not %<\"user\"%>, %<\"supervisor\"%>, "
3327 "or %<\"machine\"%>", name);
3328 *no_add_attrs = true;
3329 }
3330 }
3331 }
3332
3333 return NULL_TREE;
3334 }
3335
3336 /* Return true if function TYPE is an interrupt function. */
3337 static bool
riscv_interrupt_type_p(tree type)3338 riscv_interrupt_type_p (tree type)
3339 {
3340 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
3341 }
3342
3343 /* Return true if FUNC is a naked function. */
3344 static bool
riscv_naked_function_p(tree func)3345 riscv_naked_function_p (tree func)
3346 {
3347 tree func_decl = func;
3348 if (func == NULL_TREE)
3349 func_decl = current_function_decl;
3350 return NULL_TREE != lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl));
3351 }
3352
3353 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */
3354 static bool
riscv_allocate_stack_slots_for_args()3355 riscv_allocate_stack_slots_for_args ()
3356 {
3357 /* Naked functions should not allocate stack slots for arguments. */
3358 return !riscv_naked_function_p (current_function_decl);
3359 }
3360
3361 /* Implement TARGET_WARN_FUNC_RETURN. */
3362 static bool
riscv_warn_func_return(tree decl)3363 riscv_warn_func_return (tree decl)
3364 {
3365 /* Naked functions are implemented entirely in assembly, including the
3366 return sequence, so suppress warnings about this. */
3367 return !riscv_naked_function_p (decl);
3368 }
3369
3370 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
3371
3372 static void
riscv_va_start(tree valist,rtx nextarg)3373 riscv_va_start (tree valist, rtx nextarg)
3374 {
3375 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
3376 std_expand_builtin_va_start (valist, nextarg);
3377 }
3378
3379 /* Make ADDR suitable for use as a call or sibcall target. */
3380
3381 rtx
riscv_legitimize_call_address(rtx addr)3382 riscv_legitimize_call_address (rtx addr)
3383 {
3384 if (!call_insn_operand (addr, VOIDmode))
3385 {
3386 rtx reg = RISCV_CALL_ADDRESS_TEMP (Pmode);
3387 riscv_emit_move (reg, addr);
3388 return reg;
3389 }
3390 return addr;
3391 }
3392
3393 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3394 Assume that the areas do not overlap. */
3395
3396 static void
riscv_block_move_straight(rtx dest,rtx src,unsigned HOST_WIDE_INT length)3397 riscv_block_move_straight (rtx dest, rtx src, unsigned HOST_WIDE_INT length)
3398 {
3399 unsigned HOST_WIDE_INT offset, delta;
3400 unsigned HOST_WIDE_INT bits;
3401 int i;
3402 enum machine_mode mode;
3403 rtx *regs;
3404
3405 bits = MAX (BITS_PER_UNIT,
3406 MIN (BITS_PER_WORD, MIN (MEM_ALIGN (src), MEM_ALIGN (dest))));
3407
3408 mode = mode_for_size (bits, MODE_INT, 0).require ();
3409 delta = bits / BITS_PER_UNIT;
3410
3411 /* Allocate a buffer for the temporary registers. */
3412 regs = XALLOCAVEC (rtx, length / delta);
3413
3414 /* Load as many BITS-sized chunks as possible. Use a normal load if
3415 the source has enough alignment, otherwise use left/right pairs. */
3416 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3417 {
3418 regs[i] = gen_reg_rtx (mode);
3419 riscv_emit_move (regs[i], adjust_address (src, mode, offset));
3420 }
3421
3422 /* Copy the chunks to the destination. */
3423 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3424 riscv_emit_move (adjust_address (dest, mode, offset), regs[i]);
3425
3426 /* Mop up any left-over bytes. */
3427 if (offset < length)
3428 {
3429 src = adjust_address (src, BLKmode, offset);
3430 dest = adjust_address (dest, BLKmode, offset);
3431 move_by_pieces (dest, src, length - offset,
3432 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), RETURN_BEGIN);
3433 }
3434 }
3435
3436 /* Helper function for doing a loop-based block operation on memory
3437 reference MEM. Each iteration of the loop will operate on LENGTH
3438 bytes of MEM.
3439
3440 Create a new base register for use within the loop and point it to
3441 the start of MEM. Create a new memory reference that uses this
3442 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3443
3444 static void
riscv_adjust_block_mem(rtx mem,unsigned HOST_WIDE_INT length,rtx * loop_reg,rtx * loop_mem)3445 riscv_adjust_block_mem (rtx mem, unsigned HOST_WIDE_INT length,
3446 rtx *loop_reg, rtx *loop_mem)
3447 {
3448 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3449
3450 /* Although the new mem does not refer to a known location,
3451 it does keep up to LENGTH bytes of alignment. */
3452 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3453 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3454 }
3455
3456 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
3457 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
3458 the memory regions do not overlap. */
3459
3460 static void
riscv_block_move_loop(rtx dest,rtx src,unsigned HOST_WIDE_INT length,unsigned HOST_WIDE_INT bytes_per_iter)3461 riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length,
3462 unsigned HOST_WIDE_INT bytes_per_iter)
3463 {
3464 rtx label, src_reg, dest_reg, final_src, test;
3465 unsigned HOST_WIDE_INT leftover;
3466
3467 leftover = length % bytes_per_iter;
3468 length -= leftover;
3469
3470 /* Create registers and memory references for use within the loop. */
3471 riscv_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
3472 riscv_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
3473
3474 /* Calculate the value that SRC_REG should have after the last iteration
3475 of the loop. */
3476 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3477 0, 0, OPTAB_WIDEN);
3478
3479 /* Emit the start of the loop. */
3480 label = gen_label_rtx ();
3481 emit_label (label);
3482
3483 /* Emit the loop body. */
3484 riscv_block_move_straight (dest, src, bytes_per_iter);
3485
3486 /* Move on to the next block. */
3487 riscv_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
3488 riscv_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
3489
3490 /* Emit the loop condition. */
3491 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
3492 emit_jump_insn (gen_cbranch4 (Pmode, test, src_reg, final_src, label));
3493
3494 /* Mop up any left-over bytes. */
3495 if (leftover)
3496 riscv_block_move_straight (dest, src, leftover);
3497 else
3498 emit_insn(gen_nop ());
3499 }
3500
3501 /* Expand a cpymemsi instruction, which copies LENGTH bytes from
3502 memory reference SRC to memory reference DEST. */
3503
3504 bool
riscv_expand_block_move(rtx dest,rtx src,rtx length)3505 riscv_expand_block_move (rtx dest, rtx src, rtx length)
3506 {
3507 if (CONST_INT_P (length))
3508 {
3509 unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
3510 unsigned HOST_WIDE_INT factor, align;
3511
3512 align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD);
3513 factor = BITS_PER_WORD / align;
3514
3515 if (optimize_function_for_size_p (cfun)
3516 && hwi_length * factor * UNITS_PER_WORD > MOVE_RATIO (false))
3517 return false;
3518
3519 if (hwi_length <= (RISCV_MAX_MOVE_BYTES_STRAIGHT / factor))
3520 {
3521 riscv_block_move_straight (dest, src, INTVAL (length));
3522 return true;
3523 }
3524 else if (optimize && align >= BITS_PER_WORD)
3525 {
3526 unsigned min_iter_words
3527 = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD;
3528 unsigned iter_words = min_iter_words;
3529 unsigned HOST_WIDE_INT bytes = hwi_length;
3530 unsigned HOST_WIDE_INT words = bytes / UNITS_PER_WORD;
3531
3532 /* Lengthen the loop body if it shortens the tail. */
3533 for (unsigned i = min_iter_words; i < min_iter_words * 2 - 1; i++)
3534 {
3535 unsigned cur_cost = iter_words + words % iter_words;
3536 unsigned new_cost = i + words % i;
3537 if (new_cost <= cur_cost)
3538 iter_words = i;
3539 }
3540
3541 riscv_block_move_loop (dest, src, bytes, iter_words * UNITS_PER_WORD);
3542 return true;
3543 }
3544 }
3545 return false;
3546 }
3547
3548 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
3549 in context CONTEXT. HI_RELOC indicates a high-part reloc. */
3550
3551 static void
riscv_print_operand_reloc(FILE * file,rtx op,bool hi_reloc)3552 riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc)
3553 {
3554 const char *reloc;
3555
3556 switch (riscv_classify_symbolic_expression (op))
3557 {
3558 case SYMBOL_ABSOLUTE:
3559 reloc = hi_reloc ? "%hi" : "%lo";
3560 break;
3561
3562 case SYMBOL_PCREL:
3563 reloc = hi_reloc ? "%pcrel_hi" : "%pcrel_lo";
3564 break;
3565
3566 case SYMBOL_TLS_LE:
3567 reloc = hi_reloc ? "%tprel_hi" : "%tprel_lo";
3568 break;
3569
3570 default:
3571 output_operand_lossage ("invalid use of '%%%c'", hi_reloc ? 'h' : 'R');
3572 return;
3573 }
3574
3575 fprintf (file, "%s(", reloc);
3576 output_addr_const (file, riscv_strip_unspec_address (op));
3577 fputc (')', file);
3578 }
3579
3580 /* Return true if the .AQ suffix should be added to an AMO to implement the
3581 acquire portion of memory model MODEL. */
3582
3583 static bool
riscv_memmodel_needs_amo_acquire(enum memmodel model)3584 riscv_memmodel_needs_amo_acquire (enum memmodel model)
3585 {
3586 switch (model)
3587 {
3588 case MEMMODEL_ACQ_REL:
3589 case MEMMODEL_SEQ_CST:
3590 case MEMMODEL_SYNC_SEQ_CST:
3591 case MEMMODEL_ACQUIRE:
3592 case MEMMODEL_CONSUME:
3593 case MEMMODEL_SYNC_ACQUIRE:
3594 return true;
3595
3596 case MEMMODEL_RELEASE:
3597 case MEMMODEL_SYNC_RELEASE:
3598 case MEMMODEL_RELAXED:
3599 return false;
3600
3601 default:
3602 gcc_unreachable ();
3603 }
3604 }
3605
3606 /* Return true if a FENCE should be emitted to before a memory access to
3607 implement the release portion of memory model MODEL. */
3608
3609 static bool
riscv_memmodel_needs_release_fence(enum memmodel model)3610 riscv_memmodel_needs_release_fence (enum memmodel model)
3611 {
3612 switch (model)
3613 {
3614 case MEMMODEL_ACQ_REL:
3615 case MEMMODEL_SEQ_CST:
3616 case MEMMODEL_SYNC_SEQ_CST:
3617 case MEMMODEL_RELEASE:
3618 case MEMMODEL_SYNC_RELEASE:
3619 return true;
3620
3621 case MEMMODEL_ACQUIRE:
3622 case MEMMODEL_CONSUME:
3623 case MEMMODEL_SYNC_ACQUIRE:
3624 case MEMMODEL_RELAXED:
3625 return false;
3626
3627 default:
3628 gcc_unreachable ();
3629 }
3630 }
3631
3632 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
3633
3634 'h' Print the high-part relocation associated with OP, after stripping
3635 any outermost HIGH.
3636 'R' Print the low-part relocation associated with OP.
3637 'C' Print the integer branch condition for comparison OP.
3638 'A' Print the atomic operation suffix for memory model OP.
3639 'F' Print a FENCE if the memory model requires a release.
3640 'z' Print x0 if OP is zero, otherwise print OP normally.
3641 'i' Print i if the operand is not a register.
3642 'S' Print shift-index of single-bit mask OP.
3643 'T' Print shift-index of inverted single-bit mask OP. */
3644
3645 static void
riscv_print_operand(FILE * file,rtx op,int letter)3646 riscv_print_operand (FILE *file, rtx op, int letter)
3647 {
3648 machine_mode mode = GET_MODE (op);
3649 enum rtx_code code = GET_CODE (op);
3650
3651 switch (letter)
3652 {
3653 case 'h':
3654 if (code == HIGH)
3655 op = XEXP (op, 0);
3656 riscv_print_operand_reloc (file, op, true);
3657 break;
3658
3659 case 'R':
3660 riscv_print_operand_reloc (file, op, false);
3661 break;
3662
3663 case 'C':
3664 /* The RTL names match the instruction names. */
3665 fputs (GET_RTX_NAME (code), file);
3666 break;
3667
3668 case 'A':
3669 if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)))
3670 fputs (".aq", file);
3671 break;
3672
3673 case 'F':
3674 if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
3675 fputs ("fence iorw,ow; ", file);
3676 break;
3677
3678 case 'i':
3679 if (code != REG)
3680 fputs ("i", file);
3681 break;
3682
3683 case 'S':
3684 {
3685 rtx newop = GEN_INT (ctz_hwi (INTVAL (op)));
3686 output_addr_const (file, newop);
3687 break;
3688 }
3689 case 'T':
3690 {
3691 rtx newop = GEN_INT (ctz_hwi (~INTVAL (op)));
3692 output_addr_const (file, newop);
3693 break;
3694 }
3695 default:
3696 switch (code)
3697 {
3698 case REG:
3699 if (letter && letter != 'z')
3700 output_operand_lossage ("invalid use of '%%%c'", letter);
3701 fprintf (file, "%s", reg_names[REGNO (op)]);
3702 break;
3703
3704 case MEM:
3705 if (letter && letter != 'z')
3706 output_operand_lossage ("invalid use of '%%%c'", letter);
3707 else
3708 output_address (mode, XEXP (op, 0));
3709 break;
3710
3711 default:
3712 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
3713 fputs (reg_names[GP_REG_FIRST], file);
3714 else if (letter && letter != 'z')
3715 output_operand_lossage ("invalid use of '%%%c'", letter);
3716 else
3717 output_addr_const (file, riscv_strip_unspec_address (op));
3718 break;
3719 }
3720 }
3721 }
3722
3723 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
3724
3725 static void
riscv_print_operand_address(FILE * file,machine_mode mode ATTRIBUTE_UNUSED,rtx x)3726 riscv_print_operand_address (FILE *file, machine_mode mode ATTRIBUTE_UNUSED, rtx x)
3727 {
3728 struct riscv_address_info addr;
3729
3730 if (riscv_classify_address (&addr, x, word_mode, true))
3731 switch (addr.type)
3732 {
3733 case ADDRESS_REG:
3734 riscv_print_operand (file, addr.offset, 0);
3735 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
3736 return;
3737
3738 case ADDRESS_LO_SUM:
3739 riscv_print_operand_reloc (file, addr.offset, false);
3740 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
3741 return;
3742
3743 case ADDRESS_CONST_INT:
3744 output_addr_const (file, x);
3745 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
3746 return;
3747
3748 case ADDRESS_SYMBOLIC:
3749 output_addr_const (file, riscv_strip_unspec_address (x));
3750 return;
3751 }
3752 gcc_unreachable ();
3753 }
3754
3755 static bool
riscv_size_ok_for_small_data_p(int size)3756 riscv_size_ok_for_small_data_p (int size)
3757 {
3758 return g_switch_value && IN_RANGE (size, 1, g_switch_value);
3759 }
3760
3761 /* Return true if EXP should be placed in the small data section. */
3762
3763 static bool
riscv_in_small_data_p(const_tree x)3764 riscv_in_small_data_p (const_tree x)
3765 {
3766 if (TREE_CODE (x) == STRING_CST || TREE_CODE (x) == FUNCTION_DECL)
3767 return false;
3768
3769 if (TREE_CODE (x) == VAR_DECL && DECL_SECTION_NAME (x))
3770 {
3771 const char *sec = DECL_SECTION_NAME (x);
3772 return strcmp (sec, ".sdata") == 0 || strcmp (sec, ".sbss") == 0;
3773 }
3774
3775 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x)));
3776 }
3777
3778 /* Switch to the appropriate section for output of DECL. */
3779
3780 static section *
riscv_select_section(tree decl,int reloc,unsigned HOST_WIDE_INT align)3781 riscv_select_section (tree decl, int reloc,
3782 unsigned HOST_WIDE_INT align)
3783 {
3784 switch (categorize_decl_for_section (decl, reloc))
3785 {
3786 case SECCAT_SRODATA:
3787 return get_named_section (decl, ".srodata", reloc);
3788
3789 default:
3790 return default_elf_select_section (decl, reloc, align);
3791 }
3792 }
3793
3794 /* Switch to the appropriate section for output of DECL. */
3795
3796 static void
riscv_unique_section(tree decl,int reloc)3797 riscv_unique_section (tree decl, int reloc)
3798 {
3799 const char *prefix = NULL;
3800 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3801
3802 switch (categorize_decl_for_section (decl, reloc))
3803 {
3804 case SECCAT_SRODATA:
3805 prefix = one_only ? ".sr" : ".srodata";
3806 break;
3807
3808 default:
3809 break;
3810 }
3811 if (prefix)
3812 {
3813 const char *name, *linkonce;
3814 char *string;
3815
3816 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3817 name = targetm.strip_name_encoding (name);
3818
3819 /* If we're using one_only, then there needs to be a .gnu.linkonce
3820 prefix to the section name. */
3821 linkonce = one_only ? ".gnu.linkonce" : "";
3822
3823 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
3824
3825 set_decl_section_name (decl, string);
3826 return;
3827 }
3828 default_unique_section (decl, reloc);
3829 }
3830
3831 /* Return a section for X, handling small data. */
3832
3833 static section *
riscv_elf_select_rtx_section(machine_mode mode,rtx x,unsigned HOST_WIDE_INT align)3834 riscv_elf_select_rtx_section (machine_mode mode, rtx x,
3835 unsigned HOST_WIDE_INT align)
3836 {
3837 section *s = default_elf_select_rtx_section (mode, x, align);
3838
3839 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode)))
3840 {
3841 if (startswith (s->named.name, ".rodata.cst"))
3842 {
3843 /* Rename .rodata.cst* to .srodata.cst*. */
3844 char *name = (char *) alloca (strlen (s->named.name) + 2);
3845 sprintf (name, ".s%s", s->named.name + 1);
3846 return get_section (name, s->named.common.flags, NULL);
3847 }
3848
3849 if (s == data_section)
3850 return sdata_section;
3851 }
3852
3853 return s;
3854 }
3855
3856 /* Make the last instruction frame-related and note that it performs
3857 the operation described by FRAME_PATTERN. */
3858
3859 static void
riscv_set_frame_expr(rtx frame_pattern)3860 riscv_set_frame_expr (rtx frame_pattern)
3861 {
3862 rtx insn;
3863
3864 insn = get_last_insn ();
3865 RTX_FRAME_RELATED_P (insn) = 1;
3866 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3867 frame_pattern,
3868 REG_NOTES (insn));
3869 }
3870
3871 /* Return a frame-related rtx that stores REG at MEM.
3872 REG must be a single register. */
3873
3874 static rtx
riscv_frame_set(rtx mem,rtx reg)3875 riscv_frame_set (rtx mem, rtx reg)
3876 {
3877 rtx set = gen_rtx_SET (mem, reg);
3878 RTX_FRAME_RELATED_P (set) = 1;
3879 return set;
3880 }
3881
3882 /* Return true if the current function must save register REGNO. */
3883
3884 static bool
riscv_save_reg_p(unsigned int regno)3885 riscv_save_reg_p (unsigned int regno)
3886 {
3887 bool call_saved = !global_regs[regno] && !call_used_or_fixed_reg_p (regno);
3888 bool might_clobber = crtl->saves_all_registers
3889 || df_regs_ever_live_p (regno);
3890
3891 if (call_saved && might_clobber)
3892 return true;
3893
3894 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
3895 return true;
3896
3897 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
3898 return true;
3899
3900 /* If this is an interrupt handler, then must save extra registers. */
3901 if (cfun->machine->interrupt_handler_p)
3902 {
3903 /* zero register is always zero. */
3904 if (regno == GP_REG_FIRST)
3905 return false;
3906
3907 /* The function will return the stack pointer to its original value. */
3908 if (regno == STACK_POINTER_REGNUM)
3909 return false;
3910
3911 /* By convention, we assume that gp and tp are safe. */
3912 if (regno == GP_REGNUM || regno == THREAD_POINTER_REGNUM)
3913 return false;
3914
3915 /* We must save every register used in this function. If this is not a
3916 leaf function, then we must save all temporary registers. */
3917 if (df_regs_ever_live_p (regno)
3918 || (!crtl->is_leaf && call_used_or_fixed_reg_p (regno)))
3919 return true;
3920 }
3921
3922 return false;
3923 }
3924
3925 /* Determine whether to call GPR save/restore routines. */
3926 static bool
riscv_use_save_libcall(const struct riscv_frame_info * frame)3927 riscv_use_save_libcall (const struct riscv_frame_info *frame)
3928 {
3929 if (!TARGET_SAVE_RESTORE || crtl->calls_eh_return || frame_pointer_needed
3930 || cfun->machine->interrupt_handler_p)
3931 return false;
3932
3933 return frame->save_libcall_adjustment != 0;
3934 }
3935
3936 /* Determine which GPR save/restore routine to call. */
3937
3938 static unsigned
riscv_save_libcall_count(unsigned mask)3939 riscv_save_libcall_count (unsigned mask)
3940 {
3941 for (unsigned n = GP_REG_LAST; n > GP_REG_FIRST; n--)
3942 if (BITSET_P (mask, n))
3943 return CALLEE_SAVED_REG_NUMBER (n) + 1;
3944 abort ();
3945 }
3946
3947 /* Populate the current function's riscv_frame_info structure.
3948
3949 RISC-V stack frames grown downward. High addresses are at the top.
3950
3951 +-------------------------------+
3952 | |
3953 | incoming stack arguments |
3954 | |
3955 +-------------------------------+ <-- incoming stack pointer
3956 | |
3957 | callee-allocated save area |
3958 | for arguments that are |
3959 | split between registers and |
3960 | the stack |
3961 | |
3962 +-------------------------------+ <-- arg_pointer_rtx
3963 | |
3964 | callee-allocated save area |
3965 | for register varargs |
3966 | |
3967 +-------------------------------+ <-- hard_frame_pointer_rtx;
3968 | | stack_pointer_rtx + gp_sp_offset
3969 | GPR save area | + UNITS_PER_WORD
3970 | |
3971 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
3972 | | + UNITS_PER_HWVALUE
3973 | FPR save area |
3974 | |
3975 +-------------------------------+ <-- frame_pointer_rtx (virtual)
3976 | |
3977 | local variables |
3978 | |
3979 P +-------------------------------+
3980 | |
3981 | outgoing stack arguments |
3982 | |
3983 +-------------------------------+ <-- stack_pointer_rtx
3984
3985 Dynamic stack allocations such as alloca insert data at point P.
3986 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
3987 hard_frame_pointer_rtx unchanged. */
3988
3989 static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame);
3990
3991 static void
riscv_compute_frame_info(void)3992 riscv_compute_frame_info (void)
3993 {
3994 struct riscv_frame_info *frame;
3995 HOST_WIDE_INT offset;
3996 bool interrupt_save_prologue_temp = false;
3997 unsigned int regno, i, num_x_saved = 0, num_f_saved = 0;
3998
3999 frame = &cfun->machine->frame;
4000
4001 /* In an interrupt function, if we have a large frame, then we need to
4002 save/restore t0. We check for this before clearing the frame struct. */
4003 if (cfun->machine->interrupt_handler_p)
4004 {
4005 HOST_WIDE_INT step1 = riscv_first_stack_step (frame);
4006 if (! SMALL_OPERAND (frame->total_size - step1))
4007 interrupt_save_prologue_temp = true;
4008 }
4009
4010 memset (frame, 0, sizeof (*frame));
4011
4012 if (!cfun->machine->naked_p)
4013 {
4014 /* Find out which GPRs we need to save. */
4015 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
4016 if (riscv_save_reg_p (regno)
4017 || (interrupt_save_prologue_temp
4018 && (regno == RISCV_PROLOGUE_TEMP_REGNUM)))
4019 frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
4020
4021 /* If this function calls eh_return, we must also save and restore the
4022 EH data registers. */
4023 if (crtl->calls_eh_return)
4024 for (i = 0; (regno = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++)
4025 frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
4026
4027 /* Find out which FPRs we need to save. This loop must iterate over
4028 the same space as its companion in riscv_for_each_saved_reg. */
4029 if (TARGET_HARD_FLOAT)
4030 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
4031 if (riscv_save_reg_p (regno))
4032 frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++;
4033 }
4034
4035 /* At the bottom of the frame are any outgoing stack arguments. */
4036 offset = RISCV_STACK_ALIGN (crtl->outgoing_args_size);
4037 /* Next are local stack variables. */
4038 offset += RISCV_STACK_ALIGN (get_frame_size ());
4039 /* The virtual frame pointer points above the local variables. */
4040 frame->frame_pointer_offset = offset;
4041 /* Next are the callee-saved FPRs. */
4042 if (frame->fmask)
4043 offset += RISCV_STACK_ALIGN (num_f_saved * UNITS_PER_FP_REG);
4044 frame->fp_sp_offset = offset - UNITS_PER_FP_REG;
4045 /* Next are the callee-saved GPRs. */
4046 if (frame->mask)
4047 {
4048 unsigned x_save_size = RISCV_STACK_ALIGN (num_x_saved * UNITS_PER_WORD);
4049 unsigned num_save_restore = 1 + riscv_save_libcall_count (frame->mask);
4050
4051 /* Only use save/restore routines if they don't alter the stack size. */
4052 if (RISCV_STACK_ALIGN (num_save_restore * UNITS_PER_WORD) == x_save_size)
4053 {
4054 /* Libcall saves/restores 3 registers at once, so we need to
4055 allocate 12 bytes for callee-saved register. */
4056 if (TARGET_RVE)
4057 x_save_size = 3 * UNITS_PER_WORD;
4058
4059 frame->save_libcall_adjustment = x_save_size;
4060 }
4061
4062 offset += x_save_size;
4063 }
4064 frame->gp_sp_offset = offset - UNITS_PER_WORD;
4065 /* The hard frame pointer points above the callee-saved GPRs. */
4066 frame->hard_frame_pointer_offset = offset;
4067 /* Above the hard frame pointer is the callee-allocated varags save area. */
4068 offset += RISCV_STACK_ALIGN (cfun->machine->varargs_size);
4069 /* Next is the callee-allocated area for pretend stack arguments. */
4070 offset += RISCV_STACK_ALIGN (crtl->args.pretend_args_size);
4071 /* Arg pointer must be below pretend args, but must be above alignment
4072 padding. */
4073 frame->arg_pointer_offset = offset - crtl->args.pretend_args_size;
4074 frame->total_size = offset;
4075 /* Next points the incoming stack pointer and any incoming arguments. */
4076
4077 /* Only use save/restore routines when the GPRs are atop the frame. */
4078 if (frame->hard_frame_pointer_offset != frame->total_size)
4079 frame->save_libcall_adjustment = 0;
4080 }
4081
4082 /* Make sure that we're not trying to eliminate to the wrong hard frame
4083 pointer. */
4084
4085 static bool
riscv_can_eliminate(const int from ATTRIBUTE_UNUSED,const int to)4086 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
4087 {
4088 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
4089 }
4090
4091 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
4092 or argument pointer. TO is either the stack pointer or hard frame
4093 pointer. */
4094
4095 HOST_WIDE_INT
riscv_initial_elimination_offset(int from,int to)4096 riscv_initial_elimination_offset (int from, int to)
4097 {
4098 HOST_WIDE_INT src, dest;
4099
4100 riscv_compute_frame_info ();
4101
4102 if (to == HARD_FRAME_POINTER_REGNUM)
4103 dest = cfun->machine->frame.hard_frame_pointer_offset;
4104 else if (to == STACK_POINTER_REGNUM)
4105 dest = 0; /* The stack pointer is the base of all offsets, hence 0. */
4106 else
4107 gcc_unreachable ();
4108
4109 if (from == FRAME_POINTER_REGNUM)
4110 src = cfun->machine->frame.frame_pointer_offset;
4111 else if (from == ARG_POINTER_REGNUM)
4112 src = cfun->machine->frame.arg_pointer_offset;
4113 else
4114 gcc_unreachable ();
4115
4116 return src - dest;
4117 }
4118
4119 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
4120 previous frame. */
4121
4122 rtx
riscv_return_addr(int count,rtx frame ATTRIBUTE_UNUSED)4123 riscv_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
4124 {
4125 if (count != 0)
4126 return const0_rtx;
4127
4128 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
4129 }
4130
4131 /* Emit code to change the current function's return address to
4132 ADDRESS. SCRATCH is available as a scratch register, if needed.
4133 ADDRESS and SCRATCH are both word-mode GPRs. */
4134
4135 void
riscv_set_return_address(rtx address,rtx scratch)4136 riscv_set_return_address (rtx address, rtx scratch)
4137 {
4138 rtx slot_address;
4139
4140 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
4141 slot_address = riscv_add_offset (scratch, stack_pointer_rtx,
4142 cfun->machine->frame.gp_sp_offset);
4143 riscv_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
4144 }
4145
4146 /* A function to save or store a register. The first argument is the
4147 register and the second is the stack slot. */
4148 typedef void (*riscv_save_restore_fn) (rtx, rtx);
4149
4150 /* Use FN to save or restore register REGNO. MODE is the register's
4151 mode and OFFSET is the offset of its save slot from the current
4152 stack pointer. */
4153
4154 static void
riscv_save_restore_reg(machine_mode mode,int regno,HOST_WIDE_INT offset,riscv_save_restore_fn fn)4155 riscv_save_restore_reg (machine_mode mode, int regno,
4156 HOST_WIDE_INT offset, riscv_save_restore_fn fn)
4157 {
4158 rtx mem;
4159
4160 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx, offset));
4161 fn (gen_rtx_REG (mode, regno), mem);
4162 }
4163
4164 /* Call FN for each register that is saved by the current function.
4165 SP_OFFSET is the offset of the current stack pointer from the start
4166 of the frame. */
4167
4168 static void
riscv_for_each_saved_reg(HOST_WIDE_INT sp_offset,riscv_save_restore_fn fn,bool epilogue,bool maybe_eh_return)4169 riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset, riscv_save_restore_fn fn,
4170 bool epilogue, bool maybe_eh_return)
4171 {
4172 HOST_WIDE_INT offset;
4173
4174 /* Save the link register and s-registers. */
4175 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
4176 for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
4177 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
4178 {
4179 bool handle_reg = TRUE;
4180
4181 /* If this is a normal return in a function that calls the eh_return
4182 builtin, then do not restore the eh return data registers as that
4183 would clobber the return value. But we do still need to save them
4184 in the prologue, and restore them for an exception return, so we
4185 need special handling here. */
4186 if (epilogue && !maybe_eh_return && crtl->calls_eh_return)
4187 {
4188 unsigned int i, regnum;
4189
4190 for (i = 0; (regnum = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM;
4191 i++)
4192 if (regno == regnum)
4193 {
4194 handle_reg = FALSE;
4195 break;
4196 }
4197 }
4198
4199 if (handle_reg)
4200 riscv_save_restore_reg (word_mode, regno, offset, fn);
4201 offset -= UNITS_PER_WORD;
4202 }
4203
4204 /* This loop must iterate over the same space as its companion in
4205 riscv_compute_frame_info. */
4206 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
4207 for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
4208 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
4209 {
4210 machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode;
4211
4212 riscv_save_restore_reg (mode, regno, offset, fn);
4213 offset -= GET_MODE_SIZE (mode);
4214 }
4215 }
4216
4217 /* Save register REG to MEM. Make the instruction frame-related. */
4218
4219 static void
riscv_save_reg(rtx reg,rtx mem)4220 riscv_save_reg (rtx reg, rtx mem)
4221 {
4222 riscv_emit_move (mem, reg);
4223 riscv_set_frame_expr (riscv_frame_set (mem, reg));
4224 }
4225
4226 /* Restore register REG from MEM. */
4227
4228 static void
riscv_restore_reg(rtx reg,rtx mem)4229 riscv_restore_reg (rtx reg, rtx mem)
4230 {
4231 rtx insn = riscv_emit_move (reg, mem);
4232 rtx dwarf = NULL_RTX;
4233 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
4234
4235 if (epilogue_cfa_sp_offset && REGNO (reg) == HARD_FRAME_POINTER_REGNUM)
4236 {
4237 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
4238 GEN_INT (epilogue_cfa_sp_offset));
4239 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
4240 }
4241
4242 REG_NOTES (insn) = dwarf;
4243 RTX_FRAME_RELATED_P (insn) = 1;
4244 }
4245
4246 /* For stack frames that can't be allocated with a single ADDI instruction,
4247 compute the best value to initially allocate. It must at a minimum
4248 allocate enough space to spill the callee-saved registers. If TARGET_RVC,
4249 try to pick a value that will allow compression of the register saves
4250 without adding extra instructions. */
4251
4252 static HOST_WIDE_INT
riscv_first_stack_step(struct riscv_frame_info * frame)4253 riscv_first_stack_step (struct riscv_frame_info *frame)
4254 {
4255 if (SMALL_OPERAND (frame->total_size))
4256 return frame->total_size;
4257
4258 HOST_WIDE_INT min_first_step =
4259 RISCV_STACK_ALIGN (frame->total_size - frame->fp_sp_offset);
4260 HOST_WIDE_INT max_first_step = IMM_REACH / 2 - PREFERRED_STACK_BOUNDARY / 8;
4261 HOST_WIDE_INT min_second_step = frame->total_size - max_first_step;
4262 gcc_assert (min_first_step <= max_first_step);
4263
4264 /* As an optimization, use the least-significant bits of the total frame
4265 size, so that the second adjustment step is just LUI + ADD. */
4266 if (!SMALL_OPERAND (min_second_step)
4267 && frame->total_size % IMM_REACH < IMM_REACH / 2
4268 && frame->total_size % IMM_REACH >= min_first_step)
4269 return frame->total_size % IMM_REACH;
4270
4271 if (TARGET_RVC)
4272 {
4273 /* If we need two subtracts, and one is small enough to allow compressed
4274 loads and stores, then put that one first. */
4275 if (IN_RANGE (min_second_step, 0,
4276 (TARGET_64BIT ? SDSP_REACH : SWSP_REACH)))
4277 return MAX (min_second_step, min_first_step);
4278
4279 /* If we need LUI + ADDI + ADD for the second adjustment step, then start
4280 with the minimum first step, so that we can get compressed loads and
4281 stores. */
4282 else if (!SMALL_OPERAND (min_second_step))
4283 return min_first_step;
4284 }
4285
4286 return max_first_step;
4287 }
4288
4289 static rtx
riscv_adjust_libcall_cfi_prologue()4290 riscv_adjust_libcall_cfi_prologue ()
4291 {
4292 rtx dwarf = NULL_RTX;
4293 rtx adjust_sp_rtx, reg, mem, insn;
4294 int saved_size = cfun->machine->frame.save_libcall_adjustment;
4295 int offset;
4296
4297 for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
4298 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
4299 {
4300 /* The save order is ra, s0, s1, s2 to s11. */
4301 if (regno == RETURN_ADDR_REGNUM)
4302 offset = saved_size - UNITS_PER_WORD;
4303 else if (regno == S0_REGNUM)
4304 offset = saved_size - UNITS_PER_WORD * 2;
4305 else if (regno == S1_REGNUM)
4306 offset = saved_size - UNITS_PER_WORD * 3;
4307 else
4308 offset = saved_size - ((regno - S2_REGNUM + 4) * UNITS_PER_WORD);
4309
4310 reg = gen_rtx_REG (SImode, regno);
4311 mem = gen_frame_mem (SImode, plus_constant (Pmode,
4312 stack_pointer_rtx,
4313 offset));
4314
4315 insn = gen_rtx_SET (mem, reg);
4316 dwarf = alloc_reg_note (REG_CFA_OFFSET, insn, dwarf);
4317 }
4318
4319 /* Debug info for adjust sp. */
4320 adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx,
4321 stack_pointer_rtx, GEN_INT (-saved_size));
4322 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
4323 dwarf);
4324 return dwarf;
4325 }
4326
4327 static void
riscv_emit_stack_tie(void)4328 riscv_emit_stack_tie (void)
4329 {
4330 if (Pmode == SImode)
4331 emit_insn (gen_stack_tiesi (stack_pointer_rtx, hard_frame_pointer_rtx));
4332 else
4333 emit_insn (gen_stack_tiedi (stack_pointer_rtx, hard_frame_pointer_rtx));
4334 }
4335
4336 /* Expand the "prologue" pattern. */
4337
4338 void
riscv_expand_prologue(void)4339 riscv_expand_prologue (void)
4340 {
4341 struct riscv_frame_info *frame = &cfun->machine->frame;
4342 HOST_WIDE_INT size = frame->total_size;
4343 unsigned mask = frame->mask;
4344 rtx insn;
4345
4346 if (flag_stack_usage_info)
4347 current_function_static_stack_size = size;
4348
4349 if (cfun->machine->naked_p)
4350 return;
4351
4352 /* When optimizing for size, call a subroutine to save the registers. */
4353 if (riscv_use_save_libcall (frame))
4354 {
4355 rtx dwarf = NULL_RTX;
4356 dwarf = riscv_adjust_libcall_cfi_prologue ();
4357
4358 size -= frame->save_libcall_adjustment;
4359 insn = emit_insn (riscv_gen_gpr_save_insn (frame));
4360 frame->mask = 0; /* Temporarily fib that we need not save GPRs. */
4361
4362 RTX_FRAME_RELATED_P (insn) = 1;
4363 REG_NOTES (insn) = dwarf;
4364 }
4365
4366 /* Save the registers. */
4367 if ((frame->mask | frame->fmask) != 0)
4368 {
4369 HOST_WIDE_INT step1 = MIN (size, riscv_first_stack_step (frame));
4370
4371 insn = gen_add3_insn (stack_pointer_rtx,
4372 stack_pointer_rtx,
4373 GEN_INT (-step1));
4374 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
4375 size -= step1;
4376 riscv_for_each_saved_reg (size, riscv_save_reg, false, false);
4377 }
4378
4379 frame->mask = mask; /* Undo the above fib. */
4380
4381 /* Set up the frame pointer, if we're using one. */
4382 if (frame_pointer_needed)
4383 {
4384 insn = gen_add3_insn (hard_frame_pointer_rtx, stack_pointer_rtx,
4385 GEN_INT (frame->hard_frame_pointer_offset - size));
4386 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
4387
4388 riscv_emit_stack_tie ();
4389 }
4390
4391 /* Allocate the rest of the frame. */
4392 if (size > 0)
4393 {
4394 if (SMALL_OPERAND (-size))
4395 {
4396 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
4397 GEN_INT (-size));
4398 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
4399 }
4400 else
4401 {
4402 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (-size));
4403 emit_insn (gen_add3_insn (stack_pointer_rtx,
4404 stack_pointer_rtx,
4405 RISCV_PROLOGUE_TEMP (Pmode)));
4406
4407 /* Describe the effect of the previous instructions. */
4408 insn = plus_constant (Pmode, stack_pointer_rtx, -size);
4409 insn = gen_rtx_SET (stack_pointer_rtx, insn);
4410 riscv_set_frame_expr (insn);
4411 }
4412 }
4413 }
4414
4415 static rtx
riscv_adjust_libcall_cfi_epilogue()4416 riscv_adjust_libcall_cfi_epilogue ()
4417 {
4418 rtx dwarf = NULL_RTX;
4419 rtx adjust_sp_rtx, reg;
4420 int saved_size = cfun->machine->frame.save_libcall_adjustment;
4421
4422 /* Debug info for adjust sp. */
4423 adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx,
4424 stack_pointer_rtx, GEN_INT (saved_size));
4425 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
4426 dwarf);
4427
4428 for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
4429 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
4430 {
4431 reg = gen_rtx_REG (SImode, regno);
4432 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
4433 }
4434
4435 return dwarf;
4436 }
4437
4438 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern;
4439 style says which. */
4440
4441 void
riscv_expand_epilogue(int style)4442 riscv_expand_epilogue (int style)
4443 {
4444 /* Split the frame into two. STEP1 is the amount of stack we should
4445 deallocate before restoring the registers. STEP2 is the amount we
4446 should deallocate afterwards.
4447
4448 Start off by assuming that no registers need to be restored. */
4449 struct riscv_frame_info *frame = &cfun->machine->frame;
4450 unsigned mask = frame->mask;
4451 HOST_WIDE_INT step1 = frame->total_size;
4452 HOST_WIDE_INT step2 = 0;
4453 bool use_restore_libcall = ((style == NORMAL_RETURN)
4454 && riscv_use_save_libcall (frame));
4455 rtx ra = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
4456 rtx insn;
4457
4458 /* We need to add memory barrier to prevent read from deallocated stack. */
4459 bool need_barrier_p = (get_frame_size ()
4460 + cfun->machine->frame.arg_pointer_offset) != 0;
4461
4462 if (cfun->machine->naked_p)
4463 {
4464 gcc_assert (style == NORMAL_RETURN);
4465
4466 emit_jump_insn (gen_return ());
4467
4468 return;
4469 }
4470
4471 if ((style == NORMAL_RETURN) && riscv_can_use_return_insn ())
4472 {
4473 emit_jump_insn (gen_return ());
4474 return;
4475 }
4476
4477 /* Reset the epilogue cfa info before starting to emit the epilogue. */
4478 epilogue_cfa_sp_offset = 0;
4479
4480 /* Move past any dynamic stack allocations. */
4481 if (cfun->calls_alloca)
4482 {
4483 /* Emit a barrier to prevent loads from a deallocated stack. */
4484 riscv_emit_stack_tie ();
4485 need_barrier_p = false;
4486
4487 rtx adjust = GEN_INT (-frame->hard_frame_pointer_offset);
4488 if (!SMALL_OPERAND (INTVAL (adjust)))
4489 {
4490 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
4491 adjust = RISCV_PROLOGUE_TEMP (Pmode);
4492 }
4493
4494 insn = emit_insn (
4495 gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx,
4496 adjust));
4497
4498 rtx dwarf = NULL_RTX;
4499 rtx cfa_adjust_value = gen_rtx_PLUS (
4500 Pmode, hard_frame_pointer_rtx,
4501 GEN_INT (-frame->hard_frame_pointer_offset));
4502 rtx cfa_adjust_rtx = gen_rtx_SET (stack_pointer_rtx, cfa_adjust_value);
4503 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, cfa_adjust_rtx, dwarf);
4504 RTX_FRAME_RELATED_P (insn) = 1;
4505
4506 REG_NOTES (insn) = dwarf;
4507 }
4508
4509 /* If we need to restore registers, deallocate as much stack as
4510 possible in the second step without going out of range. */
4511 if ((frame->mask | frame->fmask) != 0)
4512 {
4513 step2 = riscv_first_stack_step (frame);
4514 step1 -= step2;
4515 }
4516
4517 /* Set TARGET to BASE + STEP1. */
4518 if (step1 > 0)
4519 {
4520 /* Emit a barrier to prevent loads from a deallocated stack. */
4521 riscv_emit_stack_tie ();
4522 need_barrier_p = false;
4523
4524 /* Get an rtx for STEP1 that we can add to BASE. */
4525 rtx adjust = GEN_INT (step1);
4526 if (!SMALL_OPERAND (step1))
4527 {
4528 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
4529 adjust = RISCV_PROLOGUE_TEMP (Pmode);
4530 }
4531
4532 insn = emit_insn (
4533 gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
4534
4535 rtx dwarf = NULL_RTX;
4536 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
4537 GEN_INT (step2));
4538
4539 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
4540 RTX_FRAME_RELATED_P (insn) = 1;
4541
4542 REG_NOTES (insn) = dwarf;
4543 }
4544 else if (frame_pointer_needed)
4545 {
4546 /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring
4547 old value of FP. */
4548 epilogue_cfa_sp_offset = step2;
4549 }
4550
4551 if (use_restore_libcall)
4552 frame->mask = 0; /* Temporarily fib that we need not save GPRs. */
4553
4554 /* Restore the registers. */
4555 riscv_for_each_saved_reg (frame->total_size - step2, riscv_restore_reg,
4556 true, style == EXCEPTION_RETURN);
4557
4558 if (use_restore_libcall)
4559 {
4560 frame->mask = mask; /* Undo the above fib. */
4561 gcc_assert (step2 >= frame->save_libcall_adjustment);
4562 step2 -= frame->save_libcall_adjustment;
4563 }
4564
4565 if (need_barrier_p)
4566 riscv_emit_stack_tie ();
4567
4568 /* Deallocate the final bit of the frame. */
4569 if (step2 > 0)
4570 {
4571 insn = emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
4572 GEN_INT (step2)));
4573
4574 rtx dwarf = NULL_RTX;
4575 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
4576 const0_rtx);
4577 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
4578 RTX_FRAME_RELATED_P (insn) = 1;
4579
4580 REG_NOTES (insn) = dwarf;
4581 }
4582
4583 if (use_restore_libcall)
4584 {
4585 rtx dwarf = riscv_adjust_libcall_cfi_epilogue ();
4586 insn = emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask))));
4587 RTX_FRAME_RELATED_P (insn) = 1;
4588 REG_NOTES (insn) = dwarf;
4589
4590 emit_jump_insn (gen_gpr_restore_return (ra));
4591 return;
4592 }
4593
4594 /* Add in the __builtin_eh_return stack adjustment. */
4595 if ((style == EXCEPTION_RETURN) && crtl->calls_eh_return)
4596 emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
4597 EH_RETURN_STACKADJ_RTX));
4598
4599 /* Return from interrupt. */
4600 if (cfun->machine->interrupt_handler_p)
4601 {
4602 enum riscv_privilege_levels mode = cfun->machine->interrupt_mode;
4603
4604 gcc_assert (mode != UNKNOWN_MODE);
4605
4606 if (mode == MACHINE_MODE)
4607 emit_jump_insn (gen_riscv_mret ());
4608 else if (mode == SUPERVISOR_MODE)
4609 emit_jump_insn (gen_riscv_sret ());
4610 else
4611 emit_jump_insn (gen_riscv_uret ());
4612 }
4613 else if (style != SIBCALL_RETURN)
4614 emit_jump_insn (gen_simple_return_internal (ra));
4615 }
4616
4617 /* Implement EPILOGUE_USES. */
4618
4619 bool
riscv_epilogue_uses(unsigned int regno)4620 riscv_epilogue_uses (unsigned int regno)
4621 {
4622 if (regno == RETURN_ADDR_REGNUM)
4623 return true;
4624
4625 if (epilogue_completed && cfun->machine->interrupt_handler_p)
4626 {
4627 /* An interrupt function restores temp regs, so we must indicate that
4628 they are live at function end. */
4629 if (df_regs_ever_live_p (regno)
4630 || (!crtl->is_leaf && call_used_or_fixed_reg_p (regno)))
4631 return true;
4632 }
4633
4634 return false;
4635 }
4636
4637 /* Return nonzero if this function is known to have a null epilogue.
4638 This allows the optimizer to omit jumps to jumps if no stack
4639 was created. */
4640
4641 bool
riscv_can_use_return_insn(void)4642 riscv_can_use_return_insn (void)
4643 {
4644 return (reload_completed && cfun->machine->frame.total_size == 0
4645 && ! cfun->machine->interrupt_handler_p);
4646 }
4647
4648 /* Given that there exists at least one variable that is set (produced)
4649 by OUT_INSN and read (consumed) by IN_INSN, return true iff
4650 IN_INSN represents one or more memory store operations and none of
4651 the variables set by OUT_INSN is used by IN_INSN as the address of a
4652 store operation. If either IN_INSN or OUT_INSN does not represent
4653 a "single" RTL SET expression (as loosely defined by the
4654 implementation of the single_set function) or a PARALLEL with only
4655 SETs, CLOBBERs, and USEs inside, this function returns false.
4656
4657 Borrowed from rs6000, riscv_store_data_bypass_p checks for certain
4658 conditions that result in assertion failures in the generic
4659 store_data_bypass_p function and returns FALSE in such cases.
4660
4661 This is required to make -msave-restore work with the sifive-7
4662 pipeline description. */
4663
4664 bool
riscv_store_data_bypass_p(rtx_insn * out_insn,rtx_insn * in_insn)4665 riscv_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
4666 {
4667 rtx out_set, in_set;
4668 rtx out_pat, in_pat;
4669 rtx out_exp, in_exp;
4670 int i, j;
4671
4672 in_set = single_set (in_insn);
4673 if (in_set)
4674 {
4675 if (MEM_P (SET_DEST (in_set)))
4676 {
4677 out_set = single_set (out_insn);
4678 if (!out_set)
4679 {
4680 out_pat = PATTERN (out_insn);
4681 if (GET_CODE (out_pat) == PARALLEL)
4682 {
4683 for (i = 0; i < XVECLEN (out_pat, 0); i++)
4684 {
4685 out_exp = XVECEXP (out_pat, 0, i);
4686 if ((GET_CODE (out_exp) == CLOBBER)
4687 || (GET_CODE (out_exp) == USE))
4688 continue;
4689 else if (GET_CODE (out_exp) != SET)
4690 return false;
4691 }
4692 }
4693 }
4694 }
4695 }
4696 else
4697 {
4698 in_pat = PATTERN (in_insn);
4699 if (GET_CODE (in_pat) != PARALLEL)
4700 return false;
4701
4702 for (i = 0; i < XVECLEN (in_pat, 0); i++)
4703 {
4704 in_exp = XVECEXP (in_pat, 0, i);
4705 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
4706 continue;
4707 else if (GET_CODE (in_exp) != SET)
4708 return false;
4709
4710 if (MEM_P (SET_DEST (in_exp)))
4711 {
4712 out_set = single_set (out_insn);
4713 if (!out_set)
4714 {
4715 out_pat = PATTERN (out_insn);
4716 if (GET_CODE (out_pat) != PARALLEL)
4717 return false;
4718 for (j = 0; j < XVECLEN (out_pat, 0); j++)
4719 {
4720 out_exp = XVECEXP (out_pat, 0, j);
4721 if ((GET_CODE (out_exp) == CLOBBER)
4722 || (GET_CODE (out_exp) == USE))
4723 continue;
4724 else if (GET_CODE (out_exp) != SET)
4725 return false;
4726 }
4727 }
4728 }
4729 }
4730 }
4731
4732 return store_data_bypass_p (out_insn, in_insn);
4733 }
4734
4735 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
4736
4737 When floating-point registers are wider than integer ones, moves between
4738 them must go through memory. */
4739
4740 static bool
riscv_secondary_memory_needed(machine_mode mode,reg_class_t class1,reg_class_t class2)4741 riscv_secondary_memory_needed (machine_mode mode, reg_class_t class1,
4742 reg_class_t class2)
4743 {
4744 return (GET_MODE_SIZE (mode) > UNITS_PER_WORD
4745 && (class1 == FP_REGS) != (class2 == FP_REGS));
4746 }
4747
4748 /* Implement TARGET_REGISTER_MOVE_COST. */
4749
4750 static int
riscv_register_move_cost(machine_mode mode,reg_class_t from,reg_class_t to)4751 riscv_register_move_cost (machine_mode mode,
4752 reg_class_t from, reg_class_t to)
4753 {
4754 if ((from == FP_REGS && to == GR_REGS) ||
4755 (from == GR_REGS && to == FP_REGS))
4756 return tune_param->fmv_cost;
4757
4758 return riscv_secondary_memory_needed (mode, from, to) ? 8 : 2;
4759 }
4760
4761 /* Implement TARGET_HARD_REGNO_NREGS. */
4762
4763 static unsigned int
riscv_hard_regno_nregs(unsigned int regno,machine_mode mode)4764 riscv_hard_regno_nregs (unsigned int regno, machine_mode mode)
4765 {
4766 if (FP_REG_P (regno))
4767 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_REG - 1) / UNITS_PER_FP_REG;
4768
4769 /* All other registers are word-sized. */
4770 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4771 }
4772
4773 /* Implement TARGET_HARD_REGNO_MODE_OK. */
4774
4775 static bool
riscv_hard_regno_mode_ok(unsigned int regno,machine_mode mode)4776 riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
4777 {
4778 unsigned int nregs = riscv_hard_regno_nregs (regno, mode);
4779
4780 if (GP_REG_P (regno))
4781 {
4782 if (!GP_REG_P (regno + nregs - 1))
4783 return false;
4784 }
4785 else if (FP_REG_P (regno))
4786 {
4787 if (!FP_REG_P (regno + nregs - 1))
4788 return false;
4789
4790 if (GET_MODE_CLASS (mode) != MODE_FLOAT
4791 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4792 return false;
4793
4794 /* Only use callee-saved registers if a potential callee is guaranteed
4795 to spill the requisite width. */
4796 if (GET_MODE_UNIT_SIZE (mode) > UNITS_PER_FP_REG
4797 || (!call_used_or_fixed_reg_p (regno)
4798 && GET_MODE_UNIT_SIZE (mode) > UNITS_PER_FP_ARG))
4799 return false;
4800 }
4801 else
4802 return false;
4803
4804 /* Require same callee-savedness for all registers. */
4805 for (unsigned i = 1; i < nregs; i++)
4806 if (call_used_or_fixed_reg_p (regno)
4807 != call_used_or_fixed_reg_p (regno + i))
4808 return false;
4809
4810 return true;
4811 }
4812
4813 /* Implement TARGET_MODES_TIEABLE_P.
4814
4815 Don't allow floating-point modes to be tied, since type punning of
4816 single-precision and double-precision is implementation defined. */
4817
4818 static bool
riscv_modes_tieable_p(machine_mode mode1,machine_mode mode2)4819 riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)
4820 {
4821 return (mode1 == mode2
4822 || !(GET_MODE_CLASS (mode1) == MODE_FLOAT
4823 && GET_MODE_CLASS (mode2) == MODE_FLOAT));
4824 }
4825
4826 /* Implement CLASS_MAX_NREGS. */
4827
4828 static unsigned char
riscv_class_max_nregs(reg_class_t rclass,machine_mode mode)4829 riscv_class_max_nregs (reg_class_t rclass, machine_mode mode)
4830 {
4831 if (reg_class_subset_p (rclass, FP_REGS))
4832 return riscv_hard_regno_nregs (FP_REG_FIRST, mode);
4833
4834 if (reg_class_subset_p (rclass, GR_REGS))
4835 return riscv_hard_regno_nregs (GP_REG_FIRST, mode);
4836
4837 return 0;
4838 }
4839
4840 /* Implement TARGET_MEMORY_MOVE_COST. */
4841
4842 static int
riscv_memory_move_cost(machine_mode mode,reg_class_t rclass,bool in)4843 riscv_memory_move_cost (machine_mode mode, reg_class_t rclass, bool in)
4844 {
4845 return (tune_param->memory_cost
4846 + memory_move_secondary_cost (mode, rclass, in));
4847 }
4848
4849 /* Return the number of instructions that can be issued per cycle. */
4850
4851 static int
riscv_issue_rate(void)4852 riscv_issue_rate (void)
4853 {
4854 return tune_param->issue_rate;
4855 }
4856
4857 /* Auxiliary function to emit RISC-V ELF attribute. */
4858 static void
riscv_emit_attribute()4859 riscv_emit_attribute ()
4860 {
4861 fprintf (asm_out_file, "\t.attribute arch, \"%s\"\n",
4862 riscv_arch_str ().c_str ());
4863
4864 fprintf (asm_out_file, "\t.attribute unaligned_access, %d\n",
4865 TARGET_STRICT_ALIGN ? 0 : 1);
4866
4867 fprintf (asm_out_file, "\t.attribute stack_align, %d\n",
4868 riscv_stack_boundary / 8);
4869 }
4870
4871 /* Implement TARGET_ASM_FILE_START. */
4872
4873 static void
riscv_file_start(void)4874 riscv_file_start (void)
4875 {
4876 default_file_start ();
4877
4878 /* Instruct GAS to generate position-[in]dependent code. */
4879 fprintf (asm_out_file, "\t.option %spic\n", (flag_pic ? "" : "no"));
4880
4881 /* If the user specifies "-mno-relax" on the command line then disable linker
4882 relaxation in the assembler. */
4883 if (! riscv_mrelax)
4884 fprintf (asm_out_file, "\t.option norelax\n");
4885
4886 if (riscv_emit_attribute_p)
4887 riscv_emit_attribute ();
4888 }
4889
4890 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
4891 in order to avoid duplicating too much logic from elsewhere. */
4892
4893 static void
riscv_output_mi_thunk(FILE * file,tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset,tree function)4894 riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
4895 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
4896 tree function)
4897 {
4898 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
4899 rtx this_rtx, temp1, temp2, fnaddr;
4900 rtx_insn *insn;
4901
4902 /* Pretend to be a post-reload pass while generating rtl. */
4903 reload_completed = 1;
4904
4905 /* Mark the end of the (empty) prologue. */
4906 emit_note (NOTE_INSN_PROLOGUE_END);
4907
4908 /* Determine if we can use a sibcall to call FUNCTION directly. */
4909 fnaddr = gen_rtx_MEM (FUNCTION_MODE, XEXP (DECL_RTL (function), 0));
4910
4911 /* We need two temporary registers in some cases. */
4912 temp1 = gen_rtx_REG (Pmode, RISCV_PROLOGUE_TEMP_REGNUM);
4913 temp2 = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
4914
4915 /* Find out which register contains the "this" pointer. */
4916 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
4917 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
4918 else
4919 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
4920
4921 /* Add DELTA to THIS_RTX. */
4922 if (delta != 0)
4923 {
4924 rtx offset = GEN_INT (delta);
4925 if (!SMALL_OPERAND (delta))
4926 {
4927 riscv_emit_move (temp1, offset);
4928 offset = temp1;
4929 }
4930 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
4931 }
4932
4933 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
4934 if (vcall_offset != 0)
4935 {
4936 rtx addr;
4937
4938 /* Set TEMP1 to *THIS_RTX. */
4939 riscv_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
4940
4941 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
4942 addr = riscv_add_offset (temp2, temp1, vcall_offset);
4943
4944 /* Load the offset and add it to THIS_RTX. */
4945 riscv_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
4946 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
4947 }
4948
4949 /* Jump to the target function. */
4950 insn = emit_call_insn (gen_sibcall (fnaddr, const0_rtx, NULL, const0_rtx));
4951 SIBLING_CALL_P (insn) = 1;
4952
4953 /* Run just enough of rest_of_compilation. This sequence was
4954 "borrowed" from alpha.cc. */
4955 insn = get_insns ();
4956 split_all_insns_noflow ();
4957 shorten_branches (insn);
4958 assemble_start_function (thunk_fndecl, fnname);
4959 final_start_function (insn, file, 1);
4960 final (insn, file, 1);
4961 final_end_function ();
4962 assemble_end_function (thunk_fndecl, fnname);
4963
4964 /* Clean up the vars set above. Note that final_end_function resets
4965 the global pointer for us. */
4966 reload_completed = 0;
4967 }
4968
4969 /* Allocate a chunk of memory for per-function machine-dependent data. */
4970
4971 static struct machine_function *
riscv_init_machine_status(void)4972 riscv_init_machine_status (void)
4973 {
4974 return ggc_cleared_alloc<machine_function> ();
4975 }
4976
4977 /* Implement TARGET_OPTION_OVERRIDE. */
4978
4979 static void
riscv_option_override(void)4980 riscv_option_override (void)
4981 {
4982 const struct riscv_tune_info *cpu;
4983
4984 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4985 SUBTARGET_OVERRIDE_OPTIONS;
4986 #endif
4987
4988 flag_pcc_struct_return = 0;
4989
4990 if (flag_pic)
4991 g_switch_value = 0;
4992
4993 /* The presence of the M extension implies that division instructions
4994 are present, so include them unless explicitly disabled. */
4995 if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
4996 target_flags |= MASK_DIV;
4997 else if (!TARGET_MUL && TARGET_DIV)
4998 error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
4999
5000 /* Likewise floating-point division and square root. */
5001 if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
5002 target_flags |= MASK_FDIV;
5003
5004 /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
5005 if -mtune and -mcpu both not given. */
5006 cpu = riscv_parse_tune (riscv_tune_string ? riscv_tune_string :
5007 (riscv_cpu_string ? riscv_cpu_string :
5008 RISCV_TUNE_STRING_DEFAULT));
5009 riscv_microarchitecture = cpu->microarchitecture;
5010 tune_param = optimize_size ? &optimize_size_tune_info : cpu->tune_param;
5011
5012 /* Use -mtune's setting for slow_unaligned_access, even when optimizing
5013 for size. For architectures that trap and emulate unaligned accesses,
5014 the performance cost is too great, even for -Os. Similarly, if
5015 -m[no-]strict-align is left unspecified, heed -mtune's advice. */
5016 riscv_slow_unaligned_access_p = (cpu->tune_param->slow_unaligned_access
5017 || TARGET_STRICT_ALIGN);
5018 if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0
5019 && cpu->tune_param->slow_unaligned_access)
5020 target_flags |= MASK_STRICT_ALIGN;
5021
5022 /* If the user hasn't specified a branch cost, use the processor's
5023 default. */
5024 if (riscv_branch_cost == 0)
5025 riscv_branch_cost = tune_param->branch_cost;
5026
5027 /* Function to allocate machine-dependent function status. */
5028 init_machine_status = &riscv_init_machine_status;
5029
5030 if (flag_pic)
5031 riscv_cmodel = CM_PIC;
5032
5033 /* We get better code with explicit relocs for CM_MEDLOW, but
5034 worse code for the others (for now). Pick the best default. */
5035 if ((target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
5036 if (riscv_cmodel == CM_MEDLOW)
5037 target_flags |= MASK_EXPLICIT_RELOCS;
5038
5039 /* Require that the ISA supports the requested floating-point ABI. */
5040 if (UNITS_PER_FP_ARG > (TARGET_HARD_FLOAT ? UNITS_PER_FP_REG : 0))
5041 error ("requested ABI requires %<-march%> to subsume the %qc extension",
5042 UNITS_PER_FP_ARG > 8 ? 'Q' : (UNITS_PER_FP_ARG > 4 ? 'D' : 'F'));
5043
5044 if (TARGET_RVE && riscv_abi != ABI_ILP32E)
5045 error ("rv32e requires ilp32e ABI");
5046
5047 /* We do not yet support ILP32 on RV64. */
5048 if (BITS_PER_WORD != POINTER_SIZE)
5049 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
5050
5051 /* Validate -mpreferred-stack-boundary= value. */
5052 riscv_stack_boundary = ABI_STACK_BOUNDARY;
5053 if (riscv_preferred_stack_boundary_arg)
5054 {
5055 int min = ctz_hwi (STACK_BOUNDARY / 8);
5056 int max = 8;
5057
5058 if (!IN_RANGE (riscv_preferred_stack_boundary_arg, min, max))
5059 error ("%<-mpreferred-stack-boundary=%d%> must be between %d and %d",
5060 riscv_preferred_stack_boundary_arg, min, max);
5061
5062 riscv_stack_boundary = 8 << riscv_preferred_stack_boundary_arg;
5063 }
5064
5065 if (riscv_emit_attribute_p < 0)
5066 #ifdef HAVE_AS_RISCV_ATTRIBUTE
5067 riscv_emit_attribute_p = TARGET_RISCV_ATTRIBUTE;
5068 #else
5069 riscv_emit_attribute_p = 0;
5070
5071 if (riscv_emit_attribute_p)
5072 error ("%<-mriscv-attribute%> RISC-V ELF attribute requires GNU as 2.32"
5073 " [%<-mriscv-attribute%>]");
5074 #endif
5075
5076 if (riscv_stack_protector_guard == SSP_GLOBAL
5077 && OPTION_SET_P (riscv_stack_protector_guard_offset_str))
5078 {
5079 error ("incompatible options %<-mstack-protector-guard=global%> and "
5080 "%<-mstack-protector-guard-offset=%s%>",
5081 riscv_stack_protector_guard_offset_str);
5082 }
5083
5084 if (riscv_stack_protector_guard == SSP_TLS
5085 && !(OPTION_SET_P (riscv_stack_protector_guard_offset_str)
5086 && OPTION_SET_P (riscv_stack_protector_guard_reg_str)))
5087 {
5088 error ("both %<-mstack-protector-guard-offset%> and "
5089 "%<-mstack-protector-guard-reg%> must be used "
5090 "with %<-mstack-protector-guard=sysreg%>");
5091 }
5092
5093 if (OPTION_SET_P (riscv_stack_protector_guard_reg_str))
5094 {
5095 const char *str = riscv_stack_protector_guard_reg_str;
5096 int reg = decode_reg_name (str);
5097
5098 if (!IN_RANGE (reg, GP_REG_FIRST + 1, GP_REG_LAST))
5099 error ("%qs is not a valid base register in %qs", str,
5100 "-mstack-protector-guard-reg=");
5101
5102 riscv_stack_protector_guard_reg = reg;
5103 }
5104
5105 if (OPTION_SET_P (riscv_stack_protector_guard_offset_str))
5106 {
5107 char *end;
5108 const char *str = riscv_stack_protector_guard_offset_str;
5109 errno = 0;
5110 long offs = strtol (riscv_stack_protector_guard_offset_str, &end, 0);
5111
5112 if (!*str || *end || errno)
5113 error ("%qs is not a valid number in %qs", str,
5114 "-mstack-protector-guard-offset=");
5115
5116 if (!SMALL_OPERAND (offs))
5117 error ("%qs is not a valid offset in %qs", str,
5118 "-mstack-protector-guard-offset=");
5119
5120 riscv_stack_protector_guard_offset = offs;
5121 }
5122
5123 }
5124
5125 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
5126
5127 static void
riscv_conditional_register_usage(void)5128 riscv_conditional_register_usage (void)
5129 {
5130 /* We have only x0~x15 on RV32E. */
5131 if (TARGET_RVE)
5132 {
5133 for (int r = 16; r <= 31; r++)
5134 fixed_regs[r] = 1;
5135 }
5136
5137 if (riscv_abi == ABI_ILP32E)
5138 {
5139 for (int r = 16; r <= 31; r++)
5140 call_used_regs[r] = 1;
5141 }
5142
5143 if (!TARGET_HARD_FLOAT)
5144 {
5145 for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5146 fixed_regs[regno] = call_used_regs[regno] = 1;
5147 }
5148
5149 /* In the soft-float ABI, there are no callee-saved FP registers. */
5150 if (UNITS_PER_FP_ARG == 0)
5151 {
5152 for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5153 call_used_regs[regno] = 1;
5154 }
5155 }
5156
5157 /* Return a register priority for hard reg REGNO. */
5158
5159 static int
riscv_register_priority(int regno)5160 riscv_register_priority (int regno)
5161 {
5162 /* Favor compressed registers to improve the odds of RVC instruction
5163 selection. */
5164 if (riscv_compressed_reg_p (regno))
5165 return 1;
5166
5167 return 0;
5168 }
5169
5170 /* Implement TARGET_TRAMPOLINE_INIT. */
5171
5172 static void
riscv_trampoline_init(rtx m_tramp,tree fndecl,rtx chain_value)5173 riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
5174 {
5175 rtx addr, end_addr, mem;
5176 uint32_t trampoline[4];
5177 unsigned int i;
5178 HOST_WIDE_INT static_chain_offset, target_function_offset;
5179
5180 /* Work out the offsets of the pointers from the start of the
5181 trampoline code. */
5182 gcc_assert (ARRAY_SIZE (trampoline) * 4 == TRAMPOLINE_CODE_SIZE);
5183
5184 /* Get pointers to the beginning and end of the code block. */
5185 addr = force_reg (Pmode, XEXP (m_tramp, 0));
5186 end_addr = riscv_force_binary (Pmode, PLUS, addr,
5187 GEN_INT (TRAMPOLINE_CODE_SIZE));
5188
5189
5190 if (Pmode == SImode)
5191 {
5192 chain_value = force_reg (Pmode, chain_value);
5193
5194 rtx target_function = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
5195 /* lui t2, hi(chain)
5196 lui t0, hi(func)
5197 addi t2, t2, lo(chain)
5198 jr t0, lo(func)
5199 */
5200 unsigned HOST_WIDE_INT lui_hi_chain_code, lui_hi_func_code;
5201 unsigned HOST_WIDE_INT lo_chain_code, lo_func_code;
5202
5203 rtx uimm_mask = force_reg (SImode, gen_int_mode (-IMM_REACH, SImode));
5204
5205 /* 0xfff. */
5206 rtx imm12_mask = gen_reg_rtx (SImode);
5207 emit_insn (gen_one_cmplsi2 (imm12_mask, uimm_mask));
5208
5209 rtx fixup_value = force_reg (SImode, gen_int_mode (IMM_REACH/2, SImode));
5210
5211 /* Gen lui t2, hi(chain). */
5212 rtx hi_chain = riscv_force_binary (SImode, PLUS, chain_value,
5213 fixup_value);
5214 hi_chain = riscv_force_binary (SImode, AND, hi_chain,
5215 uimm_mask);
5216 lui_hi_chain_code = OPCODE_LUI | (STATIC_CHAIN_REGNUM << SHIFT_RD);
5217 rtx lui_hi_chain = riscv_force_binary (SImode, IOR, hi_chain,
5218 gen_int_mode (lui_hi_chain_code, SImode));
5219
5220 mem = adjust_address (m_tramp, SImode, 0);
5221 riscv_emit_move (mem, riscv_swap_instruction (lui_hi_chain));
5222
5223 /* Gen lui t0, hi(func). */
5224 rtx hi_func = riscv_force_binary (SImode, PLUS, target_function,
5225 fixup_value);
5226 hi_func = riscv_force_binary (SImode, AND, hi_func,
5227 uimm_mask);
5228 lui_hi_func_code = OPCODE_LUI | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD);
5229 rtx lui_hi_func = riscv_force_binary (SImode, IOR, hi_func,
5230 gen_int_mode (lui_hi_func_code, SImode));
5231
5232 mem = adjust_address (m_tramp, SImode, 1 * GET_MODE_SIZE (SImode));
5233 riscv_emit_move (mem, riscv_swap_instruction (lui_hi_func));
5234
5235 /* Gen addi t2, t2, lo(chain). */
5236 rtx lo_chain = riscv_force_binary (SImode, AND, chain_value,
5237 imm12_mask);
5238 lo_chain = riscv_force_binary (SImode, ASHIFT, lo_chain, GEN_INT (20));
5239
5240 lo_chain_code = OPCODE_ADDI
5241 | (STATIC_CHAIN_REGNUM << SHIFT_RD)
5242 | (STATIC_CHAIN_REGNUM << SHIFT_RS1);
5243
5244 rtx addi_lo_chain = riscv_force_binary (SImode, IOR, lo_chain,
5245 force_reg (SImode, GEN_INT (lo_chain_code)));
5246
5247 mem = adjust_address (m_tramp, SImode, 2 * GET_MODE_SIZE (SImode));
5248 riscv_emit_move (mem, riscv_swap_instruction (addi_lo_chain));
5249
5250 /* Gen jr t0, lo(func). */
5251 rtx lo_func = riscv_force_binary (SImode, AND, target_function,
5252 imm12_mask);
5253 lo_func = riscv_force_binary (SImode, ASHIFT, lo_func, GEN_INT (20));
5254
5255 lo_func_code = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1);
5256
5257 rtx jr_lo_func = riscv_force_binary (SImode, IOR, lo_func,
5258 force_reg (SImode, GEN_INT (lo_func_code)));
5259
5260 mem = adjust_address (m_tramp, SImode, 3 * GET_MODE_SIZE (SImode));
5261 riscv_emit_move (mem, riscv_swap_instruction (jr_lo_func));
5262 }
5263 else
5264 {
5265 static_chain_offset = TRAMPOLINE_CODE_SIZE;
5266 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
5267
5268 /* auipc t2, 0
5269 l[wd] t0, target_function_offset(t2)
5270 l[wd] t2, static_chain_offset(t2)
5271 jr t0
5272 */
5273 trampoline[0] = OPCODE_AUIPC | (STATIC_CHAIN_REGNUM << SHIFT_RD);
5274 trampoline[1] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW)
5275 | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD)
5276 | (STATIC_CHAIN_REGNUM << SHIFT_RS1)
5277 | (target_function_offset << SHIFT_IMM);
5278 trampoline[2] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW)
5279 | (STATIC_CHAIN_REGNUM << SHIFT_RD)
5280 | (STATIC_CHAIN_REGNUM << SHIFT_RS1)
5281 | (static_chain_offset << SHIFT_IMM);
5282 trampoline[3] = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1);
5283
5284 /* Copy the trampoline code. */
5285 for (i = 0; i < ARRAY_SIZE (trampoline); i++)
5286 {
5287 if (BYTES_BIG_ENDIAN)
5288 trampoline[i] = __builtin_bswap32(trampoline[i]);
5289 mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode));
5290 riscv_emit_move (mem, gen_int_mode (trampoline[i], SImode));
5291 }
5292
5293 /* Set up the static chain pointer field. */
5294 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
5295 riscv_emit_move (mem, chain_value);
5296
5297 /* Set up the target function field. */
5298 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
5299 riscv_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
5300 }
5301
5302 /* Flush the code part of the trampoline. */
5303 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
5304 emit_insn (gen_clear_cache (addr, end_addr));
5305 }
5306
5307 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
5308
5309 static bool
riscv_function_ok_for_sibcall(tree decl ATTRIBUTE_UNUSED,tree exp ATTRIBUTE_UNUSED)5310 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
5311 tree exp ATTRIBUTE_UNUSED)
5312 {
5313 /* Don't use sibcalls when use save-restore routine. */
5314 if (TARGET_SAVE_RESTORE)
5315 return false;
5316
5317 /* Don't use sibcall for naked functions. */
5318 if (cfun->machine->naked_p)
5319 return false;
5320
5321 /* Don't use sibcall for interrupt functions. */
5322 if (cfun->machine->interrupt_handler_p)
5323 return false;
5324
5325 return true;
5326 }
5327
5328 /* Get the interrupt type, return UNKNOWN_MODE if it's not
5329 interrupt function. */
5330 static enum riscv_privilege_levels
riscv_get_interrupt_type(tree decl)5331 riscv_get_interrupt_type (tree decl)
5332 {
5333 gcc_assert (decl != NULL_TREE);
5334
5335 if ((TREE_CODE(decl) != FUNCTION_DECL)
5336 || (!riscv_interrupt_type_p (TREE_TYPE (decl))))
5337 return UNKNOWN_MODE;
5338
5339 tree attr_args
5340 = TREE_VALUE (lookup_attribute ("interrupt",
5341 TYPE_ATTRIBUTES (TREE_TYPE (decl))));
5342
5343 if (attr_args && TREE_CODE (TREE_VALUE (attr_args)) != VOID_TYPE)
5344 {
5345 const char *string = TREE_STRING_POINTER (TREE_VALUE (attr_args));
5346
5347 if (!strcmp (string, "user"))
5348 return USER_MODE;
5349 else if (!strcmp (string, "supervisor"))
5350 return SUPERVISOR_MODE;
5351 else /* Must be "machine". */
5352 return MACHINE_MODE;
5353 }
5354 else
5355 /* Interrupt attributes are machine mode by default. */
5356 return MACHINE_MODE;
5357 }
5358
5359 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */
5360 /* Sanity cheching for above function attributes. */
5361 static void
riscv_set_current_function(tree decl)5362 riscv_set_current_function (tree decl)
5363 {
5364 if (decl == NULL_TREE
5365 || current_function_decl == NULL_TREE
5366 || current_function_decl == error_mark_node
5367 || ! cfun->machine
5368 || cfun->machine->attributes_checked_p)
5369 return;
5370
5371 cfun->machine->naked_p = riscv_naked_function_p (decl);
5372 cfun->machine->interrupt_handler_p
5373 = riscv_interrupt_type_p (TREE_TYPE (decl));
5374
5375 if (cfun->machine->naked_p && cfun->machine->interrupt_handler_p)
5376 error ("function attributes %qs and %qs are mutually exclusive",
5377 "interrupt", "naked");
5378
5379 if (cfun->machine->interrupt_handler_p)
5380 {
5381 tree ret = TREE_TYPE (TREE_TYPE (decl));
5382 tree args = TYPE_ARG_TYPES (TREE_TYPE (decl));
5383
5384 if (TREE_CODE (ret) != VOID_TYPE)
5385 error ("%qs function cannot return a value", "interrupt");
5386
5387 if (args && TREE_CODE (TREE_VALUE (args)) != VOID_TYPE)
5388 error ("%qs function cannot have arguments", "interrupt");
5389
5390 cfun->machine->interrupt_mode = riscv_get_interrupt_type (decl);
5391
5392 gcc_assert (cfun->machine->interrupt_mode != UNKNOWN_MODE);
5393 }
5394
5395 /* Don't print the above diagnostics more than once. */
5396 cfun->machine->attributes_checked_p = 1;
5397 }
5398
5399 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
5400 static tree
riscv_merge_decl_attributes(tree olddecl,tree newdecl)5401 riscv_merge_decl_attributes (tree olddecl, tree newdecl)
5402 {
5403 tree combined_attrs;
5404
5405 enum riscv_privilege_levels old_interrupt_type
5406 = riscv_get_interrupt_type (olddecl);
5407 enum riscv_privilege_levels new_interrupt_type
5408 = riscv_get_interrupt_type (newdecl);
5409
5410 /* Check old and new has same interrupt type. */
5411 if ((old_interrupt_type != UNKNOWN_MODE)
5412 && (new_interrupt_type != UNKNOWN_MODE)
5413 && (old_interrupt_type != new_interrupt_type))
5414 error ("%qs function cannot have different interrupt type", "interrupt");
5415
5416 /* Create combined attributes. */
5417 combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl),
5418 DECL_ATTRIBUTES (newdecl));
5419
5420 return combined_attrs;
5421 }
5422
5423 /* Implement TARGET_CANNOT_COPY_INSN_P. */
5424
5425 static bool
riscv_cannot_copy_insn_p(rtx_insn * insn)5426 riscv_cannot_copy_insn_p (rtx_insn *insn)
5427 {
5428 return recog_memoized (insn) >= 0 && get_attr_cannot_copy (insn);
5429 }
5430
5431 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
5432
5433 static bool
riscv_slow_unaligned_access(machine_mode,unsigned int)5434 riscv_slow_unaligned_access (machine_mode, unsigned int)
5435 {
5436 return riscv_slow_unaligned_access_p;
5437 }
5438
5439 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
5440
5441 static bool
riscv_can_change_mode_class(machine_mode,machine_mode,reg_class_t rclass)5442 riscv_can_change_mode_class (machine_mode, machine_mode, reg_class_t rclass)
5443 {
5444 return !reg_classes_intersect_p (FP_REGS, rclass);
5445 }
5446
5447
5448 /* Implement TARGET_CONSTANT_ALIGNMENT. */
5449
5450 static HOST_WIDE_INT
riscv_constant_alignment(const_tree exp,HOST_WIDE_INT align)5451 riscv_constant_alignment (const_tree exp, HOST_WIDE_INT align)
5452 {
5453 if ((TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR)
5454 && (riscv_align_data_type == riscv_align_data_type_xlen))
5455 return MAX (align, BITS_PER_WORD);
5456 return align;
5457 }
5458
5459 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */
5460
5461 /* This function is equivalent to default_promote_function_mode_always_promote
5462 except that it returns a promoted mode even if type is NULL_TREE. This is
5463 needed by libcalls which have no type (only a mode) such as fixed conversion
5464 routines that take a signed or unsigned char/short/int argument and convert
5465 it to a fixed type. */
5466
5467 static machine_mode
riscv_promote_function_mode(const_tree type ATTRIBUTE_UNUSED,machine_mode mode,int * punsignedp ATTRIBUTE_UNUSED,const_tree fntype ATTRIBUTE_UNUSED,int for_return ATTRIBUTE_UNUSED)5468 riscv_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
5469 machine_mode mode,
5470 int *punsignedp ATTRIBUTE_UNUSED,
5471 const_tree fntype ATTRIBUTE_UNUSED,
5472 int for_return ATTRIBUTE_UNUSED)
5473 {
5474 int unsignedp;
5475
5476 if (type != NULL_TREE)
5477 return promote_mode (type, mode, punsignedp);
5478
5479 unsignedp = *punsignedp;
5480 PROMOTE_MODE (mode, unsignedp, type);
5481 *punsignedp = unsignedp;
5482 return mode;
5483 }
5484
5485 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
5486
5487 static void
riscv_reorg(void)5488 riscv_reorg (void)
5489 {
5490 /* Do nothing unless we have -msave-restore */
5491 if (TARGET_SAVE_RESTORE)
5492 riscv_remove_unneeded_save_restore_calls ();
5493 }
5494
5495 /* Return nonzero if register FROM_REGNO can be renamed to register
5496 TO_REGNO. */
5497
5498 bool
riscv_hard_regno_rename_ok(unsigned from_regno ATTRIBUTE_UNUSED,unsigned to_regno)5499 riscv_hard_regno_rename_ok (unsigned from_regno ATTRIBUTE_UNUSED,
5500 unsigned to_regno)
5501 {
5502 /* Interrupt functions can only use registers that have already been
5503 saved by the prologue, even if they would normally be
5504 call-clobbered. */
5505 return !cfun->machine->interrupt_handler_p || df_regs_ever_live_p (to_regno);
5506 }
5507
5508 /* Implement TARGET_NEW_ADDRESS_PROFITABLE_P. */
5509
5510 bool
riscv_new_address_profitable_p(rtx memref,rtx_insn * insn,rtx new_addr)5511 riscv_new_address_profitable_p (rtx memref, rtx_insn *insn, rtx new_addr)
5512 {
5513 /* Prefer old address if it is less expensive. */
5514 addr_space_t as = MEM_ADDR_SPACE (memref);
5515 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
5516 int old_cost = address_cost (XEXP (memref, 0), GET_MODE (memref), as, speed);
5517 int new_cost = address_cost (new_addr, GET_MODE (memref), as, speed);
5518 return new_cost <= old_cost;
5519 }
5520
5521 /* Helper function for generating gpr_save pattern. */
5522
5523 rtx
riscv_gen_gpr_save_insn(struct riscv_frame_info * frame)5524 riscv_gen_gpr_save_insn (struct riscv_frame_info *frame)
5525 {
5526 unsigned count = riscv_save_libcall_count (frame->mask);
5527 /* 1 for unspec 2 for clobber t0/t1 and 1 for ra. */
5528 unsigned veclen = 1 + 2 + 1 + count;
5529 rtvec vec = rtvec_alloc (veclen);
5530
5531 gcc_assert (veclen <= ARRAY_SIZE (gpr_save_reg_order));
5532
5533 RTVEC_ELT (vec, 0) =
5534 gen_rtx_UNSPEC_VOLATILE (VOIDmode,
5535 gen_rtvec (1, GEN_INT (count)), UNSPECV_GPR_SAVE);
5536
5537 for (unsigned i = 1; i < veclen; ++i)
5538 {
5539 unsigned regno = gpr_save_reg_order[i];
5540 rtx reg = gen_rtx_REG (Pmode, regno);
5541 rtx elt;
5542
5543 /* t0 and t1 are CLOBBERs, others are USEs. */
5544 if (i < 3)
5545 elt = gen_rtx_CLOBBER (Pmode, reg);
5546 else
5547 elt = gen_rtx_USE (Pmode, reg);
5548
5549 RTVEC_ELT (vec, i) = elt;
5550 }
5551
5552 /* Largest number of caller-save register must set in mask if we are
5553 not using __riscv_save_0. */
5554 gcc_assert ((count == 0) ||
5555 BITSET_P (frame->mask, gpr_save_reg_order[veclen - 1]));
5556
5557 return gen_rtx_PARALLEL (VOIDmode, vec);
5558 }
5559
5560 /* Return true if it's valid gpr_save pattern. */
5561
5562 bool
riscv_gpr_save_operation_p(rtx op)5563 riscv_gpr_save_operation_p (rtx op)
5564 {
5565 unsigned len = XVECLEN (op, 0);
5566
5567 if (len > ARRAY_SIZE (gpr_save_reg_order))
5568 return false;
5569
5570 for (unsigned i = 0; i < len; i++)
5571 {
5572 rtx elt = XVECEXP (op, 0, i);
5573 if (i == 0)
5574 {
5575 /* First element in parallel is unspec. */
5576 if (GET_CODE (elt) != UNSPEC_VOLATILE
5577 || GET_CODE (XVECEXP (elt, 0, 0)) != CONST_INT
5578 || XINT (elt, 1) != UNSPECV_GPR_SAVE)
5579 return false;
5580 }
5581 else
5582 {
5583 /* Two CLOBBER and USEs, must check the order. */
5584 unsigned expect_code = i < 3 ? CLOBBER : USE;
5585 if (GET_CODE (elt) != expect_code
5586 || !REG_P (XEXP (elt, 1))
5587 || (REGNO (XEXP (elt, 1)) != gpr_save_reg_order[i]))
5588 return false;
5589 }
5590 break;
5591 }
5592 return true;
5593 }
5594
5595 /* Implement TARGET_ASAN_SHADOW_OFFSET. */
5596
5597 static unsigned HOST_WIDE_INT
riscv_asan_shadow_offset(void)5598 riscv_asan_shadow_offset (void)
5599 {
5600 /* We only have libsanitizer support for RV64 at present.
5601
5602 This number must match kRiscv*_ShadowOffset* in the file
5603 libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
5604 even though 1<<36 makes more sense. */
5605 return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
5606 }
5607
5608 /* Initialize the GCC target structure. */
5609 #undef TARGET_ASM_ALIGNED_HI_OP
5610 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
5611 #undef TARGET_ASM_ALIGNED_SI_OP
5612 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
5613 #undef TARGET_ASM_ALIGNED_DI_OP
5614 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
5615
5616 #undef TARGET_OPTION_OVERRIDE
5617 #define TARGET_OPTION_OVERRIDE riscv_option_override
5618
5619 #undef TARGET_LEGITIMIZE_ADDRESS
5620 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
5621
5622 #undef TARGET_SCHED_ISSUE_RATE
5623 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
5624
5625 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5626 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
5627
5628 #undef TARGET_SET_CURRENT_FUNCTION
5629 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
5630
5631 #undef TARGET_REGISTER_MOVE_COST
5632 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
5633 #undef TARGET_MEMORY_MOVE_COST
5634 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
5635 #undef TARGET_RTX_COSTS
5636 #define TARGET_RTX_COSTS riscv_rtx_costs
5637 #undef TARGET_ADDRESS_COST
5638 #define TARGET_ADDRESS_COST riscv_address_cost
5639
5640 #undef TARGET_ASM_FILE_START
5641 #define TARGET_ASM_FILE_START riscv_file_start
5642 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5643 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5644
5645 #undef TARGET_EXPAND_BUILTIN_VA_START
5646 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
5647
5648 #undef TARGET_PROMOTE_FUNCTION_MODE
5649 #define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode
5650
5651 #undef TARGET_RETURN_IN_MEMORY
5652 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory
5653
5654 #undef TARGET_ASM_OUTPUT_MI_THUNK
5655 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk
5656 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5657 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
5658
5659 #undef TARGET_PRINT_OPERAND
5660 #define TARGET_PRINT_OPERAND riscv_print_operand
5661 #undef TARGET_PRINT_OPERAND_ADDRESS
5662 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
5663
5664 #undef TARGET_SETUP_INCOMING_VARARGS
5665 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
5666 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
5667 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
5668 #undef TARGET_STRICT_ARGUMENT_NAMING
5669 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
5670 #undef TARGET_MUST_PASS_IN_STACK
5671 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
5672 #undef TARGET_PASS_BY_REFERENCE
5673 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference
5674 #undef TARGET_ARG_PARTIAL_BYTES
5675 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes
5676 #undef TARGET_FUNCTION_ARG
5677 #define TARGET_FUNCTION_ARG riscv_function_arg
5678 #undef TARGET_FUNCTION_ARG_ADVANCE
5679 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance
5680 #undef TARGET_FUNCTION_ARG_BOUNDARY
5681 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
5682
5683 /* The generic ELF target does not always have TLS support. */
5684 #ifdef HAVE_AS_TLS
5685 #undef TARGET_HAVE_TLS
5686 #define TARGET_HAVE_TLS true
5687 #endif
5688
5689 #undef TARGET_CANNOT_FORCE_CONST_MEM
5690 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem
5691
5692 #undef TARGET_LEGITIMATE_CONSTANT_P
5693 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p
5694
5695 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
5696 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
5697
5698 #undef TARGET_LEGITIMATE_ADDRESS_P
5699 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p
5700
5701 #undef TARGET_CAN_ELIMINATE
5702 #define TARGET_CAN_ELIMINATE riscv_can_eliminate
5703
5704 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5705 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
5706
5707 #undef TARGET_CLASS_MAX_NREGS
5708 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
5709
5710 #undef TARGET_TRAMPOLINE_INIT
5711 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
5712
5713 #undef TARGET_IN_SMALL_DATA_P
5714 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
5715
5716 #undef TARGET_HAVE_SRODATA_SECTION
5717 #define TARGET_HAVE_SRODATA_SECTION true
5718
5719 #undef TARGET_ASM_SELECT_SECTION
5720 #define TARGET_ASM_SELECT_SECTION riscv_select_section
5721
5722 #undef TARGET_ASM_UNIQUE_SECTION
5723 #define TARGET_ASM_UNIQUE_SECTION riscv_unique_section
5724
5725 #undef TARGET_ASM_SELECT_RTX_SECTION
5726 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
5727
5728 #undef TARGET_MIN_ANCHOR_OFFSET
5729 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
5730
5731 #undef TARGET_MAX_ANCHOR_OFFSET
5732 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
5733
5734 #undef TARGET_REGISTER_PRIORITY
5735 #define TARGET_REGISTER_PRIORITY riscv_register_priority
5736
5737 #undef TARGET_CANNOT_COPY_INSN_P
5738 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p
5739
5740 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
5741 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv
5742
5743 #undef TARGET_INIT_BUILTINS
5744 #define TARGET_INIT_BUILTINS riscv_init_builtins
5745
5746 #undef TARGET_BUILTIN_DECL
5747 #define TARGET_BUILTIN_DECL riscv_builtin_decl
5748
5749 #undef TARGET_EXPAND_BUILTIN
5750 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin
5751
5752 #undef TARGET_HARD_REGNO_NREGS
5753 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs
5754 #undef TARGET_HARD_REGNO_MODE_OK
5755 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
5756
5757 #undef TARGET_MODES_TIEABLE_P
5758 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p
5759
5760 #undef TARGET_SLOW_UNALIGNED_ACCESS
5761 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access
5762
5763 #undef TARGET_SECONDARY_MEMORY_NEEDED
5764 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed
5765
5766 #undef TARGET_CAN_CHANGE_MODE_CLASS
5767 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
5768
5769 #undef TARGET_CONSTANT_ALIGNMENT
5770 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
5771
5772 #undef TARGET_MERGE_DECL_ATTRIBUTES
5773 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
5774
5775 #undef TARGET_ATTRIBUTE_TABLE
5776 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
5777
5778 #undef TARGET_WARN_FUNC_RETURN
5779 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
5780
5781 /* The low bit is ignored by jump instructions so is safe to use. */
5782 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
5783 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
5784
5785 #undef TARGET_MACHINE_DEPENDENT_REORG
5786 #define TARGET_MACHINE_DEPENDENT_REORG riscv_reorg
5787
5788 #undef TARGET_NEW_ADDRESS_PROFITABLE_P
5789 #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
5790
5791 #undef TARGET_ASAN_SHADOW_OFFSET
5792 #define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
5793
5794 #ifdef TARGET_BIG_ENDIAN_DEFAULT
5795 #undef TARGET_DEFAULT_TARGET_FLAGS
5796 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN)
5797 #endif
5798
5799 struct gcc_target targetm = TARGET_INITIALIZER;
5800
5801 #include "gt-riscv.h"
5802