1//Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple1/lmu_cplb_multiple1.dsp 2// Description: Multiple CPLB Hit exceptions (DAG1) 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10include(selfcheck.inc) 11include(std.inc) 12include(mmrs.inc) 13 14//------------------------------------- 15 16// Test LMU/CPLB exceptions 17 18// Basic outline: 19// Set exception handler 20// program CPLB Entries 21// Enable CPLB in DMEM_CNTL 22// perform access 23// verify exception occurred 24 25CHECK_INIT(p5, 0xEFFFFFFC); 26 27//------------------------- 28// Zero the CPLB Address and Data regs. 29 30 LD32(p0, DCPLB_ADDR0); 31 R0 = 0; 32 [ P0 ++ ] = R0; // 0 33 [ P0 ++ ] = R0; // 1 34 [ P0 ++ ] = R0; // 2 35 [ P0 ++ ] = R0; // 3 36 [ P0 ++ ] = R0; // 4 37 [ P0 ++ ] = R0; // 5 38 [ P0 ++ ] = R0; // 6 39 [ P0 ++ ] = R0; // 7 40 [ P0 ++ ] = R0; // 8 41 [ P0 ++ ] = R0; // 9 42 [ P0 ++ ] = R0; // 10 43 [ P0 ++ ] = R0; // 11 44 [ P0 ++ ] = R0; // 12 45 [ P0 ++ ] = R0; // 13 46 [ P0 ++ ] = R0; // 14 47 [ P0 ++ ] = R0; // 15 48 49 LD32(p0, DCPLB_DATA0); 50 [ P0 ++ ] = R0; // 0 51 [ P0 ++ ] = R0; // 1 52 [ P0 ++ ] = R0; // 2 53 [ P0 ++ ] = R0; // 3 54 [ P0 ++ ] = R0; // 4 55 [ P0 ++ ] = R0; // 5 56 [ P0 ++ ] = R0; // 6 57 [ P0 ++ ] = R0; // 7 58 [ P0 ++ ] = R0; // 8 59 [ P0 ++ ] = R0; // 9 60 [ P0 ++ ] = R0; // 10 61 [ P0 ++ ] = R0; // 11 62 [ P0 ++ ] = R0; // 12 63 [ P0 ++ ] = R0; // 13 64 [ P0 ++ ] = R0; // 14 65 [ P0 ++ ] = R0; // 15 66 67 // Now set the CPLB entries we will need 68 69 70 71 72 // Data area for the desired error 73 WR_MMR(DCPLB_ADDR0, 0x10000000, p0, r0); 74 WR_MMR(DCPLB_ADDR1, 0x10000000, p0, r0); 75 WR_MMR(DCPLB_ADDR2, 0x10000000, p0, r0); 76 WR_MMR(DCPLB_ADDR3, 0x10000000, p0, r0); 77 WR_MMR(DCPLB_ADDR4, 0x10000000, p0, r0); 78 WR_MMR(DCPLB_ADDR5, 0x10000000, p0, r0); 79 WR_MMR(DCPLB_ADDR6, 0x10000000, p0, r0); 80 WR_MMR(DCPLB_ADDR7, 0x10000000, p0, r0); 81 WR_MMR(DCPLB_ADDR8, 0x10000000, p0, r0); 82 WR_MMR(DCPLB_ADDR9, 0x10000000, p0, r0); 83 WR_MMR(DCPLB_ADDR10, 0x10000000, p0, r0); 84 WR_MMR(DCPLB_ADDR11, 0x10000000, p0, r0); 85 WR_MMR(DCPLB_ADDR12, 0x10000000, p0, r0); 86 WR_MMR(DCPLB_ADDR13, 0x10000000, p0, r0); 87 WR_MMR(DCPLB_ADDR14, 0x10000000, p0, r0); 88 89 // MMR space 90 WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); 91 WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); 92 93 // setup interrupt controller with exception handler address 94 WR_MMR_LABEL(EVT3, handler, p0, r1); 95 WR_MMR_LABEL(EVT15, int_15, p0, r1); 96 WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); 97 WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); 98 CSYNC; 99 100 A0 = 0; 101 102 // go to user mode. and enable exceptions 103 LD32_LABEL(r0, User); 104 RETI = R0; 105 106 // But first raise interrupt 15 so we can do one test 107 // in supervisor mode. 108 RAISE 15; 109 NOP; 110 111 RTI; 112 113 // Nops to work around ICache bug 114 NOP;NOP;NOP;NOP;NOP; 115 NOP;NOP;NOP;NOP;NOP; 116 117handler: 118 // generic protection exception handler 119 // Inputs: 120 // p2: addr of CPLB entry to be modified ( current test) 121 // 122 // Outputs: 123 // r4: SEQSTAT 124 // r5: DCPLB_FAULT_ADDR 125 // r6: DCPLB_STATUS 126 // r7: RETX (instruction addr where exception occurred) 127 128 129 R4 = SEQSTAT; // Get exception cause 130 R4 <<= 24; // Clear HWERRCAUSE + SFTRESET 131 R4 >>= 24; 132 133 // read data addr which caused exception 134 RD_MMR(DCPLB_FAULT_ADDR, p0, r5); 135 136 RD_MMR(DCPLB_STATUS, p0, r6); 137 138 R7 = RETX; // get address of excepting instruction 139 140 // disable the offending CPLB entries 141 R2 = 0; 142 [ P2 ] = R2; 143 144 CSYNC; 145 146 // return from exception and re-execute offending instruction 147 RTX; 148 149 // Nops to work around ICache bug 150 NOP;NOP;NOP;NOP;NOP; 151 NOP;NOP;NOP;NOP;NOP; 152 153 154int_15: 155 // Interrupt 15 handler - test will run in supervisor mode 156 157 //------------------------------------------------------- 158 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 159 160 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 161 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 162 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 163 CSYNC; 164 165 LD32(i1, 0x10000000); 166 R1 = 0x41C6 (Z); 167 LD32(p2, DCPLB_DATA1); 168 169X0_1: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 170 171 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 172 CSYNC; 173 WR_MMR(DCPLB_DATA0, 0, p0, r0); 174 175 // Now check that handler read correct values 176 CHECKREG(r4,0x27); // supv and EXCPT_PROT 177 CHECKREG(r5, 0x10000000); 178 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB1)); 179 CHECKREG_SYM(r7, X0_1, r0); // RETX should be value of X0_1 (HARDCODED ADDR!!) 180 181 //------------------------------------------------------- 182 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 183 184 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 185 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 186 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 187 CSYNC; 188 189 LD32(i1, 0x10000000); 190 R1 = 0x167E (Z); 191 LD32(p2, DCPLB_DATA2); 192 193X0_2: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 194 195 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 196 CSYNC; 197 WR_MMR(DCPLB_DATA0, 0, p0, r0); 198 199 // Now check that handler read correct values 200 CHECKREG(r4,0x27); // supv and EXCPT_PROT 201 CHECKREG(r5, 0x10000000); 202 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB2)); 203 CHECKREG_SYM(r7, X0_2, r0); // RETX should be value of X0_2 (HARDCODED ADDR!!) 204 205 //------------------------------------------------------- 206 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 207 208 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 209 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 210 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 211 CSYNC; 212 213 LD32(i1, 0x10000000); 214 R1 = 0x2781 (Z); 215 LD32(p2, DCPLB_DATA3); 216 217X0_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 218 219 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 220 CSYNC; 221 WR_MMR(DCPLB_DATA0, 0, p0, r0); 222 223 // Now check that handler read correct values 224 CHECKREG(r4,0x27); // supv and EXCPT_PROT 225 CHECKREG(r5, 0x10000000); 226 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB3)); 227 CHECKREG_SYM(r7, X0_3, r0); // RETX should be value of X0_3 (HARDCODED ADDR!!) 228 229 //------------------------------------------------------- 230 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 231 232 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 233 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 234 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 235 CSYNC; 236 237 LD32(i1, 0x10000000); 238 R1 = 0x446B (Z); 239 LD32(p2, DCPLB_DATA4); 240 241X0_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 242 243 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 244 CSYNC; 245 WR_MMR(DCPLB_DATA0, 0, p0, r0); 246 247 // Now check that handler read correct values 248 CHECKREG(r4,0x27); // supv and EXCPT_PROT 249 CHECKREG(r5, 0x10000000); 250 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB4)); 251 CHECKREG_SYM(r7, X0_4, r0); // RETX should be value of X0_4 (HARDCODED ADDR!!) 252 253 //------------------------------------------------------- 254 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 255 256 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 257 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 258 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 259 CSYNC; 260 261 LD32(i1, 0x10000000); 262 R1 = 0x794B (Z); 263 LD32(p2, DCPLB_DATA5); 264 265X0_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 266 267 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 268 CSYNC; 269 WR_MMR(DCPLB_DATA0, 0, p0, r0); 270 271 // Now check that handler read correct values 272 CHECKREG(r4,0x27); // supv and EXCPT_PROT 273 CHECKREG(r5, 0x10000000); 274 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB5)); 275 CHECKREG_SYM(r7, X0_5, r0); // RETX should be value of X0_5 (HARDCODED ADDR!!) 276 277 //------------------------------------------------------- 278 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 279 280 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 281 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 282 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 283 CSYNC; 284 285 LD32(i1, 0x10000000); 286 R1 = 0x15FB (Z); 287 LD32(p2, DCPLB_DATA6); 288 289X0_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 290 291 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 292 CSYNC; 293 WR_MMR(DCPLB_DATA0, 0, p0, r0); 294 295 // Now check that handler read correct values 296 CHECKREG(r4,0x27); // supv and EXCPT_PROT 297 CHECKREG(r5, 0x10000000); 298 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB6)); 299 CHECKREG_SYM(r7, X0_6, r0); // RETX should be value of X0_6 (HARDCODED ADDR!!) 300 301 //------------------------------------------------------- 302 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 303 304 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 305 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 306 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 307 CSYNC; 308 309 LD32(i1, 0x10000000); 310 R1 = 0x59E2 (Z); 311 LD32(p2, DCPLB_DATA7); 312 313X0_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 314 315 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 316 CSYNC; 317 WR_MMR(DCPLB_DATA0, 0, p0, r0); 318 319 // Now check that handler read correct values 320 CHECKREG(r4,0x27); // supv and EXCPT_PROT 321 CHECKREG(r5, 0x10000000); 322 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB7)); 323 CHECKREG_SYM(r7, X0_7, r0); // RETX should be value of X0_7 (HARDCODED ADDR!!) 324 325 //------------------------------------------------------- 326 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 327 328 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 329 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 330 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 331 CSYNC; 332 333 LD32(i1, 0x10000000); 334 R1 = 0x1CFB (Z); 335 LD32(p2, DCPLB_DATA8); 336 337X0_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 338 339 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 340 CSYNC; 341 WR_MMR(DCPLB_DATA0, 0, p0, r0); 342 343 // Now check that handler read correct values 344 CHECKREG(r4,0x27); // supv and EXCPT_PROT 345 CHECKREG(r5, 0x10000000); 346 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB8)); 347 CHECKREG_SYM(r7, X0_8, r0); // RETX should be value of X0_8 (HARDCODED ADDR!!) 348 349 //------------------------------------------------------- 350 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 351 352 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 353 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 354 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 355 CSYNC; 356 357 LD32(i1, 0x10000000); 358 R1 = 0x3F54 (Z); 359 LD32(p2, DCPLB_DATA9); 360 361X0_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 362 363 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 364 CSYNC; 365 WR_MMR(DCPLB_DATA0, 0, p0, r0); 366 367 // Now check that handler read correct values 368 CHECKREG(r4,0x27); // supv and EXCPT_PROT 369 CHECKREG(r5, 0x10000000); 370 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB9)); 371 CHECKREG_SYM(r7, X0_9, r0); // RETX should be value of X0_9 (HARDCODED ADDR!!) 372 373 //------------------------------------------------------- 374 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 375 376 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 377 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 378 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 379 CSYNC; 380 381 LD32(i1, 0x10000000); 382 R1 = 0x0FF6 (Z); 383 LD32(p2, DCPLB_DATA10); 384 385X0_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 386 387 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 388 CSYNC; 389 WR_MMR(DCPLB_DATA0, 0, p0, r0); 390 391 // Now check that handler read correct values 392 CHECKREG(r4,0x27); // supv and EXCPT_PROT 393 CHECKREG(r5, 0x10000000); 394 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB10)); 395 CHECKREG_SYM(r7, X0_10, r0); // RETX should be value of X0_10 (HARDCODED ADDR!!) 396 397 //------------------------------------------------------- 398 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 399 400 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 401 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 402 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 403 CSYNC; 404 405 LD32(i1, 0x10000000); 406 R1 = 0x0ABD (Z); 407 LD32(p2, DCPLB_DATA11); 408 409X0_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 410 411 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 412 CSYNC; 413 WR_MMR(DCPLB_DATA0, 0, p0, r0); 414 415 // Now check that handler read correct values 416 CHECKREG(r4,0x27); // supv and EXCPT_PROT 417 CHECKREG(r5, 0x10000000); 418 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB11)); 419 CHECKREG_SYM(r7, X0_11, r0); // RETX should be value of X0_11 (HARDCODED ADDR!!) 420 421 //------------------------------------------------------- 422 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 423 424 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 425 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 426 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 427 CSYNC; 428 429 LD32(i1, 0x10000000); 430 R1 = 0x31DF (Z); 431 LD32(p2, DCPLB_DATA12); 432 433X0_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 434 435 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 436 CSYNC; 437 WR_MMR(DCPLB_DATA0, 0, p0, r0); 438 439 // Now check that handler read correct values 440 CHECKREG(r4,0x27); // supv and EXCPT_PROT 441 CHECKREG(r5, 0x10000000); 442 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB12)); 443 CHECKREG_SYM(r7, X0_12, r0); // RETX should be value of X0_12 (HARDCODED ADDR!!) 444 445 //------------------------------------------------------- 446 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 447 448 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 449 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 450 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 451 CSYNC; 452 453 LD32(i1, 0x10000000); 454 R1 = 0x237C (Z); 455 LD32(p2, DCPLB_DATA13); 456 457X0_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 458 459 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 460 CSYNC; 461 WR_MMR(DCPLB_DATA0, 0, p0, r0); 462 463 // Now check that handler read correct values 464 CHECKREG(r4,0x27); // supv and EXCPT_PROT 465 CHECKREG(r5, 0x10000000); 466 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB13)); 467 CHECKREG_SYM(r7, X0_13, r0); // RETX should be value of X0_13 (HARDCODED ADDR!!) 468 469 //------------------------------------------------------- 470 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 471 472 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 473 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 474 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 475 CSYNC; 476 477 LD32(i1, 0x10000000); 478 R1 = 0x2F1C (Z); 479 LD32(p2, DCPLB_DATA14); 480 481X0_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 482 483 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 484 CSYNC; 485 WR_MMR(DCPLB_DATA0, 0, p0, r0); 486 487 // Now check that handler read correct values 488 CHECKREG(r4,0x27); // supv and EXCPT_PROT 489 CHECKREG(r5, 0x10000000); 490 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB14)); 491 CHECKREG_SYM(r7, X0_14, r0); // RETX should be value of X0_14 (HARDCODED ADDR!!) 492 493 //------------------------------------------------------- 494 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 495 496 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 497 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 498 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 499 CSYNC; 500 501 LD32(i1, 0x10000000); 502 R1 = 0x7DE1 (Z); 503 LD32(p2, DCPLB_DATA2); 504 505X1_2: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 506 507 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 508 CSYNC; 509 WR_MMR(DCPLB_DATA1, 0, p0, r0); 510 511 // Now check that handler read correct values 512 CHECKREG(r4,0x27); // supv and EXCPT_PROT 513 CHECKREG(r5, 0x10000000); 514 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB2)); 515 CHECKREG_SYM(r7, X1_2, r0); // RETX should be value of X1_2 (HARDCODED ADDR!!) 516 517 //------------------------------------------------------- 518 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 519 520 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 521 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 522 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 523 CSYNC; 524 525 LD32(i1, 0x10000000); 526 R1 = 0x4487 (Z); 527 LD32(p2, DCPLB_DATA3); 528 529X1_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 530 531 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 532 CSYNC; 533 WR_MMR(DCPLB_DATA1, 0, p0, r0); 534 535 // Now check that handler read correct values 536 CHECKREG(r4,0x27); // supv and EXCPT_PROT 537 CHECKREG(r5, 0x10000000); 538 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB3)); 539 CHECKREG_SYM(r7, X1_3, r0); // RETX should be value of X1_3 (HARDCODED ADDR!!) 540 541 //------------------------------------------------------- 542 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 543 544 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 545 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 546 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 547 CSYNC; 548 549 LD32(i1, 0x10000000); 550 R1 = 0x6201 (Z); 551 LD32(p2, DCPLB_DATA4); 552 553X1_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 554 555 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 556 CSYNC; 557 WR_MMR(DCPLB_DATA1, 0, p0, r0); 558 559 // Now check that handler read correct values 560 CHECKREG(r4,0x27); // supv and EXCPT_PROT 561 CHECKREG(r5, 0x10000000); 562 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB4)); 563 CHECKREG_SYM(r7, X1_4, r0); // RETX should be value of X1_4 (HARDCODED ADDR!!) 564 565 //------------------------------------------------------- 566 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 567 568 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 569 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 570 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 571 CSYNC; 572 573 LD32(i1, 0x10000000); 574 R1 = 0x52BF (Z); 575 LD32(p2, DCPLB_DATA5); 576 577X1_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 578 579 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 580 CSYNC; 581 WR_MMR(DCPLB_DATA1, 0, p0, r0); 582 583 // Now check that handler read correct values 584 CHECKREG(r4,0x27); // supv and EXCPT_PROT 585 CHECKREG(r5, 0x10000000); 586 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB5)); 587 CHECKREG_SYM(r7, X1_5, r0); // RETX should be value of X1_5 (HARDCODED ADDR!!) 588 589 //------------------------------------------------------- 590 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 591 592 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 593 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 594 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 595 CSYNC; 596 597 LD32(i1, 0x10000000); 598 R1 = 0x6231 (Z); 599 LD32(p2, DCPLB_DATA6); 600 601X1_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 602 603 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 604 CSYNC; 605 WR_MMR(DCPLB_DATA1, 0, p0, r0); 606 607 // Now check that handler read correct values 608 CHECKREG(r4,0x27); // supv and EXCPT_PROT 609 CHECKREG(r5, 0x10000000); 610 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB6)); 611 CHECKREG_SYM(r7, X1_6, r0); // RETX should be value of X1_6 (HARDCODED ADDR!!) 612 613 //------------------------------------------------------- 614 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 615 616 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 617 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 618 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 619 CSYNC; 620 621 LD32(i1, 0x10000000); 622 R1 = 0x63DE (Z); 623 LD32(p2, DCPLB_DATA7); 624 625X1_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 626 627 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 628 CSYNC; 629 WR_MMR(DCPLB_DATA1, 0, p0, r0); 630 631 // Now check that handler read correct values 632 CHECKREG(r4,0x27); // supv and EXCPT_PROT 633 CHECKREG(r5, 0x10000000); 634 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB7)); 635 CHECKREG_SYM(r7, X1_7, r0); // RETX should be value of X1_7 (HARDCODED ADDR!!) 636 637 //------------------------------------------------------- 638 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 639 640 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 641 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 642 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 643 CSYNC; 644 645 LD32(i1, 0x10000000); 646 R1 = 0x6956 (Z); 647 LD32(p2, DCPLB_DATA8); 648 649X1_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 650 651 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 652 CSYNC; 653 WR_MMR(DCPLB_DATA1, 0, p0, r0); 654 655 // Now check that handler read correct values 656 CHECKREG(r4,0x27); // supv and EXCPT_PROT 657 CHECKREG(r5, 0x10000000); 658 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB8)); 659 CHECKREG_SYM(r7, X1_8, r0); // RETX should be value of X1_8 (HARDCODED ADDR!!) 660 661 //------------------------------------------------------- 662 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 663 664 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 665 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 666 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 667 CSYNC; 668 669 LD32(i1, 0x10000000); 670 R1 = 0x1372 (Z); 671 LD32(p2, DCPLB_DATA9); 672 673X1_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 674 675 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 676 CSYNC; 677 WR_MMR(DCPLB_DATA1, 0, p0, r0); 678 679 // Now check that handler read correct values 680 CHECKREG(r4,0x27); // supv and EXCPT_PROT 681 CHECKREG(r5, 0x10000000); 682 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB9)); 683 CHECKREG_SYM(r7, X1_9, r0); // RETX should be value of X1_9 (HARDCODED ADDR!!) 684 685 //------------------------------------------------------- 686 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 687 688 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 689 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 690 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 691 CSYNC; 692 693 LD32(i1, 0x10000000); 694 R1 = 0x500F (Z); 695 LD32(p2, DCPLB_DATA10); 696 697X1_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 698 699 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 700 CSYNC; 701 WR_MMR(DCPLB_DATA1, 0, p0, r0); 702 703 // Now check that handler read correct values 704 CHECKREG(r4,0x27); // supv and EXCPT_PROT 705 CHECKREG(r5, 0x10000000); 706 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB10)); 707 CHECKREG_SYM(r7, X1_10, r0); // RETX should be value of X1_10 (HARDCODED ADDR!!) 708 709 //------------------------------------------------------- 710 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 711 712 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 713 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 714 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 715 CSYNC; 716 717 LD32(i1, 0x10000000); 718 R1 = 0x2847 (Z); 719 LD32(p2, DCPLB_DATA11); 720 721X1_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 722 723 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 724 CSYNC; 725 WR_MMR(DCPLB_DATA1, 0, p0, r0); 726 727 // Now check that handler read correct values 728 CHECKREG(r4,0x27); // supv and EXCPT_PROT 729 CHECKREG(r5, 0x10000000); 730 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB11)); 731 CHECKREG_SYM(r7, X1_11, r0); // RETX should be value of X1_11 (HARDCODED ADDR!!) 732 733 //------------------------------------------------------- 734 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 735 736 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 737 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 738 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 739 CSYNC; 740 741 LD32(i1, 0x10000000); 742 R1 = 0x2C67 (Z); 743 LD32(p2, DCPLB_DATA12); 744 745X1_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 746 747 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 748 CSYNC; 749 WR_MMR(DCPLB_DATA1, 0, p0, r0); 750 751 // Now check that handler read correct values 752 CHECKREG(r4,0x27); // supv and EXCPT_PROT 753 CHECKREG(r5, 0x10000000); 754 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB12)); 755 CHECKREG_SYM(r7, X1_12, r0); // RETX should be value of X1_12 (HARDCODED ADDR!!) 756 757 //------------------------------------------------------- 758 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 759 760 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 761 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 762 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 763 CSYNC; 764 765 LD32(i1, 0x10000000); 766 R1 = 0x7566 (Z); 767 LD32(p2, DCPLB_DATA13); 768 769X1_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 770 771 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 772 CSYNC; 773 WR_MMR(DCPLB_DATA1, 0, p0, r0); 774 775 // Now check that handler read correct values 776 CHECKREG(r4,0x27); // supv and EXCPT_PROT 777 CHECKREG(r5, 0x10000000); 778 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB13)); 779 CHECKREG_SYM(r7, X1_13, r0); // RETX should be value of X1_13 (HARDCODED ADDR!!) 780 781 //------------------------------------------------------- 782 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 783 784 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 785 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 786 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 787 CSYNC; 788 789 LD32(i1, 0x10000000); 790 R1 = 0x4287 (Z); 791 LD32(p2, DCPLB_DATA14); 792 793X1_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 794 795 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 796 CSYNC; 797 WR_MMR(DCPLB_DATA1, 0, p0, r0); 798 799 // Now check that handler read correct values 800 CHECKREG(r4,0x27); // supv and EXCPT_PROT 801 CHECKREG(r5, 0x10000000); 802 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB14)); 803 CHECKREG_SYM(r7, X1_14, r0); // RETX should be value of X1_14 (HARDCODED ADDR!!) 804 805 //------------------------------------------------------- 806 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 807 808 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 809 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 810 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 811 CSYNC; 812 813 LD32(i1, 0x10000000); 814 R1 = 0x3359 (Z); 815 LD32(p2, DCPLB_DATA3); 816 817X2_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 818 819 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 820 CSYNC; 821 WR_MMR(DCPLB_DATA2, 0, p0, r0); 822 823 // Now check that handler read correct values 824 CHECKREG(r4,0x27); // supv and EXCPT_PROT 825 CHECKREG(r5, 0x10000000); 826 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB3)); 827 CHECKREG_SYM(r7, X2_3, r0); // RETX should be value of X2_3 (HARDCODED ADDR!!) 828 829 //------------------------------------------------------- 830 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 831 832 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 833 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 834 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 835 CSYNC; 836 837 LD32(i1, 0x10000000); 838 R1 = 0x4DAA (Z); 839 LD32(p2, DCPLB_DATA4); 840 841X2_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 842 843 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 844 CSYNC; 845 WR_MMR(DCPLB_DATA2, 0, p0, r0); 846 847 // Now check that handler read correct values 848 CHECKREG(r4,0x27); // supv and EXCPT_PROT 849 CHECKREG(r5, 0x10000000); 850 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB4)); 851 CHECKREG_SYM(r7, X2_4, r0); // RETX should be value of X2_4 (HARDCODED ADDR!!) 852 853 //------------------------------------------------------- 854 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 855 856 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 857 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 858 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 859 CSYNC; 860 861 LD32(i1, 0x10000000); 862 R1 = 0x6488 (Z); 863 LD32(p2, DCPLB_DATA5); 864 865X2_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 866 867 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 868 CSYNC; 869 WR_MMR(DCPLB_DATA2, 0, p0, r0); 870 871 // Now check that handler read correct values 872 CHECKREG(r4,0x27); // supv and EXCPT_PROT 873 CHECKREG(r5, 0x10000000); 874 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB5)); 875 CHECKREG_SYM(r7, X2_5, r0); // RETX should be value of X2_5 (HARDCODED ADDR!!) 876 877 //------------------------------------------------------- 878 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 879 880 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 881 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 882 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 883 CSYNC; 884 885 LD32(i1, 0x10000000); 886 R1 = 0x773C (Z); 887 LD32(p2, DCPLB_DATA6); 888 889X2_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 890 891 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 892 CSYNC; 893 WR_MMR(DCPLB_DATA2, 0, p0, r0); 894 895 // Now check that handler read correct values 896 CHECKREG(r4,0x27); // supv and EXCPT_PROT 897 CHECKREG(r5, 0x10000000); 898 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB6)); 899 CHECKREG_SYM(r7, X2_6, r0); // RETX should be value of X2_6 (HARDCODED ADDR!!) 900 901 //------------------------------------------------------- 902 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 903 904 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 905 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 906 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 907 CSYNC; 908 909 LD32(i1, 0x10000000); 910 R1 = 0x6F59 (Z); 911 LD32(p2, DCPLB_DATA7); 912 913X2_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 914 915 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 916 CSYNC; 917 WR_MMR(DCPLB_DATA2, 0, p0, r0); 918 919 // Now check that handler read correct values 920 CHECKREG(r4,0x27); // supv and EXCPT_PROT 921 CHECKREG(r5, 0x10000000); 922 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB7)); 923 CHECKREG_SYM(r7, X2_7, r0); // RETX should be value of X2_7 (HARDCODED ADDR!!) 924 925 //------------------------------------------------------- 926 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 927 928 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 929 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 930 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 931 CSYNC; 932 933 LD32(i1, 0x10000000); 934 R1 = 0x6EEA (Z); 935 LD32(p2, DCPLB_DATA8); 936 937X2_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 938 939 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 940 CSYNC; 941 WR_MMR(DCPLB_DATA2, 0, p0, r0); 942 943 // Now check that handler read correct values 944 CHECKREG(r4,0x27); // supv and EXCPT_PROT 945 CHECKREG(r5, 0x10000000); 946 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB8)); 947 CHECKREG_SYM(r7, X2_8, r0); // RETX should be value of X2_8 (HARDCODED ADDR!!) 948 949 //------------------------------------------------------- 950 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 951 952 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 953 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 954 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 955 CSYNC; 956 957 LD32(i1, 0x10000000); 958 R1 = 0x5656 (Z); 959 LD32(p2, DCPLB_DATA9); 960 961X2_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 962 963 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 964 CSYNC; 965 WR_MMR(DCPLB_DATA2, 0, p0, r0); 966 967 // Now check that handler read correct values 968 CHECKREG(r4,0x27); // supv and EXCPT_PROT 969 CHECKREG(r5, 0x10000000); 970 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB9)); 971 CHECKREG_SYM(r7, X2_9, r0); // RETX should be value of X2_9 (HARDCODED ADDR!!) 972 973 //------------------------------------------------------- 974 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 975 976 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 977 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 978 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 979 CSYNC; 980 981 LD32(i1, 0x10000000); 982 R1 = 0x6113 (Z); 983 LD32(p2, DCPLB_DATA10); 984 985X2_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 986 987 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 988 CSYNC; 989 WR_MMR(DCPLB_DATA2, 0, p0, r0); 990 991 // Now check that handler read correct values 992 CHECKREG(r4,0x27); // supv and EXCPT_PROT 993 CHECKREG(r5, 0x10000000); 994 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB10)); 995 CHECKREG_SYM(r7, X2_10, r0); // RETX should be value of X2_10 (HARDCODED ADDR!!) 996 997 //------------------------------------------------------- 998 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 999 1000 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1001 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1002 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1003 CSYNC; 1004 1005 LD32(i1, 0x10000000); 1006 R1 = 0x4A7B (Z); 1007 LD32(p2, DCPLB_DATA11); 1008 1009X2_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1010 1011 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1012 CSYNC; 1013 WR_MMR(DCPLB_DATA2, 0, p0, r0); 1014 1015 // Now check that handler read correct values 1016 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1017 CHECKREG(r5, 0x10000000); 1018 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB11)); 1019 CHECKREG_SYM(r7, X2_11, r0); // RETX should be value of X2_11 (HARDCODED ADDR!!) 1020 1021 //------------------------------------------------------- 1022 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1023 1024 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1025 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1026 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1027 CSYNC; 1028 1029 LD32(i1, 0x10000000); 1030 R1 = 0x31D2 (Z); 1031 LD32(p2, DCPLB_DATA12); 1032 1033X2_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1034 1035 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1036 CSYNC; 1037 WR_MMR(DCPLB_DATA2, 0, p0, r0); 1038 1039 // Now check that handler read correct values 1040 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1041 CHECKREG(r5, 0x10000000); 1042 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB12)); 1043 CHECKREG_SYM(r7, X2_12, r0); // RETX should be value of X2_12 (HARDCODED ADDR!!) 1044 1045 //------------------------------------------------------- 1046 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1047 1048 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1049 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1050 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1051 CSYNC; 1052 1053 LD32(i1, 0x10000000); 1054 R1 = 0x2D85 (Z); 1055 LD32(p2, DCPLB_DATA13); 1056 1057X2_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1058 1059 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1060 CSYNC; 1061 WR_MMR(DCPLB_DATA2, 0, p0, r0); 1062 1063 // Now check that handler read correct values 1064 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1065 CHECKREG(r5, 0x10000000); 1066 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB13)); 1067 CHECKREG_SYM(r7, X2_13, r0); // RETX should be value of X2_13 (HARDCODED ADDR!!) 1068 1069 //------------------------------------------------------- 1070 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1071 1072 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1073 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1074 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1075 CSYNC; 1076 1077 LD32(i1, 0x10000000); 1078 R1 = 0x19A1 (Z); 1079 LD32(p2, DCPLB_DATA14); 1080 1081X2_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1082 1083 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1084 CSYNC; 1085 WR_MMR(DCPLB_DATA2, 0, p0, r0); 1086 1087 // Now check that handler read correct values 1088 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1089 CHECKREG(r5, 0x10000000); 1090 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB14)); 1091 CHECKREG_SYM(r7, X2_14, r0); // RETX should be value of X2_14 (HARDCODED ADDR!!) 1092 1093 //------------------------------------------------------- 1094 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1095 1096 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1097 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1098 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1099 CSYNC; 1100 1101 LD32(i1, 0x10000000); 1102 R1 = 0x69D8 (Z); 1103 LD32(p2, DCPLB_DATA4); 1104 1105X3_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1106 1107 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1108 CSYNC; 1109 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1110 1111 // Now check that handler read correct values 1112 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1113 CHECKREG(r5, 0x10000000); 1114 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB4)); 1115 CHECKREG_SYM(r7, X3_4, r0); // RETX should be value of X3_4 (HARDCODED ADDR!!) 1116 1117 //------------------------------------------------------- 1118 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1119 1120 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1121 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1122 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1123 CSYNC; 1124 1125 LD32(i1, 0x10000000); 1126 R1 = 0x353C (Z); 1127 LD32(p2, DCPLB_DATA5); 1128 1129X3_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1130 1131 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1132 CSYNC; 1133 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1134 1135 // Now check that handler read correct values 1136 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1137 CHECKREG(r5, 0x10000000); 1138 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB5)); 1139 CHECKREG_SYM(r7, X3_5, r0); // RETX should be value of X3_5 (HARDCODED ADDR!!) 1140 1141 //------------------------------------------------------- 1142 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1143 1144 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1145 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1146 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1147 CSYNC; 1148 1149 LD32(i1, 0x10000000); 1150 R1 = 0x3B54 (Z); 1151 LD32(p2, DCPLB_DATA6); 1152 1153X3_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1154 1155 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1156 CSYNC; 1157 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1158 1159 // Now check that handler read correct values 1160 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1161 CHECKREG(r5, 0x10000000); 1162 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB6)); 1163 CHECKREG_SYM(r7, X3_6, r0); // RETX should be value of X3_6 (HARDCODED ADDR!!) 1164 1165 //------------------------------------------------------- 1166 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1167 1168 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1169 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1170 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1171 CSYNC; 1172 1173 LD32(i1, 0x10000000); 1174 R1 = 0x7D55 (Z); 1175 LD32(p2, DCPLB_DATA7); 1176 1177X3_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1178 1179 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1180 CSYNC; 1181 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1182 1183 // Now check that handler read correct values 1184 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1185 CHECKREG(r5, 0x10000000); 1186 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB7)); 1187 CHECKREG_SYM(r7, X3_7, r0); // RETX should be value of X3_7 (HARDCODED ADDR!!) 1188 1189 //------------------------------------------------------- 1190 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1191 1192 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1193 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1194 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1195 CSYNC; 1196 1197 LD32(i1, 0x10000000); 1198 R1 = 0x102F (Z); 1199 LD32(p2, DCPLB_DATA8); 1200 1201X3_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1202 1203 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1204 CSYNC; 1205 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1206 1207 // Now check that handler read correct values 1208 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1209 CHECKREG(r5, 0x10000000); 1210 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB8)); 1211 CHECKREG_SYM(r7, X3_8, r0); // RETX should be value of X3_8 (HARDCODED ADDR!!) 1212 1213 //------------------------------------------------------- 1214 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1215 1216 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1217 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1218 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1219 CSYNC; 1220 1221 LD32(i1, 0x10000000); 1222 R1 = 0x1B37 (Z); 1223 LD32(p2, DCPLB_DATA9); 1224 1225X3_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1226 1227 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1228 CSYNC; 1229 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1230 1231 // Now check that handler read correct values 1232 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1233 CHECKREG(r5, 0x10000000); 1234 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB9)); 1235 CHECKREG_SYM(r7, X3_9, r0); // RETX should be value of X3_9 (HARDCODED ADDR!!) 1236 1237 //------------------------------------------------------- 1238 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1239 1240 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1241 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1242 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1243 CSYNC; 1244 1245 LD32(i1, 0x10000000); 1246 R1 = 0x7AAE (Z); 1247 LD32(p2, DCPLB_DATA10); 1248 1249X3_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1250 1251 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1252 CSYNC; 1253 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1254 1255 // Now check that handler read correct values 1256 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1257 CHECKREG(r5, 0x10000000); 1258 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB10)); 1259 CHECKREG_SYM(r7, X3_10, r0); // RETX should be value of X3_10 (HARDCODED ADDR!!) 1260 1261 //------------------------------------------------------- 1262 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1263 1264 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1265 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1266 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1267 CSYNC; 1268 1269 LD32(i1, 0x10000000); 1270 R1 = 0x5E65 (Z); 1271 LD32(p2, DCPLB_DATA11); 1272 1273X3_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1274 1275 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1276 CSYNC; 1277 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1278 1279 // Now check that handler read correct values 1280 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1281 CHECKREG(r5, 0x10000000); 1282 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB11)); 1283 CHECKREG_SYM(r7, X3_11, r0); // RETX should be value of X3_11 (HARDCODED ADDR!!) 1284 1285 //------------------------------------------------------- 1286 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1287 1288 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1289 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1290 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1291 CSYNC; 1292 1293 LD32(i1, 0x10000000); 1294 R1 = 0x345B (Z); 1295 LD32(p2, DCPLB_DATA12); 1296 1297X3_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1298 1299 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1300 CSYNC; 1301 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1302 1303 // Now check that handler read correct values 1304 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1305 CHECKREG(r5, 0x10000000); 1306 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB12)); 1307 CHECKREG_SYM(r7, X3_12, r0); // RETX should be value of X3_12 (HARDCODED ADDR!!) 1308 1309 //------------------------------------------------------- 1310 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1311 1312 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1313 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1314 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1315 CSYNC; 1316 1317 LD32(i1, 0x10000000); 1318 R1 = 0x63DA (Z); 1319 LD32(p2, DCPLB_DATA13); 1320 1321X3_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1322 1323 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1324 CSYNC; 1325 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1326 1327 // Now check that handler read correct values 1328 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1329 CHECKREG(r5, 0x10000000); 1330 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB13)); 1331 CHECKREG_SYM(r7, X3_13, r0); // RETX should be value of X3_13 (HARDCODED ADDR!!) 1332 1333 //------------------------------------------------------- 1334 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1335 1336 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1337 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1338 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1339 CSYNC; 1340 1341 LD32(i1, 0x10000000); 1342 R1 = 0x6102 (Z); 1343 LD32(p2, DCPLB_DATA14); 1344 1345X3_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1346 1347 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1348 CSYNC; 1349 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1350 1351 // Now check that handler read correct values 1352 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1353 CHECKREG(r5, 0x10000000); 1354 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB14)); 1355 CHECKREG_SYM(r7, X3_14, r0); // RETX should be value of X3_14 (HARDCODED ADDR!!) 1356 1357 //------------------------------------------------------- 1358 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1359 1360 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1361 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1362 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1363 CSYNC; 1364 1365 LD32(i1, 0x10000000); 1366 R1 = 0x7A79 (Z); 1367 LD32(p2, DCPLB_DATA5); 1368 1369X4_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1370 1371 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1372 CSYNC; 1373 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1374 1375 // Now check that handler read correct values 1376 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1377 CHECKREG(r5, 0x10000000); 1378 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB5)); 1379 CHECKREG_SYM(r7, X4_5, r0); // RETX should be value of X4_5 (HARDCODED ADDR!!) 1380 1381 //------------------------------------------------------- 1382 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1383 1384 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1385 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1386 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1387 CSYNC; 1388 1389 LD32(i1, 0x10000000); 1390 R1 = 0x0398 (Z); 1391 LD32(p2, DCPLB_DATA6); 1392 1393X4_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1394 1395 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1396 CSYNC; 1397 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1398 1399 // Now check that handler read correct values 1400 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1401 CHECKREG(r5, 0x10000000); 1402 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB6)); 1403 CHECKREG_SYM(r7, X4_6, r0); // RETX should be value of X4_6 (HARDCODED ADDR!!) 1404 1405 //------------------------------------------------------- 1406 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1407 1408 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1409 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1410 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1411 CSYNC; 1412 1413 LD32(i1, 0x10000000); 1414 R1 = 0x28CC (Z); 1415 LD32(p2, DCPLB_DATA7); 1416 1417X4_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1418 1419 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1420 CSYNC; 1421 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1422 1423 // Now check that handler read correct values 1424 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1425 CHECKREG(r5, 0x10000000); 1426 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB7)); 1427 CHECKREG_SYM(r7, X4_7, r0); // RETX should be value of X4_7 (HARDCODED ADDR!!) 1428 1429 //------------------------------------------------------- 1430 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1431 1432 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1433 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1434 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1435 CSYNC; 1436 1437 LD32(i1, 0x10000000); 1438 R1 = 0x60E3 (Z); 1439 LD32(p2, DCPLB_DATA8); 1440 1441X4_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1442 1443 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1444 CSYNC; 1445 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1446 1447 // Now check that handler read correct values 1448 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1449 CHECKREG(r5, 0x10000000); 1450 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB8)); 1451 CHECKREG_SYM(r7, X4_8, r0); // RETX should be value of X4_8 (HARDCODED ADDR!!) 1452 1453 //------------------------------------------------------- 1454 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1455 1456 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1457 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1458 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1459 CSYNC; 1460 1461 LD32(i1, 0x10000000); 1462 R1 = 0x1F1A (Z); 1463 LD32(p2, DCPLB_DATA9); 1464 1465X4_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1466 1467 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1468 CSYNC; 1469 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1470 1471 // Now check that handler read correct values 1472 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1473 CHECKREG(r5, 0x10000000); 1474 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB9)); 1475 CHECKREG_SYM(r7, X4_9, r0); // RETX should be value of X4_9 (HARDCODED ADDR!!) 1476 1477 //------------------------------------------------------- 1478 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1479 1480 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1481 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1482 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1483 CSYNC; 1484 1485 LD32(i1, 0x10000000); 1486 R1 = 0x4B76 (Z); 1487 LD32(p2, DCPLB_DATA10); 1488 1489X4_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1490 1491 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1492 CSYNC; 1493 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1494 1495 // Now check that handler read correct values 1496 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1497 CHECKREG(r5, 0x10000000); 1498 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB10)); 1499 CHECKREG_SYM(r7, X4_10, r0); // RETX should be value of X4_10 (HARDCODED ADDR!!) 1500 1501 //------------------------------------------------------- 1502 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1503 1504 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1505 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1506 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1507 CSYNC; 1508 1509 LD32(i1, 0x10000000); 1510 R1 = 0x058E (Z); 1511 LD32(p2, DCPLB_DATA11); 1512 1513X4_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1514 1515 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1516 CSYNC; 1517 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1518 1519 // Now check that handler read correct values 1520 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1521 CHECKREG(r5, 0x10000000); 1522 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB11)); 1523 CHECKREG_SYM(r7, X4_11, r0); // RETX should be value of X4_11 (HARDCODED ADDR!!) 1524 1525 //------------------------------------------------------- 1526 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1527 1528 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1529 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1530 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1531 CSYNC; 1532 1533 LD32(i1, 0x10000000); 1534 R1 = 0x7A5F (Z); 1535 LD32(p2, DCPLB_DATA12); 1536 1537X4_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1538 1539 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1540 CSYNC; 1541 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1542 1543 // Now check that handler read correct values 1544 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1545 CHECKREG(r5, 0x10000000); 1546 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB12)); 1547 CHECKREG_SYM(r7, X4_12, r0); // RETX should be value of X4_12 (HARDCODED ADDR!!) 1548 1549 //------------------------------------------------------- 1550 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1551 1552 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1553 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1554 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1555 CSYNC; 1556 1557 LD32(i1, 0x10000000); 1558 R1 = 0x28D9 (Z); 1559 LD32(p2, DCPLB_DATA13); 1560 1561X4_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1562 1563 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1564 CSYNC; 1565 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1566 1567 // Now check that handler read correct values 1568 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1569 CHECKREG(r5, 0x10000000); 1570 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB13)); 1571 CHECKREG_SYM(r7, X4_13, r0); // RETX should be value of X4_13 (HARDCODED ADDR!!) 1572 1573 //------------------------------------------------------- 1574 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1575 1576 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1577 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1578 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1579 CSYNC; 1580 1581 LD32(i1, 0x10000000); 1582 R1 = 0x0799 (Z); 1583 LD32(p2, DCPLB_DATA14); 1584 1585X4_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1586 1587 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1588 CSYNC; 1589 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1590 1591 // Now check that handler read correct values 1592 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1593 CHECKREG(r5, 0x10000000); 1594 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB14)); 1595 CHECKREG_SYM(r7, X4_14, r0); // RETX should be value of X4_14 (HARDCODED ADDR!!) 1596 1597 //------------------------------------------------------- 1598 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1599 1600 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1601 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1602 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1603 CSYNC; 1604 1605 LD32(i1, 0x10000000); 1606 R1 = 0x388F (Z); 1607 LD32(p2, DCPLB_DATA6); 1608 1609X5_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1610 1611 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1612 CSYNC; 1613 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1614 1615 // Now check that handler read correct values 1616 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1617 CHECKREG(r5, 0x10000000); 1618 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB6)); 1619 CHECKREG_SYM(r7, X5_6, r0); // RETX should be value of X5_6 (HARDCODED ADDR!!) 1620 1621 //------------------------------------------------------- 1622 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1623 1624 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1625 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1626 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1627 CSYNC; 1628 1629 LD32(i1, 0x10000000); 1630 R1 = 0x751F (Z); 1631 LD32(p2, DCPLB_DATA7); 1632 1633X5_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1634 1635 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1636 CSYNC; 1637 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1638 1639 // Now check that handler read correct values 1640 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1641 CHECKREG(r5, 0x10000000); 1642 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB7)); 1643 CHECKREG_SYM(r7, X5_7, r0); // RETX should be value of X5_7 (HARDCODED ADDR!!) 1644 1645 //------------------------------------------------------- 1646 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1647 1648 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1649 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1650 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1651 CSYNC; 1652 1653 LD32(i1, 0x10000000); 1654 R1 = 0x493F (Z); 1655 LD32(p2, DCPLB_DATA8); 1656 1657X5_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1658 1659 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1660 CSYNC; 1661 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1662 1663 // Now check that handler read correct values 1664 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1665 CHECKREG(r5, 0x10000000); 1666 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB8)); 1667 CHECKREG_SYM(r7, X5_8, r0); // RETX should be value of X5_8 (HARDCODED ADDR!!) 1668 1669 //------------------------------------------------------- 1670 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1671 1672 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1673 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1674 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1675 CSYNC; 1676 1677 LD32(i1, 0x10000000); 1678 R1 = 0x0F36 (Z); 1679 LD32(p2, DCPLB_DATA9); 1680 1681X5_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1682 1683 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1684 CSYNC; 1685 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1686 1687 // Now check that handler read correct values 1688 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1689 CHECKREG(r5, 0x10000000); 1690 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB9)); 1691 CHECKREG_SYM(r7, X5_9, r0); // RETX should be value of X5_9 (HARDCODED ADDR!!) 1692 1693 //------------------------------------------------------- 1694 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1695 1696 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1697 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1698 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1699 CSYNC; 1700 1701 LD32(i1, 0x10000000); 1702 R1 = 0x48EE (Z); 1703 LD32(p2, DCPLB_DATA10); 1704 1705X5_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1706 1707 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1708 CSYNC; 1709 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1710 1711 // Now check that handler read correct values 1712 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1713 CHECKREG(r5, 0x10000000); 1714 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB10)); 1715 CHECKREG_SYM(r7, X5_10, r0); // RETX should be value of X5_10 (HARDCODED ADDR!!) 1716 1717 //------------------------------------------------------- 1718 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1719 1720 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1721 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1722 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1723 CSYNC; 1724 1725 LD32(i1, 0x10000000); 1726 R1 = 0x2043 (Z); 1727 LD32(p2, DCPLB_DATA11); 1728 1729X5_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1730 1731 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1732 CSYNC; 1733 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1734 1735 // Now check that handler read correct values 1736 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1737 CHECKREG(r5, 0x10000000); 1738 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB11)); 1739 CHECKREG_SYM(r7, X5_11, r0); // RETX should be value of X5_11 (HARDCODED ADDR!!) 1740 1741 //------------------------------------------------------- 1742 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1743 1744 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1745 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1746 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1747 CSYNC; 1748 1749 LD32(i1, 0x10000000); 1750 R1 = 0x3F78 (Z); 1751 LD32(p2, DCPLB_DATA12); 1752 1753X5_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1754 1755 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1756 CSYNC; 1757 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1758 1759 // Now check that handler read correct values 1760 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1761 CHECKREG(r5, 0x10000000); 1762 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB12)); 1763 CHECKREG_SYM(r7, X5_12, r0); // RETX should be value of X5_12 (HARDCODED ADDR!!) 1764 1765 //------------------------------------------------------- 1766 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1767 1768 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1769 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1770 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1771 CSYNC; 1772 1773 LD32(i1, 0x10000000); 1774 R1 = 0x1E4D (Z); 1775 LD32(p2, DCPLB_DATA13); 1776 1777X5_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1778 1779 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1780 CSYNC; 1781 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1782 1783 // Now check that handler read correct values 1784 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1785 CHECKREG(r5, 0x10000000); 1786 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB13)); 1787 CHECKREG_SYM(r7, X5_13, r0); // RETX should be value of X5_13 (HARDCODED ADDR!!) 1788 1789 //------------------------------------------------------- 1790 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1791 1792 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1793 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1794 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1795 CSYNC; 1796 1797 LD32(i1, 0x10000000); 1798 R1 = 0x3D0D (Z); 1799 LD32(p2, DCPLB_DATA14); 1800 1801X5_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1802 1803 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1804 CSYNC; 1805 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1806 1807 // Now check that handler read correct values 1808 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1809 CHECKREG(r5, 0x10000000); 1810 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB14)); 1811 CHECKREG_SYM(r7, X5_14, r0); // RETX should be value of X5_14 (HARDCODED ADDR!!) 1812 1813 //------------------------------------------------------- 1814 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1815 1816 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1817 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1818 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1819 CSYNC; 1820 1821 LD32(i1, 0x10000000); 1822 R1 = 0x33FA (Z); 1823 LD32(p2, DCPLB_DATA7); 1824 1825X6_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1826 1827 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1828 CSYNC; 1829 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1830 1831 // Now check that handler read correct values 1832 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1833 CHECKREG(r5, 0x10000000); 1834 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB7)); 1835 CHECKREG_SYM(r7, X6_7, r0); // RETX should be value of X6_7 (HARDCODED ADDR!!) 1836 1837 //------------------------------------------------------- 1838 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1839 1840 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1841 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1842 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1843 CSYNC; 1844 1845 LD32(i1, 0x10000000); 1846 R1 = 0x6FBE (Z); 1847 LD32(p2, DCPLB_DATA8); 1848 1849X6_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1850 1851 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1852 CSYNC; 1853 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1854 1855 // Now check that handler read correct values 1856 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1857 CHECKREG(r5, 0x10000000); 1858 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB8)); 1859 CHECKREG_SYM(r7, X6_8, r0); // RETX should be value of X6_8 (HARDCODED ADDR!!) 1860 1861 //------------------------------------------------------- 1862 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1863 1864 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1865 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1866 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1867 CSYNC; 1868 1869 LD32(i1, 0x10000000); 1870 R1 = 0x36A6 (Z); 1871 LD32(p2, DCPLB_DATA9); 1872 1873X6_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1874 1875 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1876 CSYNC; 1877 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1878 1879 // Now check that handler read correct values 1880 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1881 CHECKREG(r5, 0x10000000); 1882 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB9)); 1883 CHECKREG_SYM(r7, X6_9, r0); // RETX should be value of X6_9 (HARDCODED ADDR!!) 1884 1885 //------------------------------------------------------- 1886 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1887 1888 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1889 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1890 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1891 CSYNC; 1892 1893 LD32(i1, 0x10000000); 1894 R1 = 0x2DDA (Z); 1895 LD32(p2, DCPLB_DATA10); 1896 1897X6_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1898 1899 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1900 CSYNC; 1901 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1902 1903 // Now check that handler read correct values 1904 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1905 CHECKREG(r5, 0x10000000); 1906 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB10)); 1907 CHECKREG_SYM(r7, X6_10, r0); // RETX should be value of X6_10 (HARDCODED ADDR!!) 1908 1909 //------------------------------------------------------- 1910 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1911 1912 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1913 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1914 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1915 CSYNC; 1916 1917 LD32(i1, 0x10000000); 1918 R1 = 0x30E4 (Z); 1919 LD32(p2, DCPLB_DATA11); 1920 1921X6_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1922 1923 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1924 CSYNC; 1925 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1926 1927 // Now check that handler read correct values 1928 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1929 CHECKREG(r5, 0x10000000); 1930 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB11)); 1931 CHECKREG_SYM(r7, X6_11, r0); // RETX should be value of X6_11 (HARDCODED ADDR!!) 1932 1933 //------------------------------------------------------- 1934 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1935 1936 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1937 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1938 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1939 CSYNC; 1940 1941 LD32(i1, 0x10000000); 1942 R1 = 0x0586 (Z); 1943 LD32(p2, DCPLB_DATA12); 1944 1945X6_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1946 1947 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1948 CSYNC; 1949 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1950 1951 // Now check that handler read correct values 1952 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1953 CHECKREG(r5, 0x10000000); 1954 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB12)); 1955 CHECKREG_SYM(r7, X6_12, r0); // RETX should be value of X6_12 (HARDCODED ADDR!!) 1956 1957 //------------------------------------------------------- 1958 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1959 1960 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1961 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1962 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1963 CSYNC; 1964 1965 LD32(i1, 0x10000000); 1966 R1 = 0x148E (Z); 1967 LD32(p2, DCPLB_DATA13); 1968 1969X6_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1970 1971 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1972 CSYNC; 1973 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1974 1975 // Now check that handler read correct values 1976 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1977 CHECKREG(r5, 0x10000000); 1978 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB13)); 1979 CHECKREG_SYM(r7, X6_13, r0); // RETX should be value of X6_13 (HARDCODED ADDR!!) 1980 1981 //------------------------------------------------------- 1982 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1983 1984 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1985 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1986 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1987 CSYNC; 1988 1989 LD32(i1, 0x10000000); 1990 R1 = 0x42DC (Z); 1991 LD32(p2, DCPLB_DATA14); 1992 1993X6_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 1994 1995 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1996 CSYNC; 1997 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1998 1999 // Now check that handler read correct values 2000 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2001 CHECKREG(r5, 0x10000000); 2002 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB14)); 2003 CHECKREG_SYM(r7, X6_14, r0); // RETX should be value of X6_14 (HARDCODED ADDR!!) 2004 2005 //------------------------------------------------------- 2006 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2007 2008 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2009 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2010 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2011 CSYNC; 2012 2013 LD32(i1, 0x10000000); 2014 R1 = 0x5929 (Z); 2015 LD32(p2, DCPLB_DATA8); 2016 2017X7_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2018 2019 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2020 CSYNC; 2021 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2022 2023 // Now check that handler read correct values 2024 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2025 CHECKREG(r5, 0x10000000); 2026 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB8)); 2027 CHECKREG_SYM(r7, X7_8, r0); // RETX should be value of X7_8 (HARDCODED ADDR!!) 2028 2029 //------------------------------------------------------- 2030 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2031 2032 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2033 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2034 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2035 CSYNC; 2036 2037 LD32(i1, 0x10000000); 2038 R1 = 0x0C6D (Z); 2039 LD32(p2, DCPLB_DATA9); 2040 2041X7_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2042 2043 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2044 CSYNC; 2045 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2046 2047 // Now check that handler read correct values 2048 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2049 CHECKREG(r5, 0x10000000); 2050 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB9)); 2051 CHECKREG_SYM(r7, X7_9, r0); // RETX should be value of X7_9 (HARDCODED ADDR!!) 2052 2053 //------------------------------------------------------- 2054 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2055 2056 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2057 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2058 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2059 CSYNC; 2060 2061 LD32(i1, 0x10000000); 2062 R1 = 0x334E (Z); 2063 LD32(p2, DCPLB_DATA10); 2064 2065X7_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2066 2067 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2068 CSYNC; 2069 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2070 2071 // Now check that handler read correct values 2072 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2073 CHECKREG(r5, 0x10000000); 2074 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB10)); 2075 CHECKREG_SYM(r7, X7_10, r0); // RETX should be value of X7_10 (HARDCODED ADDR!!) 2076 2077 //------------------------------------------------------- 2078 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2079 2080 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2081 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2082 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2083 CSYNC; 2084 2085 LD32(i1, 0x10000000); 2086 R1 = 0x62FF (Z); 2087 LD32(p2, DCPLB_DATA11); 2088 2089X7_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2090 2091 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2092 CSYNC; 2093 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2094 2095 // Now check that handler read correct values 2096 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2097 CHECKREG(r5, 0x10000000); 2098 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB11)); 2099 CHECKREG_SYM(r7, X7_11, r0); // RETX should be value of X7_11 (HARDCODED ADDR!!) 2100 2101 //------------------------------------------------------- 2102 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2103 2104 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2105 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2106 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2107 CSYNC; 2108 2109 LD32(i1, 0x10000000); 2110 R1 = 0x1F56 (Z); 2111 LD32(p2, DCPLB_DATA12); 2112 2113X7_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2114 2115 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2116 CSYNC; 2117 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2118 2119 // Now check that handler read correct values 2120 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2121 CHECKREG(r5, 0x10000000); 2122 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB12)); 2123 CHECKREG_SYM(r7, X7_12, r0); // RETX should be value of X7_12 (HARDCODED ADDR!!) 2124 2125 //------------------------------------------------------- 2126 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2127 2128 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2129 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2130 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2131 CSYNC; 2132 2133 LD32(i1, 0x10000000); 2134 R1 = 0x2BE1 (Z); 2135 LD32(p2, DCPLB_DATA13); 2136 2137X7_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2138 2139 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2140 CSYNC; 2141 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2142 2143 // Now check that handler read correct values 2144 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2145 CHECKREG(r5, 0x10000000); 2146 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB13)); 2147 CHECKREG_SYM(r7, X7_13, r0); // RETX should be value of X7_13 (HARDCODED ADDR!!) 2148 2149 //------------------------------------------------------- 2150 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2151 2152 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2153 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2154 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2155 CSYNC; 2156 2157 LD32(i1, 0x10000000); 2158 R1 = 0x1D70 (Z); 2159 LD32(p2, DCPLB_DATA14); 2160 2161X7_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2162 2163 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2164 CSYNC; 2165 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2166 2167 // Now check that handler read correct values 2168 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2169 CHECKREG(r5, 0x10000000); 2170 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB14)); 2171 CHECKREG_SYM(r7, X7_14, r0); // RETX should be value of X7_14 (HARDCODED ADDR!!) 2172 2173 //------------------------------------------------------- 2174 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2175 2176 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2177 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2178 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2179 CSYNC; 2180 2181 LD32(i1, 0x10000000); 2182 R1 = 0x2620 (Z); 2183 LD32(p2, DCPLB_DATA9); 2184 2185X8_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2186 2187 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2188 CSYNC; 2189 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2190 2191 // Now check that handler read correct values 2192 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2193 CHECKREG(r5, 0x10000000); 2194 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB9)); 2195 CHECKREG_SYM(r7, X8_9, r0); // RETX should be value of X8_9 (HARDCODED ADDR!!) 2196 2197 //------------------------------------------------------- 2198 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2199 2200 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2201 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2202 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2203 CSYNC; 2204 2205 LD32(i1, 0x10000000); 2206 R1 = 0x26FB (Z); 2207 LD32(p2, DCPLB_DATA10); 2208 2209X8_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2210 2211 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2212 CSYNC; 2213 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2214 2215 // Now check that handler read correct values 2216 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2217 CHECKREG(r5, 0x10000000); 2218 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB10)); 2219 CHECKREG_SYM(r7, X8_10, r0); // RETX should be value of X8_10 (HARDCODED ADDR!!) 2220 2221 //------------------------------------------------------- 2222 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2223 2224 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2225 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2226 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2227 CSYNC; 2228 2229 LD32(i1, 0x10000000); 2230 R1 = 0x718F (Z); 2231 LD32(p2, DCPLB_DATA11); 2232 2233X8_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2234 2235 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2236 CSYNC; 2237 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2238 2239 // Now check that handler read correct values 2240 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2241 CHECKREG(r5, 0x10000000); 2242 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB11)); 2243 CHECKREG_SYM(r7, X8_11, r0); // RETX should be value of X8_11 (HARDCODED ADDR!!) 2244 2245 //------------------------------------------------------- 2246 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2247 2248 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2249 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2250 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2251 CSYNC; 2252 2253 LD32(i1, 0x10000000); 2254 R1 = 0x04B1 (Z); 2255 LD32(p2, DCPLB_DATA12); 2256 2257X8_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2258 2259 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2260 CSYNC; 2261 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2262 2263 // Now check that handler read correct values 2264 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2265 CHECKREG(r5, 0x10000000); 2266 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB12)); 2267 CHECKREG_SYM(r7, X8_12, r0); // RETX should be value of X8_12 (HARDCODED ADDR!!) 2268 2269 //------------------------------------------------------- 2270 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2271 2272 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2273 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2274 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2275 CSYNC; 2276 2277 LD32(i1, 0x10000000); 2278 R1 = 0x5358 (Z); 2279 LD32(p2, DCPLB_DATA13); 2280 2281X8_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2282 2283 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2284 CSYNC; 2285 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2286 2287 // Now check that handler read correct values 2288 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2289 CHECKREG(r5, 0x10000000); 2290 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB13)); 2291 CHECKREG_SYM(r7, X8_13, r0); // RETX should be value of X8_13 (HARDCODED ADDR!!) 2292 2293 //------------------------------------------------------- 2294 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2295 2296 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2297 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2298 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2299 CSYNC; 2300 2301 LD32(i1, 0x10000000); 2302 R1 = 0x3305 (Z); 2303 LD32(p2, DCPLB_DATA14); 2304 2305X8_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2306 2307 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2308 CSYNC; 2309 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2310 2311 // Now check that handler read correct values 2312 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2313 CHECKREG(r5, 0x10000000); 2314 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB14)); 2315 CHECKREG_SYM(r7, X8_14, r0); // RETX should be value of X8_14 (HARDCODED ADDR!!) 2316 2317 //------------------------------------------------------- 2318 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2319 2320 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2321 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2322 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2323 CSYNC; 2324 2325 LD32(i1, 0x10000000); 2326 R1 = 0x5690 (Z); 2327 LD32(p2, DCPLB_DATA10); 2328 2329X9_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2330 2331 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2332 CSYNC; 2333 WR_MMR(DCPLB_DATA9, 0, p0, r0); 2334 2335 // Now check that handler read correct values 2336 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2337 CHECKREG(r5, 0x10000000); 2338 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB10)); 2339 CHECKREG_SYM(r7, X9_10, r0); // RETX should be value of X9_10 (HARDCODED ADDR!!) 2340 2341 //------------------------------------------------------- 2342 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2343 2344 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2345 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2346 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2347 CSYNC; 2348 2349 LD32(i1, 0x10000000); 2350 R1 = 0x5DC5 (Z); 2351 LD32(p2, DCPLB_DATA11); 2352 2353X9_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2354 2355 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2356 CSYNC; 2357 WR_MMR(DCPLB_DATA9, 0, p0, r0); 2358 2359 // Now check that handler read correct values 2360 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2361 CHECKREG(r5, 0x10000000); 2362 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB11)); 2363 CHECKREG_SYM(r7, X9_11, r0); // RETX should be value of X9_11 (HARDCODED ADDR!!) 2364 2365 //------------------------------------------------------- 2366 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2367 2368 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2369 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2370 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2371 CSYNC; 2372 2373 LD32(i1, 0x10000000); 2374 R1 = 0x7809 (Z); 2375 LD32(p2, DCPLB_DATA12); 2376 2377X9_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2378 2379 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2380 CSYNC; 2381 WR_MMR(DCPLB_DATA9, 0, p0, r0); 2382 2383 // Now check that handler read correct values 2384 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2385 CHECKREG(r5, 0x10000000); 2386 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB12)); 2387 CHECKREG_SYM(r7, X9_12, r0); // RETX should be value of X9_12 (HARDCODED ADDR!!) 2388 2389 //------------------------------------------------------- 2390 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2391 2392 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2393 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2394 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2395 CSYNC; 2396 2397 LD32(i1, 0x10000000); 2398 R1 = 0x1DDC (Z); 2399 LD32(p2, DCPLB_DATA13); 2400 2401X9_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2402 2403 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2404 CSYNC; 2405 WR_MMR(DCPLB_DATA9, 0, p0, r0); 2406 2407 // Now check that handler read correct values 2408 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2409 CHECKREG(r5, 0x10000000); 2410 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB13)); 2411 CHECKREG_SYM(r7, X9_13, r0); // RETX should be value of X9_13 (HARDCODED ADDR!!) 2412 2413 //------------------------------------------------------- 2414 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2415 2416 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2417 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2418 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2419 CSYNC; 2420 2421 LD32(i1, 0x10000000); 2422 R1 = 0x6B53 (Z); 2423 LD32(p2, DCPLB_DATA14); 2424 2425X9_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2426 2427 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2428 CSYNC; 2429 WR_MMR(DCPLB_DATA9, 0, p0, r0); 2430 2431 // Now check that handler read correct values 2432 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2433 CHECKREG(r5, 0x10000000); 2434 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB14)); 2435 CHECKREG_SYM(r7, X9_14, r0); // RETX should be value of X9_14 (HARDCODED ADDR!!) 2436 2437 //------------------------------------------------------- 2438 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2439 2440 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2441 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2442 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2443 CSYNC; 2444 2445 LD32(i1, 0x10000000); 2446 R1 = 0x7BCD (Z); 2447 LD32(p2, DCPLB_DATA11); 2448 2449X10_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2450 2451 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2452 CSYNC; 2453 WR_MMR(DCPLB_DATA10, 0, p0, r0); 2454 2455 // Now check that handler read correct values 2456 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2457 CHECKREG(r5, 0x10000000); 2458 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB11)); 2459 CHECKREG_SYM(r7, X10_11, r0); // RETX should be value of X10_11 (HARDCODED ADDR!!) 2460 2461 //------------------------------------------------------- 2462 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2463 2464 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2465 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2466 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2467 CSYNC; 2468 2469 LD32(i1, 0x10000000); 2470 R1 = 0x63AA (Z); 2471 LD32(p2, DCPLB_DATA12); 2472 2473X10_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2474 2475 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2476 CSYNC; 2477 WR_MMR(DCPLB_DATA10, 0, p0, r0); 2478 2479 // Now check that handler read correct values 2480 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2481 CHECKREG(r5, 0x10000000); 2482 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB12)); 2483 CHECKREG_SYM(r7, X10_12, r0); // RETX should be value of X10_12 (HARDCODED ADDR!!) 2484 2485 //------------------------------------------------------- 2486 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2487 2488 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2489 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2490 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2491 CSYNC; 2492 2493 LD32(i1, 0x10000000); 2494 R1 = 0x373B (Z); 2495 LD32(p2, DCPLB_DATA13); 2496 2497X10_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2498 2499 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2500 CSYNC; 2501 WR_MMR(DCPLB_DATA10, 0, p0, r0); 2502 2503 // Now check that handler read correct values 2504 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2505 CHECKREG(r5, 0x10000000); 2506 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB13)); 2507 CHECKREG_SYM(r7, X10_13, r0); // RETX should be value of X10_13 (HARDCODED ADDR!!) 2508 2509 //------------------------------------------------------- 2510 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2511 2512 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2513 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2514 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2515 CSYNC; 2516 2517 LD32(i1, 0x10000000); 2518 R1 = 0x5648 (Z); 2519 LD32(p2, DCPLB_DATA14); 2520 2521X10_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2522 2523 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2524 CSYNC; 2525 WR_MMR(DCPLB_DATA10, 0, p0, r0); 2526 2527 // Now check that handler read correct values 2528 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2529 CHECKREG(r5, 0x10000000); 2530 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB14)); 2531 CHECKREG_SYM(r7, X10_14, r0); // RETX should be value of X10_14 (HARDCODED ADDR!!) 2532 2533 //------------------------------------------------------- 2534 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2535 2536 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2537 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2538 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2539 CSYNC; 2540 2541 LD32(i1, 0x10000000); 2542 R1 = 0x6799 (Z); 2543 LD32(p2, DCPLB_DATA12); 2544 2545X11_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2546 2547 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2548 CSYNC; 2549 WR_MMR(DCPLB_DATA11, 0, p0, r0); 2550 2551 // Now check that handler read correct values 2552 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2553 CHECKREG(r5, 0x10000000); 2554 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB12)); 2555 CHECKREG_SYM(r7, X11_12, r0); // RETX should be value of X11_12 (HARDCODED ADDR!!) 2556 2557 //------------------------------------------------------- 2558 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2559 2560 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2561 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2562 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2563 CSYNC; 2564 2565 LD32(i1, 0x10000000); 2566 R1 = 0x1452 (Z); 2567 LD32(p2, DCPLB_DATA13); 2568 2569X11_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2570 2571 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2572 CSYNC; 2573 WR_MMR(DCPLB_DATA11, 0, p0, r0); 2574 2575 // Now check that handler read correct values 2576 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2577 CHECKREG(r5, 0x10000000); 2578 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB13)); 2579 CHECKREG_SYM(r7, X11_13, r0); // RETX should be value of X11_13 (HARDCODED ADDR!!) 2580 2581 //------------------------------------------------------- 2582 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2583 2584 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2585 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2586 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2587 CSYNC; 2588 2589 LD32(i1, 0x10000000); 2590 R1 = 0x23D3 (Z); 2591 LD32(p2, DCPLB_DATA14); 2592 2593X11_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2594 2595 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2596 CSYNC; 2597 WR_MMR(DCPLB_DATA11, 0, p0, r0); 2598 2599 // Now check that handler read correct values 2600 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2601 CHECKREG(r5, 0x10000000); 2602 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB14)); 2603 CHECKREG_SYM(r7, X11_14, r0); // RETX should be value of X11_14 (HARDCODED ADDR!!) 2604 2605 //------------------------------------------------------- 2606 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2607 2608 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2609 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2610 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2611 CSYNC; 2612 2613 LD32(i1, 0x10000000); 2614 R1 = 0x1152 (Z); 2615 LD32(p2, DCPLB_DATA13); 2616 2617X12_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2618 2619 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2620 CSYNC; 2621 WR_MMR(DCPLB_DATA12, 0, p0, r0); 2622 2623 // Now check that handler read correct values 2624 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2625 CHECKREG(r5, 0x10000000); 2626 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB13)); 2627 CHECKREG_SYM(r7, X12_13, r0); // RETX should be value of X12_13 (HARDCODED ADDR!!) 2628 2629 //------------------------------------------------------- 2630 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2631 2632 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2633 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2634 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2635 CSYNC; 2636 2637 LD32(i1, 0x10000000); 2638 R1 = 0x6E9D (Z); 2639 LD32(p2, DCPLB_DATA14); 2640 2641X12_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2642 2643 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2644 CSYNC; 2645 WR_MMR(DCPLB_DATA12, 0, p0, r0); 2646 2647 // Now check that handler read correct values 2648 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2649 CHECKREG(r5, 0x10000000); 2650 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB14)); 2651 CHECKREG_SYM(r7, X12_14, r0); // RETX should be value of X12_14 (HARDCODED ADDR!!) 2652 2653 //------------------------------------------------------- 2654 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2655 2656 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2657 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2658 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2659 CSYNC; 2660 2661 LD32(i1, 0x10000000); 2662 R1 = 0x6006 (Z); 2663 LD32(p2, DCPLB_DATA14); 2664 2665X13_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 2666 2667 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2668 CSYNC; 2669 WR_MMR(DCPLB_DATA13, 0, p0, r0); 2670 2671 // Now check that handler read correct values 2672 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2673 CHECKREG(r5, 0x10000000); 2674 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB13|FAULT_CPLB14)); 2675 CHECKREG_SYM(r7, X13_14, r0); // RETX should be value of X13_14 (HARDCODED ADDR!!) 2676 2677 //------------------------------------------------------- 2678User: 2679 NOP; 2680 dbg_pass; 2681