1# fr30 testcase for mul $Rj,$Ri 2# mach(): fr30 3 4 .include "testutils.inc" 5 6 START 7 8 .text 9 .global mul 10mul: 11 ; Test mul $Rj,$Ri 12 ; Positive operands 13 mvi_h_gr 3,r7 ; multiply small numbers 14 mvi_h_gr 2,r8 15 set_cc 0x0f ; Set mask opposite of expected 16 mul r7,r8 17 test_cc 0 0 0 1 18 test_h_dr 0,mdh 19 test_h_dr 6,mdl 20 21 mvi_h_gr 1,r7 ; multiply by 1 22 mvi_h_gr 2,r8 23 set_cc 0x0e ; Set mask opposite of expected 24 mul r7,r8 25 test_cc 0 0 0 0 26 test_h_dr 0,mdh 27 test_h_dr 2,mdl 28 29 mvi_h_gr 2,r7 ; multiply by 1 30 mvi_h_gr 1,r8 31 set_cc 0x0f ; Set mask opposite of expected 32 mul r7,r8 33 test_cc 0 0 0 1 34 test_h_dr 0,mdh 35 test_h_dr 2,mdl 36 37 mvi_h_gr 0,r7 ; multiply by 0 38 mvi_h_gr 2,r8 39 set_cc 0x0b ; Set mask opposite of expected 40 mul r7,r8 41 test_cc 0 1 0 1 42 test_h_dr 0,mdh 43 test_h_dr 0,mdl 44 45 mvi_h_gr 2,r7 ; multiply by 0 46 mvi_h_gr 0,r8 47 set_cc 0x0a ; Set mask opposite of expected 48 mul r7,r8 49 test_cc 0 1 0 0 50 test_h_dr 0,mdh 51 test_h_dr 0,mdl 52 53 mvi_h_gr 0x3fffffff,r7 ; 31 bit result 54 mvi_h_gr 2,r8 55 set_cc 0x0f ; Set mask opposite of expected 56 mul r7,r8 57 test_cc 0 0 0 1 58 test_h_dr 0,mdh 59 test_h_dr 0x7ffffffe,mdl 60 61 mvi_h_gr 0x40000000,r7 ; 32 bit result 62 mvi_h_gr 2,r8 63 set_cc 0x04 ; Set mask opposite of expected 64 mul r7,r8 65 test_cc 1 0 1 0 66 test_h_dr 0,mdh 67 test_h_dr 0x80000000,mdl 68 69 mvi_h_gr 0x40000000,r7 ; 33 bit result 70 mvi_h_gr 4,r8 71 set_cc 0x0d ; Set mask opposite of expected 72 mul r7,r8 73 test_cc 0 0 1 1 74 test_h_dr 1,mdh 75 test_h_dr 0x00000000,mdl 76 77 mvi_h_gr 0x7fffffff,r7 ; max positive result 78 mvi_h_gr 0x7fffffff,r8 79 set_cc 0x0d ; Set mask opposite of expected 80 mul r7,r8 81 test_cc 0 0 1 1 82 test_h_dr 0x3fffffff,mdh 83 test_h_dr 0x00000001,mdl 84 85 ; Mixed operands 86 mvi_h_gr -3,r7 ; multiply small numbers 87 mvi_h_gr 2,r8 88 set_cc 0x07 ; Set mask opposite of expected 89 mul r7,r8 90 test_cc 1 0 0 1 91 test_h_dr -1,mdh 92 test_h_dr -6,mdl 93 94 mvi_h_gr 3,r7 ; multiply small numbers 95 mvi_h_gr -2,r8 96 set_cc 0x07 ; Set mask opposite of expected 97 mul r7,r8 98 test_cc 1 0 0 1 99 test_h_dr -1,mdh 100 test_h_dr -6,mdl 101 102 mvi_h_gr 1,r7 ; multiply by 1 103 mvi_h_gr -2,r8 104 set_cc 0x06 ; Set mask opposite of expected 105 mul r7,r8 106 test_cc 1 0 0 0 107 test_h_dr -1,mdh 108 test_h_dr -2,mdl 109 110 mvi_h_gr -2,r7 ; multiply by 1 111 mvi_h_gr 1,r8 112 set_cc 0x07 ; Set mask opposite of expected 113 mul r7,r8 114 test_cc 1 0 0 1 115 test_h_dr -1,mdh 116 test_h_dr -2,mdl 117 118 mvi_h_gr 0,r7 ; multiply by 0 119 mvi_h_gr -2,r8 120 set_cc 0x0b ; Set mask opposite of expected 121 mul r7,r8 122 test_cc 0 1 0 1 123 test_h_dr 0,mdh 124 test_h_dr 0,mdl 125 126 mvi_h_gr -2,r7 ; multiply by 0 127 mvi_h_gr 0,r8 128 set_cc 0x0a ; Set mask opposite of expected 129 mul r7,r8 130 test_cc 0 1 0 0 131 test_h_dr 0,mdh 132 test_h_dr 0,mdl 133 134 mvi_h_gr 0x20000001,r7 ; 31 bit result 135 mvi_h_gr -2,r8 136 set_cc 0x07 ; Set mask opposite of expected 137 mul r7,r8 138 test_cc 1 0 0 1 139 test_h_dr 0xffffffff,mdh 140 test_h_dr 0xbffffffe,mdl 141 142 mvi_h_gr 0x40000000,r7 ; 32 bit result 143 mvi_h_gr -2,r8 144 set_cc 0x06 ; Set mask opposite of expected 145 mul r7,r8 146 test_cc 1 0 0 0 147 test_h_dr 0xffffffff,mdh 148 test_h_dr 0x80000000,mdl 149 150 mvi_h_gr 0x40000001,r7 ; 32 bit result 151 mvi_h_gr -2,r8 152 set_cc 0x0c ; Set mask opposite of expected 153 mul r7,r8 154 test_cc 0 0 1 0 155 test_h_dr 0xffffffff,mdh 156 test_h_dr 0x7ffffffe,mdl 157 158 mvi_h_gr 0x40000000,r7 ; 33 bit result 159 mvi_h_gr -4,r8 160 set_cc 0x0d ; Set mask opposite of expected 161 mul r7,r8 162 test_cc 0 0 1 1 163 test_h_dr 0xffffffff,mdh 164 test_h_dr 0x00000000,mdl 165 166 mvi_h_gr 0x7fffffff,r7 ; max negative result 167 mvi_h_gr 0x80000000,r8 168 set_cc 0x05 ; Set mask opposite of expected 169 mul r7,r8 170 test_cc 1 0 1 1 171 test_h_dr 0xc0000000,mdh 172 test_h_dr 0x80000000,mdl 173 174 ; Negative operands 175 mvi_h_gr -3,r7 ; multiply small numbers 176 mvi_h_gr -2,r8 177 set_cc 0x0f ; Set mask opposite of expected 178 mul r7,r8 179 test_cc 0 0 0 1 180 test_h_dr 0,mdh 181 test_h_dr 6,mdl 182 183 mvi_h_gr -1,r7 ; multiply by 1 184 mvi_h_gr -2,r8 185 set_cc 0x0e ; Set mask opposite of expected 186 mul r7,r8 187 test_cc 0 0 0 0 188 test_h_dr 0,mdh 189 test_h_dr 2,mdl 190 191 mvi_h_gr -2,r7 ; multiply by 1 192 mvi_h_gr -1,r8 193 set_cc 0x0f ; Set mask opposite of expected 194 mul r7,r8 195 test_cc 0 0 0 1 196 test_h_dr 0,mdh 197 test_h_dr 2,mdl 198 199 mvi_h_gr 0xc0000001,r7 ; 31 bit result 200 mvi_h_gr -2,r8 201 set_cc 0x0f ; Set mask opposite of expected 202 mul r7,r8 203 test_cc 0 0 0 1 204 test_h_dr 0,mdh 205 test_h_dr 0x7ffffffe,mdl 206 207 mvi_h_gr 0xc0000000,r7 ; 32 bit result 208 mvi_h_gr -2,r8 209 set_cc 0x04 ; Set mask opposite of expected 210 mul r7,r8 211 test_cc 1 0 1 0 212 test_h_dr 0,mdh 213 test_h_dr 0x80000000,mdl 214 215 mvi_h_gr 0xc0000000,r7 ; 33 bit result 216 mvi_h_gr -4,r8 217 set_cc 0x0d ; Set mask opposite of expected 218 mul r7,r8 219 test_cc 0 0 1 1 220 test_h_dr 1,mdh 221 test_h_dr 0x00000000,mdl 222 223 mvi_h_gr 0x80000001,r7 ; almost max positive result 224 mvi_h_gr 0x80000001,r8 225 set_cc 0x0d ; Set mask opposite of expected 226 mul r7,r8 227 test_cc 0 0 1 1 228 test_h_dr 0x3fffffff,mdh 229 test_h_dr 0x00000001,mdl 230 231 232 mvi_h_gr 0x80000000,r7 ; max positive result 233 mvi_h_gr 0x80000000,r8 234 set_cc 0x0d ; Set mask opposite of expected 235 mul r7,r8 236 test_cc 0 0 1 1 237 test_h_dr 0x40000000,mdh 238 test_h_dr 0x00000000,mdl 239 240 pass 241