1# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond 2# mach: frv fr500 3 4 .include "../testutils.inc" 5 6 start 7 8 .global cmqaddhss 9cmqaddhss: 10 set_spr_immed 0x1b1b,cccr 11 12 set_fr_iimmed 0x0000,0x0000,fr10 13 set_fr_iimmed 0xdead,0x0000,fr11 14 set_fr_iimmed 0x0000,0x0000,fr12 15 set_fr_iimmed 0x0000,0xbeef,fr13 16 cmqaddhss fr10,fr12,fr14,cc0,1 17 test_fr_limmed 0x0000,0x0000,fr14 18 test_fr_limmed 0xdead,0xbeef,fr15 19 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 20 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 21 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 22 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 23 24 set_fr_iimmed 0x0000,0xdead,fr10 25 set_fr_iimmed 0x1234,0x5678,fr11 26 set_fr_iimmed 0xbeef,0x0000,fr12 27 set_fr_iimmed 0x1111,0x1111,fr13 28 cmqaddhss fr10,fr12,fr14,cc0,1 29 test_fr_limmed 0xbeef,0xdead,fr14 30 test_fr_limmed 0x2345,0x6789,fr15 31 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 32 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 33 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 34 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 35 36 set_spr_immed 0,msr0 37 set_fr_iimmed 0x1234,0x5678,fr10 38 set_fr_iimmed 0x7ffe,0x7ffe,fr11 39 set_fr_iimmed 0xffff,0xffff,fr12 40 set_fr_iimmed 0x0002,0x0001,fr13 41 cmqaddhss fr10,fr12,fr14,cc0,1 42 test_fr_limmed 0x1233,0x5677,fr14 43 test_fr_limmed 0x7fff,0x7fff,fr15 44 test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set 45 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 46 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 47 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 48 49 set_spr_immed 0,msr0 50 set_fr_iimmed 0x8001,0x8001,fr10 51 set_fr_iimmed 0x8001,0x8001,fr11 52 set_fr_iimmed 0xffff,0xfffe,fr12 53 set_fr_iimmed 0xfffe,0xfffe,fr13 54 cmqaddhss fr10,fr12,fr14,cc4,1 55 test_fr_limmed 0x8000,0x8000,fr14 56 test_fr_limmed 0x8000,0x8000,fr15 57 test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set 58 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 59 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 60 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 61 62 set_spr_immed 0,msr0 63 set_spr_immed 0,msr1 64 set_fr_iimmed 0x0001,0x0001,fr10 65 set_fr_iimmed 0xffff,0xffff,fr11 66 set_fr_iimmed 0x7fff,0x0000,fr12 67 set_fr_iimmed 0x0000,0x8000,fr13 68 cmqaddhss.p fr10,fr10,fr14,cc4,1 69 cmqaddhss fr12,fr12,fr16,cc4,1 70 test_fr_limmed 0x0002,0x0002,fr14 71 test_fr_limmed 0xfffe,0xfffe,fr15 72 test_fr_limmed 0x7fff,0x0000,fr16 73 test_fr_limmed 0x0000,0x8000,fr17 74 test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set 75 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 76 test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set 77 test_spr_bits 2,1,1,msr1 ; msr1.ovf set 78 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 79 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 80 81 set_spr_immed 0,msr0 82 set_spr_immed 0,msr1 83 set_fr_iimmed 0x0000,0x0000,fr10 84 set_fr_iimmed 0xdead,0x0000,fr11 85 set_fr_iimmed 0x0000,0x0000,fr12 86 set_fr_iimmed 0x0000,0xbeef,fr13 87 cmqaddhss fr10,fr12,fr14,cc1,0 88 test_fr_limmed 0x0000,0x0000,fr14 89 test_fr_limmed 0xdead,0xbeef,fr15 90 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 91 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 92 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 93 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 94 95 set_fr_iimmed 0x0000,0xdead,fr10 96 set_fr_iimmed 0x1234,0x5678,fr11 97 set_fr_iimmed 0xbeef,0x0000,fr12 98 set_fr_iimmed 0x1111,0x1111,fr13 99 cmqaddhss fr10,fr12,fr14,cc1,0 100 test_fr_limmed 0xbeef,0xdead,fr14 101 test_fr_limmed 0x2345,0x6789,fr15 102 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 103 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 104 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 105 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 106 107 set_spr_immed 0,msr0 108 set_fr_iimmed 0x1234,0x5678,fr10 109 set_fr_iimmed 0x7ffe,0x7ffe,fr11 110 set_fr_iimmed 0xffff,0xffff,fr12 111 set_fr_iimmed 0x0002,0x0001,fr13 112 cmqaddhss fr10,fr12,fr14,cc1,0 113 test_fr_limmed 0x1233,0x5677,fr14 114 test_fr_limmed 0x7fff,0x7fff,fr15 115 test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set 116 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 117 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 118 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 119 120 set_spr_immed 0,msr0 121 set_fr_iimmed 0x8001,0x8001,fr10 122 set_fr_iimmed 0x8001,0x8001,fr11 123 set_fr_iimmed 0xffff,0xfffe,fr12 124 set_fr_iimmed 0xfffe,0xfffe,fr13 125 cmqaddhss fr10,fr12,fr14,cc5,0 126 test_fr_limmed 0x8000,0x8000,fr14 127 test_fr_limmed 0x8000,0x8000,fr15 128 test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set 129 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 130 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 131 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 132 133 set_spr_immed 0,msr0 134 set_spr_immed 0,msr1 135 set_fr_iimmed 0x0001,0x0001,fr10 136 set_fr_iimmed 0xffff,0xffff,fr11 137 set_fr_iimmed 0x7fff,0x0000,fr12 138 set_fr_iimmed 0x0000,0x8000,fr13 139 cmqaddhss.p fr10,fr10,fr14,cc5,0 140 cmqaddhss fr12,fr12,fr16,cc5,0 141 test_fr_limmed 0x0002,0x0002,fr14 142 test_fr_limmed 0xfffe,0xfffe,fr15 143 test_fr_limmed 0x7fff,0x0000,fr16 144 test_fr_limmed 0x0000,0x8000,fr17 145 test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set 146 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 147 test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set 148 test_spr_bits 2,1,1,msr1 ; msr1.ovf set 149 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 150 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 151 152 set_fr_iimmed 0x1111,0x1111,fr14 153 set_fr_iimmed 0x2222,0x2222,fr15 154 set_spr_immed 0,msr0 155 set_spr_immed 0,msr1 156 set_fr_iimmed 0x0000,0x0000,fr10 157 set_fr_iimmed 0xdead,0x0000,fr11 158 set_fr_iimmed 0x0000,0x0000,fr12 159 set_fr_iimmed 0x0000,0xbeef,fr13 160 cmqaddhss fr10,fr12,fr14,cc0,0 161 test_fr_limmed 0x1111,0x1111,fr14 162 test_fr_limmed 0x2222,0x2222,fr15 163 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 164 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 165 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 166 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 167 168 set_fr_iimmed 0x0000,0xdead,fr10 169 set_fr_iimmed 0x1234,0x5678,fr11 170 set_fr_iimmed 0xbeef,0x0000,fr12 171 set_fr_iimmed 0x1111,0x1111,fr13 172 cmqaddhss fr10,fr12,fr14,cc0,0 173 test_fr_limmed 0x1111,0x1111,fr14 174 test_fr_limmed 0x2222,0x2222,fr15 175 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 176 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 177 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 178 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 179 180 set_spr_immed 0,msr0 181 set_fr_iimmed 0x1234,0x5678,fr10 182 set_fr_iimmed 0x7ffe,0x7ffe,fr11 183 set_fr_iimmed 0xffff,0xffff,fr12 184 set_fr_iimmed 0x0002,0x0001,fr13 185 cmqaddhss fr10,fr12,fr14,cc0,0 186 test_fr_limmed 0x1111,0x1111,fr14 187 test_fr_limmed 0x2222,0x2222,fr15 188 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 189 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 190 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 191 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 192 193 set_spr_immed 0,msr0 194 set_fr_iimmed 0x8001,0x8001,fr10 195 set_fr_iimmed 0x8001,0x8001,fr11 196 set_fr_iimmed 0xffff,0xfffe,fr12 197 set_fr_iimmed 0xfffe,0xfffe,fr13 198 cmqaddhss fr10,fr12,fr14,cc4,0 199 test_fr_limmed 0x1111,0x1111,fr14 200 test_fr_limmed 0x2222,0x2222,fr15 201 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 202 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 203 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 204 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 205 206 set_fr_iimmed 0x3333,0x3333,fr16 207 set_fr_iimmed 0x4444,0x4444,fr17 208 set_spr_immed 0,msr0 209 set_spr_immed 0,msr1 210 set_fr_iimmed 0x0001,0x0001,fr10 211 set_fr_iimmed 0xffff,0xffff,fr11 212 set_fr_iimmed 0x7fff,0x0000,fr12 213 set_fr_iimmed 0x0000,0x8000,fr13 214 cmqaddhss.p fr10,fr10,fr14,cc4,0 215 cmqaddhss fr12,fr12,fr16,cc4,0 216 test_fr_limmed 0x1111,0x1111,fr14 217 test_fr_limmed 0x2222,0x2222,fr15 218 test_fr_limmed 0x3333,0x3333,fr16 219 test_fr_limmed 0x4444,0x4444,fr17 220 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 221 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 222 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 223 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 224 225 set_fr_iimmed 0x1111,0x1111,fr14 226 set_fr_iimmed 0x2222,0x2222,fr15 227 set_spr_immed 0,msr0 228 set_spr_immed 0,msr1 229 set_fr_iimmed 0x0000,0x0000,fr10 230 set_fr_iimmed 0xdead,0x0000,fr11 231 set_fr_iimmed 0x0000,0x0000,fr12 232 set_fr_iimmed 0x0000,0xbeef,fr13 233 cmqaddhss fr10,fr12,fr14,cc1,1 234 test_fr_limmed 0x1111,0x1111,fr14 235 test_fr_limmed 0x2222,0x2222,fr15 236 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 237 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 238 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 239 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 240 241 set_fr_iimmed 0x0000,0xdead,fr10 242 set_fr_iimmed 0x1234,0x5678,fr11 243 set_fr_iimmed 0xbeef,0x0000,fr12 244 set_fr_iimmed 0x1111,0x1111,fr13 245 cmqaddhss fr10,fr12,fr14,cc1,1 246 test_fr_limmed 0x1111,0x1111,fr14 247 test_fr_limmed 0x2222,0x2222,fr15 248 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 249 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 250 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 251 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 252 253 set_spr_immed 0,msr0 254 set_fr_iimmed 0x1234,0x5678,fr10 255 set_fr_iimmed 0x7ffe,0x7ffe,fr11 256 set_fr_iimmed 0xffff,0xffff,fr12 257 set_fr_iimmed 0x0002,0x0001,fr13 258 cmqaddhss fr10,fr12,fr14,cc1,1 259 test_fr_limmed 0x1111,0x1111,fr14 260 test_fr_limmed 0x2222,0x2222,fr15 261 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 262 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 263 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 264 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 265 266 set_spr_immed 0,msr0 267 set_fr_iimmed 0x8001,0x8001,fr10 268 set_fr_iimmed 0x8001,0x8001,fr11 269 set_fr_iimmed 0xffff,0xfffe,fr12 270 set_fr_iimmed 0xfffe,0xfffe,fr13 271 cmqaddhss fr10,fr12,fr14,cc5,1 272 test_fr_limmed 0x1111,0x1111,fr14 273 test_fr_limmed 0x2222,0x2222,fr15 274 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 275 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 276 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 277 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 278 279 set_fr_iimmed 0x3333,0x3333,fr16 280 set_fr_iimmed 0x4444,0x4444,fr17 281 set_spr_immed 0,msr0 282 set_spr_immed 0,msr1 283 set_fr_iimmed 0x0001,0x0001,fr10 284 set_fr_iimmed 0xffff,0xffff,fr11 285 set_fr_iimmed 0x7fff,0x0000,fr12 286 set_fr_iimmed 0x0000,0x8000,fr13 287 cmqaddhss.p fr10,fr10,fr14,cc5,1 288 cmqaddhss fr12,fr12,fr16,cc5,1 289 test_fr_limmed 0x1111,0x1111,fr14 290 test_fr_limmed 0x2222,0x2222,fr15 291 test_fr_limmed 0x3333,0x3333,fr16 292 test_fr_limmed 0x4444,0x4444,fr17 293 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 294 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 295 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 296 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 297 298 set_fr_iimmed 0x1111,0x1111,fr14 299 set_fr_iimmed 0x2222,0x2222,fr15 300 set_spr_immed 0,msr0 301 set_spr_immed 0,msr1 302 set_fr_iimmed 0x0000,0x0000,fr10 303 set_fr_iimmed 0xdead,0x0000,fr11 304 set_fr_iimmed 0x0000,0x0000,fr12 305 set_fr_iimmed 0x0000,0xbeef,fr13 306 cmqaddhss fr10,fr12,fr14,cc2,1 307 test_fr_limmed 0x1111,0x1111,fr14 308 test_fr_limmed 0x2222,0x2222,fr15 309 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 310 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 311 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 312 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 313 314 set_fr_iimmed 0x0000,0xdead,fr10 315 set_fr_iimmed 0x1234,0x5678,fr11 316 set_fr_iimmed 0xbeef,0x0000,fr12 317 set_fr_iimmed 0x1111,0x1111,fr13 318 cmqaddhss fr10,fr12,fr14,cc2,0 319 test_fr_limmed 0x1111,0x1111,fr14 320 test_fr_limmed 0x2222,0x2222,fr15 321 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 322 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 323 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 324 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 325 326 set_spr_immed 0,msr0 327 set_fr_iimmed 0x1234,0x5678,fr10 328 set_fr_iimmed 0x7ffe,0x7ffe,fr11 329 set_fr_iimmed 0xffff,0xffff,fr12 330 set_fr_iimmed 0x0002,0x0001,fr13 331 cmqaddhss fr10,fr12,fr14,cc2,1 332 test_fr_limmed 0x1111,0x1111,fr14 333 test_fr_limmed 0x2222,0x2222,fr15 334 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 335 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 336 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 337 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 338 339 set_spr_immed 0,msr0 340 set_fr_iimmed 0x8001,0x8001,fr10 341 set_fr_iimmed 0x8001,0x8001,fr11 342 set_fr_iimmed 0xffff,0xfffe,fr12 343 set_fr_iimmed 0xfffe,0xfffe,fr13 344 cmqaddhss fr10,fr12,fr14,cc6,0 345 test_fr_limmed 0x1111,0x1111,fr14 346 test_fr_limmed 0x2222,0x2222,fr15 347 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 348 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 349 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 350 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 351 352 set_fr_iimmed 0x3333,0x3333,fr16 353 set_fr_iimmed 0x4444,0x4444,fr17 354 set_spr_immed 0,msr0 355 set_spr_immed 0,msr1 356 set_fr_iimmed 0x0001,0x0001,fr10 357 set_fr_iimmed 0xffff,0xffff,fr11 358 set_fr_iimmed 0x7fff,0x0000,fr12 359 set_fr_iimmed 0x0000,0x8000,fr13 360 cmqaddhss.p fr10,fr10,fr14,cc6,1 361 cmqaddhss fr12,fr12,fr16,cc6,0 362 test_fr_limmed 0x1111,0x1111,fr14 363 test_fr_limmed 0x2222,0x2222,fr15 364 test_fr_limmed 0x3333,0x3333,fr16 365 test_fr_limmed 0x4444,0x4444,fr17 366 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 367 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 368 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 369 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 370; 371 set_fr_iimmed 0x1111,0x1111,fr14 372 set_fr_iimmed 0x2222,0x2222,fr15 373 set_spr_immed 0,msr0 374 set_spr_immed 0,msr1 375 set_fr_iimmed 0x0000,0x0000,fr10 376 set_fr_iimmed 0xdead,0x0000,fr11 377 set_fr_iimmed 0x0000,0x0000,fr12 378 set_fr_iimmed 0x0000,0xbeef,fr13 379 cmqaddhss fr10,fr12,fr14,cc3,1 380 test_fr_limmed 0x1111,0x1111,fr14 381 test_fr_limmed 0x2222,0x2222,fr15 382 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 383 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 384 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 385 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 386 387 set_fr_iimmed 0x0000,0xdead,fr10 388 set_fr_iimmed 0x1234,0x5678,fr11 389 set_fr_iimmed 0xbeef,0x0000,fr12 390 set_fr_iimmed 0x1111,0x1111,fr13 391 cmqaddhss fr10,fr12,fr14,cc3,0 392 test_fr_limmed 0x1111,0x1111,fr14 393 test_fr_limmed 0x2222,0x2222,fr15 394 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 395 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 396 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 397 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 398 399 set_spr_immed 0,msr0 400 set_fr_iimmed 0x1234,0x5678,fr10 401 set_fr_iimmed 0x7ffe,0x7ffe,fr11 402 set_fr_iimmed 0xffff,0xffff,fr12 403 set_fr_iimmed 0x0002,0x0001,fr13 404 cmqaddhss fr10,fr12,fr14,cc3,1 405 test_fr_limmed 0x1111,0x1111,fr14 406 test_fr_limmed 0x2222,0x2222,fr15 407 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 408 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 409 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 410 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 411 412 set_spr_immed 0,msr0 413 set_fr_iimmed 0x8001,0x8001,fr10 414 set_fr_iimmed 0x8001,0x8001,fr11 415 set_fr_iimmed 0xffff,0xfffe,fr12 416 set_fr_iimmed 0xfffe,0xfffe,fr13 417 cmqaddhss fr10,fr12,fr14,cc7,0 418 test_fr_limmed 0x1111,0x1111,fr14 419 test_fr_limmed 0x2222,0x2222,fr15 420 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 421 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 422 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 423 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 424 425 set_fr_iimmed 0x3333,0x3333,fr16 426 set_fr_iimmed 0x4444,0x4444,fr17 427 set_spr_immed 0,msr0 428 set_spr_immed 0,msr1 429 set_fr_iimmed 0x0001,0x0001,fr10 430 set_fr_iimmed 0xffff,0xffff,fr11 431 set_fr_iimmed 0x7fff,0x0000,fr12 432 set_fr_iimmed 0x0000,0x8000,fr13 433 cmqaddhss.p fr10,fr10,fr14,cc7,1 434 cmqaddhss fr12,fr12,fr16,cc7,0 435 test_fr_limmed 0x1111,0x1111,fr14 436 test_fr_limmed 0x2222,0x2222,fr15 437 test_fr_limmed 0x3333,0x3333,fr16 438 test_fr_limmed 0x4444,0x4444,fr17 439 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 440 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 441 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 442 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 443 444 pass 445