1 /* $NetBSD: pmap.h,v 1.58 2023/04/20 08:28:03 skrll Exp $ */
2
3 /*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef _AARCH64_PMAP_H_
33 #define _AARCH64_PMAP_H_
34
35 #ifdef __aarch64__
36
37 #ifdef _KERNEL
38 #ifdef _KERNEL_OPT
39 #include "opt_kasan.h"
40 #include "opt_pmap.h"
41 #endif
42
43 #include <sys/types.h>
44 #include <sys/pool.h>
45 #include <sys/queue.h>
46
47 #include <uvm/uvm_pglist.h>
48
49 #include <aarch64/armreg.h>
50 #include <aarch64/pte.h>
51
52 #define PMAP_TLB_MAX 1
53 #if PMAP_TLB_MAX > 1
54 #define PMAP_TLB_NEED_SHOOTDOWN 1
55 #endif
56
57 #define PMAP_TLB_FLUSH_ASID_ON_RESET true
58
59 /* Maximum number of ASIDs. Some CPUs have less.*/
60 #define PMAP_TLB_NUM_PIDS 65536
61 #define PMAP_TLB_BITMAP_LENGTH PMAP_TLB_NUM_PIDS
62 #define cpu_set_tlb_info(ci, ti) ((void)((ci)->ci_tlb_info = (ti)))
63 #if PMAP_TLB_MAX > 1
64 #define cpu_tlb_info(ci) ((ci)->ci_tlb_info)
65 #else
66 #define cpu_tlb_info(ci) (&pmap_tlb0_info)
67 #endif
68
69 static inline tlb_asid_t
pmap_md_tlb_asid_max(void)70 pmap_md_tlb_asid_max(void)
71 {
72 switch (__SHIFTOUT(reg_id_aa64mmfr0_el1_read(), ID_AA64MMFR0_EL1_ASIDBITS)) {
73 case ID_AA64MMFR0_EL1_ASIDBITS_8BIT:
74 return (1U << 8) - 1;
75 case ID_AA64MMFR0_EL1_ASIDBITS_16BIT:
76 return (1U << 16) - 1;
77 default:
78 return 0;
79 }
80 }
81
82 #include <uvm/pmap/tlb.h>
83 #include <uvm/pmap/pmap_devmap.h>
84 #include <uvm/pmap/pmap_tlb.h>
85
86 #define KERNEL_PID 0 /* The kernel uses ASID 0 */
87
88
89 /* memory attributes are configured MAIR_EL1 in locore */
90 #define LX_BLKPAG_ATTR_NORMAL_WB __SHIFTIN(0, LX_BLKPAG_ATTR_INDX)
91 #define LX_BLKPAG_ATTR_NORMAL_NC __SHIFTIN(1, LX_BLKPAG_ATTR_INDX)
92 #define LX_BLKPAG_ATTR_NORMAL_WT __SHIFTIN(2, LX_BLKPAG_ATTR_INDX)
93 #define LX_BLKPAG_ATTR_DEVICE_MEM __SHIFTIN(3, LX_BLKPAG_ATTR_INDX)
94 #define LX_BLKPAG_ATTR_DEVICE_MEM_NP __SHIFTIN(4, LX_BLKPAG_ATTR_INDX)
95 #define LX_BLKPAG_ATTR_MASK LX_BLKPAG_ATTR_INDX
96
97 #define lxpde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA))
98 #define lxpde_valid(pde) (((pde) & LX_VALID) == LX_VALID)
99 #define l0pde_pa(pde) lxpde_pa(pde)
100 #define l0pde_index(v) (((vaddr_t)(v) & L0_ADDR_BITS) >> L0_SHIFT)
101 #define l0pde_valid(pde) lxpde_valid(pde)
102 /* l0pte always contains table entries */
103
104 #define l1pde_pa(pde) lxpde_pa(pde)
105 #define l1pde_index(v) (((vaddr_t)(v) & L1_ADDR_BITS) >> L1_SHIFT)
106 #define l1pde_valid(pde) lxpde_valid(pde)
107 #define l1pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK)
108 #define l1pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL)
109
110 #define l2pde_pa(pde) lxpde_pa(pde)
111 #define l2pde_index(v) (((vaddr_t)(v) & L2_ADDR_BITS) >> L2_SHIFT)
112 #define l2pde_valid(pde) lxpde_valid(pde)
113 #define l2pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK)
114 #define l2pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL)
115
116 #define l3pte_pa(pde) lxpde_pa(pde)
117 #define l3pte_executable(pde,user) \
118 (((pde) & ((user) ? LX_BLKPAG_UXN : LX_BLKPAG_PXN)) == 0)
119 #define l3pte_readable(pde) ((pde) & LX_BLKPAG_AF)
120 #define l3pte_writable(pde) \
121 (((pde) & (LX_BLKPAG_AF | LX_BLKPAG_AP)) == (LX_BLKPAG_AF | LX_BLKPAG_AP_RW))
122 #define l3pte_index(v) (((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT)
123 #define l3pte_valid(pde) lxpde_valid(pde)
124 #define l3pte_is_page(pde) (((pde) & LX_TYPE) == L3_TYPE_PAG)
125
126 pd_entry_t *pmap_l0table(struct pmap *);
127 void pmap_bootstrap(vaddr_t, vaddr_t);
128 bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user);
129
130 bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *);
131
132
133 /* change attribute of kernel segment */
134 static inline pt_entry_t
pmap_kvattr(pt_entry_t * ptep,vm_prot_t prot)135 pmap_kvattr(pt_entry_t *ptep, vm_prot_t prot)
136 {
137 pt_entry_t pte = *ptep;
138 const pt_entry_t opte = pte;
139
140 pte &= ~(LX_BLKPAG_AF | LX_BLKPAG_AP);
141 switch (prot & (VM_PROT_READ | VM_PROT_WRITE)) {
142 case 0:
143 break;
144 case VM_PROT_READ:
145 pte |= LX_BLKPAG_AF | LX_BLKPAG_AP_RO;
146 break;
147 case VM_PROT_WRITE:
148 case VM_PROT_READ | VM_PROT_WRITE:
149 pte |= LX_BLKPAG_AF | LX_BLKPAG_AP_RW;
150 break;
151 }
152
153 if ((prot & VM_PROT_EXECUTE) == 0) {
154 pte |= LX_BLKPAG_PXN;
155 } else {
156 pte |= LX_BLKPAG_AF;
157 pte &= ~LX_BLKPAG_PXN;
158 }
159
160 *ptep = pte;
161
162 return opte;
163 }
164
165 #define L1_TRUNC_BLOCK(x) ((x) & L1_FRAME)
166 #define L1_ROUND_BLOCK(x) L1_TRUNC_BLOCK((x) + L1_SIZE - 1)
167 #define L2_TRUNC_BLOCK(x) ((x) & L2_FRAME)
168 #define L2_ROUND_BLOCK(x) L2_TRUNC_BLOCK((x) + L2_SIZE - 1)
169 #define L3_TRUNC_BLOCK(x) ((x) & L3_FRAME)
170 #define L3_ROUND_BLOCK(x) L3_TRUNC_BLOCK((x) + L3_SIZE - 1)
171
172 #define DEVMAP_ALIGN(x) L3_TRUNC_BLOCK((x))
173 #define DEVMAP_SIZE(x) L3_ROUND_BLOCK((x))
174 #define DEVMAP_FLAGS PMAP_DEV
175
176 /* Hooks for the pool allocator */
177 paddr_t vtophys(vaddr_t);
178
179 /* mmap cookie and flags */
180 #define AARCH64_MMAP_FLAG_SHIFT (64 - PGSHIFT)
181 #define AARCH64_MMAP_FLAG_MASK 0xf
182 #define AARCH64_MMAP_WRITEBACK 0UL
183 #define AARCH64_MMAP_NOCACHE 1UL
184 #define AARCH64_MMAP_WRITECOMBINE 2UL
185 #define AARCH64_MMAP_DEVICE 3UL
186
187 #define ARM_MMAP_MASK __BITS(63, AARCH64_MMAP_FLAG_SHIFT)
188 #define ARM_MMAP_WRITECOMBINE __SHIFTIN(AARCH64_MMAP_WRITECOMBINE, ARM_MMAP_MASK)
189 #define ARM_MMAP_WRITEBACK __SHIFTIN(AARCH64_MMAP_WRITEBACK, ARM_MMAP_MASK)
190 #define ARM_MMAP_NOCACHE __SHIFTIN(AARCH64_MMAP_NOCACHE, ARM_MMAP_MASK)
191 #define ARM_MMAP_DEVICE __SHIFTIN(AARCH64_MMAP_DEVICE, ARM_MMAP_MASK)
192
193 #define PMAP_PTE 0x10000000 /* kenter_pa */
194 #define PMAP_DEV 0x20000000 /* kenter_pa */
195 #define PMAP_DEV_NP 0x40000000 /* kenter_pa */
196 #define PMAP_DEV_MASK (PMAP_DEV | PMAP_DEV_NP)
197
198 static inline u_int
aarch64_mmap_flags(paddr_t mdpgno)199 aarch64_mmap_flags(paddr_t mdpgno)
200 {
201 u_int nflag, pflag;
202
203 /*
204 * aarch64 arch has 5 memory attributes defined:
205 *
206 * WriteBack - write back cache
207 * WriteThru - write through cache
208 * NoCache - no cache
209 * Device(nGnRE) - no Gathering, no Reordering, Early write ack
210 * Device(nGnRnE) - no Gathering, no Reordering, no Early write ack
211 *
212 * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags.
213 */
214
215 nflag = (mdpgno >> AARCH64_MMAP_FLAG_SHIFT) & AARCH64_MMAP_FLAG_MASK;
216 switch (nflag) {
217 case AARCH64_MMAP_DEVICE:
218 pflag = PMAP_DEV;
219 break;
220 case AARCH64_MMAP_WRITECOMBINE:
221 pflag = PMAP_WRITE_COMBINE;
222 break;
223 case AARCH64_MMAP_WRITEBACK:
224 pflag = PMAP_WRITE_BACK;
225 break;
226 case AARCH64_MMAP_NOCACHE:
227 default:
228 pflag = PMAP_NOCACHE;
229 break;
230 }
231 return pflag;
232 }
233
234 #define pmap_phys_address(pa) aarch64_ptob((pa))
235 #define pmap_mmap_flags(ppn) aarch64_mmap_flags((ppn))
236
237 void pmap_bootstrap(vaddr_t, vaddr_t);
238 bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user);
239
240 pd_entry_t *pmapboot_pagealloc(void);
241 void pmapboot_enter(vaddr_t, paddr_t, psize_t, psize_t, pt_entry_t,
242 void (*pr)(const char *, ...) __printflike(1, 2));
243 void pmapboot_enter_range(vaddr_t, paddr_t, psize_t, pt_entry_t,
244 void (*)(const char *, ...) __printflike(1, 2));
245 int pmapboot_protect(vaddr_t, vaddr_t, vm_prot_t);
246
247 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int);
248
249 #if defined(DDB)
250 void pmap_db_pte_print(pt_entry_t, int, void (*)(const char *, ...) __printflike(1, 2));
251 void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2));
252 void pmap_db_ttbrdump(bool, vaddr_t, void (*)(const char *, ...) __printflike(1, 2));
253 #endif
254
255 #define LX_BLKPAG_OS_WIRED LX_BLKPAG_OS_2
256 #define LX_BLKPAG_OS_BOOT LX_BLKPAG_OS_3
257
258 #define PMAP_PTE_OS2 "wired"
259 #define PMAP_PTE_OS3 "boot"
260
261 #if defined(PMAP_MI)
262 #include <aarch64/pmap_machdep.h>
263 #else
264
265 #define PMAP_NEED_PROCWR
266 #define PMAP_GROWKERNEL
267 #define PMAP_STEAL_MEMORY
268
269 #define __HAVE_VM_PAGE_MD
270 #define __HAVE_PMAP_PV_TRACK 1
271
272 struct pmap {
273 kmutex_t pm_lock;
274 struct pool *pm_pvpool;
275 pd_entry_t *pm_l0table; /* L0 table: 512G*512 */
276 paddr_t pm_l0table_pa;
277
278 LIST_HEAD(, vm_page) pm_vmlist; /* for L[0123] tables */
279 LIST_HEAD(, pv_entry) pm_pvlist; /* all pv of this process */
280
281 struct pmap_statistics pm_stats;
282 unsigned int pm_refcnt;
283 unsigned int pm_idlepdp;
284
285 kcpuset_t *pm_onproc;
286 kcpuset_t *pm_active;
287
288 struct pmap_asid_info pm_pai[PMAP_TLB_MAX];
289 bool pm_activated;
290 };
291
292 static inline paddr_t
pmap_l0pa(struct pmap * pm)293 pmap_l0pa(struct pmap *pm)
294 {
295 return pm->pm_l0table_pa;
296 }
297
298
299 /*
300 * should be kept <=32 bytes sized to reduce memory consumption & cache misses,
301 * but it doesn't...
302 */
303 struct pv_entry {
304 struct pv_entry *pv_next;
305 struct pmap *pv_pmap;
306 vaddr_t pv_va; /* for embedded entry (pp_pv) also includes flags */
307 void *pv_ptep; /* pointer for fast pte lookup */
308 LIST_ENTRY(pv_entry) pv_proc; /* belonging to the process */
309 };
310
311 struct pmap_page {
312 kmutex_t pp_pvlock;
313 struct pv_entry pp_pv;
314 };
315
316 /* try to keep vm_page at or under 128 bytes to reduce cache misses */
317 struct vm_page_md {
318 struct pmap_page mdpg_pp;
319 };
320 /* for page descriptor page only */
321 #define mdpg_ptep_parent mdpg_pp.pp_pv.pv_ptep
322
323 #define VM_MDPAGE_INIT(pg) \
324 do { \
325 PMAP_PAGE_INIT(&(pg)->mdpage.mdpg_pp); \
326 } while (/*CONSTCOND*/ 0)
327
328 #define PMAP_PAGE_INIT(pp) \
329 do { \
330 mutex_init(&(pp)->pp_pvlock, MUTEX_NODEBUG, IPL_NONE); \
331 (pp)->pp_pv.pv_next = NULL; \
332 (pp)->pp_pv.pv_pmap = NULL; \
333 (pp)->pp_pv.pv_va = 0; \
334 (pp)->pp_pv.pv_ptep = NULL; \
335 } while (/*CONSTCOND*/ 0)
336
337 /* saved permission bit for referenced/modified emulation */
338 #define LX_BLKPAG_OS_READ LX_BLKPAG_OS_0
339 #define LX_BLKPAG_OS_WRITE LX_BLKPAG_OS_1
340 #define LX_BLKPAG_OS_RWMASK (LX_BLKPAG_OS_WRITE | LX_BLKPAG_OS_READ)
341
342 #define PMAP_PTE_OS0 "read"
343 #define PMAP_PTE_OS1 "write"
344
345 #define VTOPHYS_FAILED ((paddr_t)-1L) /* POOL_PADDR_INVALID */
346 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va))
347
348 #ifndef KASAN
349 #define PMAP_MAP_POOLPAGE(pa) AARCH64_PA_TO_KVA(pa)
350 #define PMAP_UNMAP_POOLPAGE(va) AARCH64_KVA_TO_PA(va)
351
352 #define PMAP_DIRECT
353 static __inline int
pmap_direct_process(paddr_t pa,voff_t pgoff,size_t len,int (* process)(void *,size_t,void *),void * arg)354 pmap_direct_process(paddr_t pa, voff_t pgoff, size_t len,
355 int (*process)(void *, size_t, void *), void *arg)
356 {
357 vaddr_t va = AARCH64_PA_TO_KVA(pa);
358
359 return process((void *)(va + pgoff), len, arg);
360 }
361 #endif
362
363 /* l3pte contains always page entries */
364 static inline uint64_t
pte_value(pt_entry_t pte)365 pte_value(pt_entry_t pte)
366 {
367 return pte;
368 }
369
370 static inline bool
pte_valid_p(pt_entry_t pte)371 pte_valid_p(pt_entry_t pte)
372 {
373 return l3pte_valid(pte);
374 }
375
376 pt_entry_t *kvtopte(vaddr_t);
377
378 #define pmap_update(pmap) ((void)0)
379 #define pmap_copy(dp,sp,d,l,s) ((void)0)
380 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
381 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
382
383 struct pmap *
384 pmap_efirt(void);
385 void pmap_activate_efirt(void);
386 void pmap_deactivate_efirt(void);
387
388 void pmap_procwr(struct proc *, vaddr_t, int);
389 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t);
390
391 void pmap_pv_init(void);
392 void pmap_pv_track(paddr_t, psize_t);
393 void pmap_pv_untrack(paddr_t, psize_t);
394 void pmap_pv_protect(paddr_t, vm_prot_t);
395
396 vsize_t pmap_kenter_range(vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int);
397
398 #define PMAP_MAPSIZE1 L2_SIZE
399
400 /* for ddb */
401 void pmap_db_pmap_print(struct pmap *, void (*)(const char *, ...) __printflike(1, 2));
402 void pmap_db_mdpg_print(struct vm_page *, void (*)(const char *, ...) __printflike(1, 2));
403
404 #endif /* !PMAP_MI */
405
406 #endif /* _KERNEL */
407
408 #elif defined(__arm__)
409
410 #include <arm/pmap.h>
411
412 #endif /* __arm__/__aarch64__ */
413
414 #endif /* !_AARCH64_PMAP_ */
415