1 /* $NetBSD: dec_2100_a50.c,v 1.68 2020/09/04 03:41:49 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
5 * All rights reserved.
6 *
7 * Author: Chris G. Demetriou
8 *
9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation.
14 *
15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 *
19 * Carnegie Mellon requests users of this software to return to
20 *
21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
22 * School of Computer Science
23 * Carnegie Mellon University
24 * Pittsburgh PA 15213-3890
25 *
26 * any improvements or extensions that they make and grant Carnegie the
27 * rights to redistribute these changes.
28 */
29 /*
30 * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
31 */
32
33 #include "opt_kgdb.h"
34
35 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
36
37 __KERNEL_RCSID(0, "$NetBSD: dec_2100_a50.c,v 1.68 2020/09/04 03:41:49 thorpej Exp $");
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/device.h>
42 #include <sys/lwp.h>
43 #include <sys/termios.h>
44
45 #include <sys/conf.h>
46 #include <dev/cons.h>
47
48 #include <machine/rpb.h>
49 #include <machine/alpha.h>
50 #include <machine/autoconf.h>
51 #include <machine/cpuconf.h>
52 #include <sys/bus.h>
53
54 #include <dev/ic/comreg.h>
55 #include <dev/ic/comvar.h>
56
57 #include <dev/isa/isareg.h>
58 #include <dev/isa/isavar.h>
59 #include <dev/ic/i8042reg.h>
60 #include <dev/ic/pckbcvar.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63
64 #include <alpha/pci/apecsreg.h>
65 #include <alpha/pci/apecsvar.h>
66 #include <machine/logout.h>
67
68 #include <dev/scsipi/scsi_all.h>
69 #include <dev/scsipi/scsipi_all.h>
70 #include <dev/scsipi/scsiconf.h>
71
72 #include "pckbd.h"
73
74 #ifndef CONSPEED
75 #define CONSPEED TTYDEF_SPEED
76 #endif
77 static int comcnrate = CONSPEED;
78
79 void dec_2100_a50_init(void);
80 static void dec_2100_a50_cons_init(void);
81 static void dec_2100_a50_device_register(device_t, void *);
82
83 static void dec_2100_a50_mcheck_handler
84 (unsigned long, struct trapframe *, unsigned long, unsigned long);
85
86 static void dec_2100_a50_mcheck(unsigned long, unsigned long,
87 unsigned long, struct trapframe *);
88
89
90 #ifdef KGDB
91 #include <machine/db_machdep.h>
92
93 static const char *kgdb_devlist[] = {
94 "com",
95 NULL,
96 };
97 #endif /* KGDB */
98
99 const struct alpha_variation_table dec_2100_a50_variations[] = {
100 { SV_ST_AVANTI, "AlphaStation 400 4/233 (\"Avanti\")" },
101 { SV_ST_MUSTANG2_4_166, "AlphaStation 200 4/166 (\"Mustang II\")" },
102 { SV_ST_MUSTANG2_4_233, "AlphaStation 200 4/233 (\"Mustang II\")" },
103 { SV_ST_AVANTI_4_266, "AlphaStation 250 4/266" },
104 { SV_ST_MUSTANG2_4_100, "AlphaStation 200 4/100 (\"Mustang II\")" },
105 { SV_ST_AVANTI_4_233, "AlphaStation 255/233" },
106 { 0, NULL },
107 };
108
109 void
dec_2100_a50_init(void)110 dec_2100_a50_init(void)
111 {
112 uint64_t variation;
113
114 platform.family = "AlphaStation 200/400 (\"Avanti\")";
115
116 if ((platform.model = alpha_dsr_sysname()) == NULL) {
117 variation = hwrpb->rpb_variation & SV_ST_MASK;
118 if (variation == SV_ST_AVANTI_XXX) {
119 /* XXX apparently the same? */
120 variation = SV_ST_AVANTI;
121 }
122 if ((platform.model = alpha_variation_name(variation,
123 dec_2100_a50_variations)) == NULL)
124 platform.model = alpha_unknown_sysname();
125 }
126
127 platform.iobus = "apecs";
128 platform.cons_init = dec_2100_a50_cons_init;
129 platform.device_register = dec_2100_a50_device_register;
130 platform.mcheck_handler = dec_2100_a50_mcheck_handler;
131
132 }
133
134 static void
dec_2100_a50_cons_init(void)135 dec_2100_a50_cons_init(void)
136 {
137 struct ctb *ctb;
138 struct apecs_config *acp;
139 extern struct apecs_config apecs_configuration;
140
141 acp = &apecs_configuration;
142 apecs_init(acp, 0);
143
144 ctb = (struct ctb *)(((char *)hwrpb) + hwrpb->rpb_ctb_off);
145
146 switch (ctb->ctb_term_type) {
147 case CTB_PRINTERPORT:
148 /* serial console ... */
149 /* XXX */
150 {
151 /*
152 * Delay to allow PROM putchars to complete.
153 * FIFO depth * character time,
154 * character time = (1000000 / (defaultrate / 10))
155 */
156 DELAY(160000000 / comcnrate);
157
158 if(comcnattach(&acp->ac_iot, 0x3f8, comcnrate,
159 COM_FREQ, COM_TYPE_NORMAL,
160 (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8))
161 panic("can't init serial console");
162
163 break;
164 }
165
166 case CTB_GRAPHICS:
167 #if NPCKBD > 0
168 /* display console ... */
169 /* XXX */
170 (void) pckbc_cnattach(&acp->ac_iot, IO_KBD, KBCMDP,
171 PCKBC_KBD_SLOT, 0);
172
173 if (CTB_TURBOSLOT_TYPE(ctb->ctb_turboslot) ==
174 CTB_TURBOSLOT_TYPE_ISA)
175 isa_display_console(&acp->ac_iot, &acp->ac_memt);
176 else
177 pci_display_console(&acp->ac_iot, &acp->ac_memt,
178 &acp->ac_pc, CTB_TURBOSLOT_BUS(ctb->ctb_turboslot),
179 CTB_TURBOSLOT_SLOT(ctb->ctb_turboslot), 0);
180 #else
181 panic("not configured to use display && keyboard console");
182 #endif
183 break;
184
185 default:
186 printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
187 printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
188
189 panic("consinit: unknown console type %ld",
190 ctb->ctb_term_type);
191 }
192 #ifdef KGDB
193 /* Attach the KGDB device. */
194 alpha_kgdb_init(kgdb_devlist, &acp->ac_iot);
195 #endif /* KGDB */
196 }
197
198 static void
dec_2100_a50_device_register(device_t dev,void * aux)199 dec_2100_a50_device_register(device_t dev, void *aux)
200 {
201 static int found, initted, diskboot, netboot;
202 static device_t pcidev, ctrlrdev;
203 struct bootdev_data *b = bootdev_data;
204 device_t parent = device_parent(dev);
205
206 if (found)
207 return;
208
209 if (!initted) {
210 diskboot = (strcasecmp(b->protocol, "SCSI") == 0);
211 netboot = (strcasecmp(b->protocol, "BOOTP") == 0) ||
212 (strcasecmp(b->protocol, "MOP") == 0);
213 #if 0
214 printf("diskboot = %d, netboot = %d\n", diskboot, netboot);
215 #endif
216 initted =1;
217 }
218
219 if (pcidev == NULL) {
220 if (!device_is_a(dev, "pci"))
221 return;
222 else {
223 struct pcibus_attach_args *pba = aux;
224
225 if ((b->slot / 1000) != pba->pba_bus)
226 return;
227
228 pcidev = dev;
229 #if 0
230 printf("\npcidev = %s\n", device_xname(dev));
231 #endif
232 return;
233 }
234 }
235
236 if (ctrlrdev == NULL) {
237 if (parent != pcidev)
238 return;
239 else {
240 struct pci_attach_args *pa = aux;
241 int slot;
242
243 slot = pa->pa_bus * 1000 + pa->pa_function * 100 +
244 pa->pa_device;
245 if (b->slot != slot)
246 return;
247
248 if (netboot) {
249 booted_device = dev;
250 #if 0
251 printf("\nbooted_device = %s\n", device_xname(dev));
252 #endif
253 found = 1;
254 } else {
255 ctrlrdev = dev;
256 #if 0
257 printf("\nctrlrdev = %s\n", device_xname(dev));
258 #endif
259 }
260 return;
261 }
262 }
263
264 if (!diskboot)
265 return;
266
267 if (device_is_a(dev, "sd") ||
268 device_is_a(dev, "st") ||
269 device_is_a(dev, "cd")) {
270 struct scsipibus_attach_args *sa = aux;
271 struct scsipi_periph *periph = sa->sa_periph;
272 int unit;
273
274 if (device_parent(parent) != ctrlrdev)
275 return;
276
277 unit = periph->periph_target * 100 + periph->periph_lun;
278 if (b->unit != unit)
279 return;
280 if (b->channel != periph->periph_channel->chan_channel)
281 return;
282
283 /* we've found it! */
284 booted_device = dev;
285 #if 0
286 printf("\nbooted_device = %s\n", device_xname(dev));
287 #endif
288 found = 1;
289 }
290 }
291
292
293 static void
dec_2100_a50_mcheck(unsigned long mces,unsigned long type,unsigned long logout,struct trapframe * framep)294 dec_2100_a50_mcheck(unsigned long mces, unsigned long type, unsigned long logout, struct trapframe *framep)
295 {
296 struct mchkinfo *mcp;
297 static const char *fmt1 = " %-25s = 0x%016lx\n";
298 int i, sysaddr;
299 mc_hdr_avanti *hdr;
300 mc_uc_avanti *ptr;
301
302 /*
303 * If we expected a machine check, just go handle it in common code.
304 */
305 mcp = &curcpu()->ci_mcinfo;
306 if (mcp->mc_expected) {
307 machine_check(mces, framep, type, logout);
308 return;
309 }
310
311 hdr = (mc_hdr_avanti *) logout;
312 ptr = (mc_uc_avanti *) (logout + sizeof (*hdr));
313
314 printf(" Processor Machine Check (%lx), Code 0x%lx\n",
315 type, hdr->mcheck_code);
316 printf("CPU state:\n");
317 /* Print PAL fields */
318 for (i = 0; i < 32; i += 2) {
319 printf("\tPAL temp[%d-%d]\t\t= 0x%16lx 0x%16lx\n", i, i+1,
320 ptr->paltemp[i], ptr->paltemp[i+1]);
321 }
322 printf(fmt1, "Excepting Instruction Addr", ptr->exc_addr);
323 printf(fmt1, "Summary of arithmetic traps", ptr->exc_sum);
324 printf(fmt1, "Exception mask", ptr->exc_mask);
325 printf(fmt1, "ICCSR", ptr->iccsr);
326 printf(fmt1, "Base address for PALcode", ptr->pal_base);
327 printf(fmt1, "HIER", ptr->hier);
328 printf(fmt1, "HIRR", ptr->hirr);
329 printf(fmt1, "MM_CSR", ptr->mm_csr);
330 printf(fmt1, "DC_STAT", ptr->dc_stat);
331 printf(fmt1, "DC_ADDR", ptr->dc_addr);
332 printf(fmt1, "ABOX_CTL", ptr->abox_ctl);
333 printf(fmt1, "Bus Interface Unit status", ptr->biu_stat);
334 printf(fmt1, "Bus Interface Unit addr", ptr->biu_addr);
335 printf(fmt1, "Bus Interface Unit control", ptr->biu_ctl);
336 printf(fmt1, "Fill Syndrome", ptr->fill_syndrome);
337 printf(fmt1, "Fill Address", ptr->fill_addr);
338 printf(fmt1, "Effective VA", ptr->va);
339 printf(fmt1, "BC_TAG", ptr->bc_tag);
340
341 printf("\nCache and Memory Controller (21071-CA) state:\n");
342 printf(fmt1, "COMA_GCR", ptr->coma_gcr);
343 printf(fmt1, "COMA_EDSR", ptr->coma_edsr);
344 printf(fmt1, "COMA_TER", ptr->coma_ter);
345 printf(fmt1, "COMA_ELAR", ptr->coma_elar);
346 printf(fmt1, "COMA_EHAR", ptr->coma_ehar);
347 printf(fmt1, "COMA_LDLR", ptr->coma_ldlr);
348 printf(fmt1, "COMA_LDHR", ptr->coma_ldhr);
349 printf(fmt1, "COMA_BASE0", ptr->coma_base0);
350 printf(fmt1, "COMA_BASE1", ptr->coma_base1);
351 printf(fmt1, "COMA_BASE2", ptr->coma_base2);
352 printf(fmt1, "COMA_CNFG0", ptr->coma_cnfg0);
353 printf(fmt1, "COMA_CNFG1", ptr->coma_cnfg1);
354 printf(fmt1, "COMA_CNFG2", ptr->coma_cnfg2);
355
356 printf("\nPCI bridge (21071-DA) state:\n");
357
358 printf(fmt1, "EPIC Diag. control/status", ptr->epic_dcsr);
359 printf(fmt1, "EPIC_PEAR", ptr->epic_pear);
360 printf(fmt1, "EPIC_SEAR", ptr->epic_sear);
361 printf(fmt1, "EPIC_TBR1", ptr->epic_tbr1);
362 printf(fmt1, "EPIC_TBR2", ptr->epic_tbr2);
363 printf(fmt1, "EPIC_PBR1", ptr->epic_pbr1);
364 printf(fmt1, "EPIC_PBR2", ptr->epic_pbr2);
365 printf(fmt1, "EPIC_PMR1", ptr->epic_pmr1);
366 printf(fmt1, "EPIC_PMR2", ptr->epic_pmr2);
367 printf(fmt1, "EPIC_HARX1", ptr->epic_harx1);
368 printf(fmt1, "EPIC_HARX2", ptr->epic_harx2);
369 printf(fmt1, "EPIC_PMLT", ptr->epic_pmlt);
370 printf(fmt1, "EPIC_TAG0", ptr->epic_tag0);
371 printf(fmt1, "EPIC_TAG1", ptr->epic_tag1);
372 printf(fmt1, "EPIC_TAG2", ptr->epic_tag2);
373 printf(fmt1, "EPIC_TAG3", ptr->epic_tag3);
374 printf(fmt1, "EPIC_TAG4", ptr->epic_tag4);
375 printf(fmt1, "EPIC_TAG5", ptr->epic_tag5);
376 printf(fmt1, "EPIC_TAG6", ptr->epic_tag6);
377 printf(fmt1, "EPIC_TAG7", ptr->epic_tag7);
378 printf(fmt1, "EPIC_DATA0", ptr->epic_data0);
379 printf(fmt1, "EPIC_DATA1", ptr->epic_data1);
380 printf(fmt1, "EPIC_DATA2", ptr->epic_data2);
381 printf(fmt1, "EPIC_DATA3", ptr->epic_data3);
382 printf(fmt1, "EPIC_DATA4", ptr->epic_data4);
383 printf(fmt1, "EPIC_DATA5", ptr->epic_data5);
384 printf(fmt1, "EPIC_DATA6", ptr->epic_data6);
385 printf(fmt1, "EPIC_DATA7", ptr->epic_data7);
386
387 printf("\n");
388
389 if (type == ALPHA_SYS_MCHECK) {
390 printf("\nPCI bridge fault\n");
391 switch(hdr->mcheck_code) {
392 case AVANTI_RETRY_TIMEOUT:
393 printf("\tRetry timeout error accessing 0x%08lx.\n",
394 ptr->epic_pear & 0xffffffff);
395 break;
396
397 case AVANTI_DMA_DATA_PARITY:
398 printf("\tDMA data parity error accessing 0x%08lx.\n",
399 ptr->epic_pear & 0xffffffff);
400 break;
401
402 case AVANTI_IO_PARITY:
403 printf("\tI/O parity error at 0x%08lx during PCI cycle 0x%0lx.\n",
404 ptr->epic_pear & 0xffffffff,
405 (ptr->epic_dcsr >> 18) & 0xf);
406 break;
407
408 case AVANTI_TARGET_ABORT:
409 printf("\tPCI target abort at 0x%08lx during PCI cycle 0x%0lx.\n",
410 ptr->epic_pear & 0xffffffff,
411 (ptr->epic_dcsr >> 18) & 0xf);
412 break;
413
414 case AVANTI_NO_DEVICE:
415 printf("\tNo device responded at 0x%08lx during PCI cycle 0x%0lx\n.",
416 ptr->epic_pear & 0xffffffff,
417 (ptr->epic_dcsr >> 18) & 0xf);
418 break;
419
420 case AVANTI_CORRRECTABLE_MEMORY:
421 printf("\tCorrectable memory error reported.\n"
422 "\tWARNING ECC not implemented on this system!\n"
423 "\tError is incorrect.\n");
424 break;
425
426 case AVANTI_UNCORRECTABLE_PCI_MEMORY:
427 printf("\tUncorrectable memory error at %016lx reported "
428 "during DMA read.\n",
429 (ptr->epic_sear & 0xfffffff0) << 2);
430 break;
431
432 case AVANTI_INVALID_PT_LOOKUP:
433 printf("\tInvalid page table lookup during scatter/gather.\n" );
434 if (ptr->epic_dcsr & 0xf20)
435 printf("\tAddress lost.\n");
436 else
437 printf("\tBus address to 0x%08lx, PCI cycle 0x%0lx\n",
438 ptr->epic_pear & 0xffffffff,
439 (ptr->epic_dcsr >> 18) & 0xf);
440 break;
441
442 case AVANTI_MEMORY:
443 printf("\tMemory error at %016lx, ",
444 (ptr->epic_sear & 0xfffffff0) << 2);
445 sysaddr = (ptr->epic_sear & 0xffffffff) >> 21;
446 if (sysaddr >= ((ptr->coma_base0 >> 5) & 0x7ff) &&
447 sysaddr < (((ptr->coma_base0 >> 5) & 0x7ff) +
448 (1 << (7 - (ptr->coma_cnfg0 >> 1)))))
449 printf("SIMM bank 0\n");
450 else if (sysaddr >= ((ptr->coma_base1 >> 5) & 0x7ff) &&
451 sysaddr < (((ptr->coma_base1 >> 5) & 0x7ff) +
452 (1 << (7 - (ptr->coma_cnfg1 >> 1)))))
453 printf("SIMM bank 1\n");
454 else if (sysaddr >= ((ptr->coma_base2 >> 5) & 0x7ff) &&
455 sysaddr < (((ptr->coma_base2 >> 5) & 0x7ff) +
456 (1 << (7 - (ptr->coma_cnfg2 >> 1)))))
457 printf("SIMM bank 2\n");
458 else
459 printf("invalid memory bank?\n");
460 break;
461
462 case AVANTI_BCACHE_TAG_ADDR_PARITY:
463 printf("\tBcache tag address parity error, caused by ");
464 if (ptr->coma_edsr & 0x20)
465 printf("victim write\n");
466 else if (ptr->coma_edsr & 0x10)
467 printf("DMA. ioCmd<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
468 else
469 printf("CPU. cpuCReq<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
470 break;
471
472 case AVANTI_BCACHE_TAG_CTRL_PARITY:
473 printf("\tBcache tag control parity error, caused by ");
474 if (ptr->coma_edsr & 0x20)
475 printf("victim write\n");
476 else if (ptr->coma_edsr & 0x10)
477 printf("DMA. ioCmd<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
478 else
479 printf("CPU. cpuCReq<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
480 break;
481
482 case AVANTI_NONEXISTENT_MEMORY:
483 printf("\tNonexistent memory error, caused by ");
484 if (ptr->coma_edsr & 0x20)
485 printf("victim write\n");
486 else if (ptr->coma_edsr & 0x10)
487 printf("DMA. ioCmd<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
488 else
489 printf("CPU. cpuCReq<2:0> = %0lx\n", (ptr->coma_edsr >> 6) & 7);
490 break;
491
492 case AVANTI_IO_BUS:
493 printf("\tI/O bus error at %08lx during PCI cycle %0lx\n",
494 ptr->epic_pear & 0xffffffff, (ptr->epic_dcsr >> 18) & 0xf);
495 break;
496
497 case AVANTI_BCACHE_TAG_PARITY:
498 printf("\tBcache tag address parity error.\n"
499 "\tcReg_h cycle %0lx, address<7:0> 0x%02lx\n",
500 (ptr->biu_stat >> 4) & 7,
501 ptr->biu_addr & 0xff);
502 break;
503
504 case AVANTI_BCACHE_TAG_CTRL_PARITY2:
505 printf("\tBcache tag control parity error.\n"
506 "\tcReg_h cycle %0lx, address<7:0> 0x%02lx\n",
507 (ptr->biu_stat >> 4) & 7,
508 ptr->biu_addr & 0xff);
509 break;
510
511 }
512 } else { /* ALPHA_PROC_MCHECK */
513 printf("\nProcessor fault\n");
514 switch(hdr->mcheck_code) {
515 case AVANTI_HARD_ERROR:
516 printf("\tHard error cycle.\n");
517 break;
518
519 case AVANTI_CORRECTABLE_ECC:
520 printf("\tCorrectable ECC error.\n"
521 "\tWARNING ECC not implemented on this system!\n"
522 "\tError is incorrect.\n");
523 break;
524
525 case AVANTI_NONCORRECTABLE_ECC:
526 printf("\tNoncorrectable ECC error.\n"
527 "\tWARNING ECC not implemented on this system!\n"
528 "\tError is incorrect.\n");
529 break;
530
531 case AVANTI_UNKNOWN_ERROR:
532 printf("\tUnknown error.\n");
533 break;
534
535 case AVANTI_SOFT_ERROR:
536 printf("\tSoft error cycle.\n");
537 break;
538
539 case AVANTI_BUGCHECK:
540 printf("\tBugcheck.\n");
541 break;
542
543 case AVANTI_OS_BUGCHECK:
544 printf("\tOS Bugcheck.\n");
545 break;
546
547 case AVANTI_DCACHE_FILL_PARITY:
548 printf("\tPrimary Dcache data fill parity error.\n"
549 "\tDcache Quadword %lx, address %08lx\n",
550 (ptr->biu_stat >> 12) & 0x3,
551 (ptr->fill_addr >> 8) & 0x7f);
552 break;
553
554 case AVANTI_ICACHE_FILL_PARITY:
555 printf("\tPrimary Icache data fill parity error.\n"
556 "\tDcache Quadword %lx, address %08lx\n",
557 (ptr->biu_stat >> 12) & 0x3,
558 (ptr->fill_addr >> 8) & 0x7f);
559 break;
560 }
561 }
562
563 /*
564 * Now that we've printed all sorts of useful information
565 * and have decided that we really can't do any more to
566 * respond to the error, go on to the common code for
567 * final disposition. Usually this means that we die.
568 */
569 /*
570 * XXX: HANDLE PCI ERRORS HERE?
571 */
572 machine_check(mces, framep, type, logout);
573 }
574
575 static void
dec_2100_a50_mcheck_handler(unsigned long mces,struct trapframe * framep,unsigned long vector,unsigned long param)576 dec_2100_a50_mcheck_handler(unsigned long mces, struct trapframe *framep, unsigned long vector, unsigned long param)
577 {
578 switch (vector) {
579 case ALPHA_SYS_MCHECK:
580 case ALPHA_PROC_MCHECK:
581 dec_2100_a50_mcheck(mces, vector, param, framep);
582 break;
583 default:
584 printf("2100_A50_MCHECK: unknown check vector 0x%lx\n", vector);
585 machine_check(mces, framep, vector, param);
586 break;
587 }
588 }
589