1 /* $NetBSD: c_nec_eisa.c,v 1.18 2018/02/08 09:05:17 dholland Exp $ */
2
3 /*-
4 * Copyright (c) 2003 Izumi Tsutsui. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*-
28 * Copyright (C) 2000 Shuichiro URATA. All rights reserved.
29 *
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions
32 * are met:
33 * 1. Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * 2. Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in the
37 * documentation and/or other materials provided with the distribution.
38 * 3. The name of the author may not be used to endorse or promote products
39 * derived from this software without specific prior written permission.
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 */
52
53 /*
54 * for NEC EISA generation machines.
55 */
56
57 #include <sys/cdefs.h>
58 __KERNEL_RCSID(0, "$NetBSD: c_nec_eisa.c,v 1.18 2018/02/08 09:05:17 dholland Exp $");
59
60 #define __INTR_PRIVATE
61 #include <sys/param.h>
62 #include <sys/systm.h>
63 #include <sys/kcore.h>
64 #include <sys/device.h>
65 #include <sys/intr.h>
66
67 #include <uvm/uvm_extern.h>
68
69 #include <mips/locore.h>
70
71 #include <machine/autoconf.h>
72 #include <machine/pio.h>
73 #include <machine/platform.h>
74 #include <machine/wired_map.h>
75 #include <mips/pte.h>
76
77 #include <dev/isa/isavar.h>
78
79 #include <arc/arc/arcbios.h>
80 #include <arc/jazz/pica.h>
81 #include <arc/jazz/rd94.h>
82 #include <arc/jazz/jazziovar.h>
83 #include <arc/isa/isabrvar.h>
84
85 #include "vga_isa.h"
86 #if NVGA_ISA > 0
87 #include <dev/ic/mc6845reg.h>
88 #include <dev/ic/pcdisplayvar.h>
89 #include <dev/ic/vgareg.h>
90 #include <dev/ic/vgavar.h>
91
92 #ifdef VGA_RESET
93 static void gd54xx_initregs(struct vga_handle *);
94 #endif
95 #endif
96
97 /*
98 * chipset-dependent isa bus configuration
99 */
100
101 int isabr_nec_eisa_intr_status(void);
102
103 struct isabr_config isabr_nec_eisa_conf = {
104 isabr_nec_eisa_intr_status,
105 };
106
107 /*
108 * This is a mask of bits to clear in the SR when we go to a
109 * given interrupt priority level.
110 */
111 static const struct ipl_sr_map nec_eisa_ipl_sr_map = {
112 .sr_bits = {
113 [IPL_NONE] = 0,
114 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
115 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
116 [IPL_VM] = MIPS_SOFT_INT_MASK
117 | MIPS_INT_MASK_0
118 | MIPS_INT_MASK_1
119 | MIPS_INT_MASK_2,
120 [IPL_SCHED] = MIPS_INT_MASK,
121 [IPL_DDB] = MIPS_INT_MASK,
122 [IPL_HIGH] = MIPS_INT_MASK,
123 },
124 };
125
126 int
isabr_nec_eisa_intr_status(void)127 isabr_nec_eisa_intr_status(void)
128 {
129
130 return in32(RD94_SYS_INTSTAT2) & (ICU_LEN - 1);
131 }
132
133 /*
134 * chipset-dependent jazzio bus configuration
135 */
136
137 void jazzio_nec_eisa_set_iointr_mask(int);
138
139 struct jazzio_config jazzio_nec_eisa_conf = {
140 RD94_SYS_INTSTAT1,
141 jazzio_nec_eisa_set_iointr_mask,
142 RD94_SYS_TL_BASE,
143 RD94_SYS_DMA0_REGS,
144 };
145
146 void
jazzio_nec_eisa_set_iointr_mask(int mask)147 jazzio_nec_eisa_set_iointr_mask(int mask)
148 {
149
150 out16(RD94_SYS_LB_IE2, mask);
151 }
152
153 /*
154 * critial i/o space, interrupt, and other chipset related initialization.
155 */
156 void
c_nec_eisa_init(void)157 c_nec_eisa_init(void)
158 {
159
160 /*
161 * Initialize interrupt priority
162 */
163 ipl_sr_map = nec_eisa_ipl_sr_map;
164
165 /*
166 * Initialize I/O address offset
167 */
168 arc_bus_space_init(&jazzio_bus, "jazzio",
169 RD94_P_LOCAL_IO_BASE, RD94_V_LOCAL_IO_BASE,
170 RD94_V_LOCAL_IO_BASE, RD94_S_LOCAL_IO_BASE);
171
172 arc_bus_space_init(&arc_bus_io, "r94eisaio",
173 RD94_P_PCI_IO, RD94_V_EISA_IO, 0, RD94_S_EISA_IO);
174 arc_bus_space_init(&arc_bus_mem, "r94eisamem",
175 RD94_P_PCI_MEM, RD94_V_EISA_MEM, 0, RD94_S_EISA_MEM);
176
177 /*
178 * Initialize wired TLB for I/O space which is used on early stage
179 */
180 arc_init_wired_map();
181 arc_wired_enter_page(RD94_V_LOCAL_IO_BASE, RD94_P_LOCAL_IO_BASE,
182 RD94_S_LOCAL_IO_BASE);
183
184 arc_wired_enter_page(RD94_V_EISA_IO, RD94_P_EISA_IO, RD94_S_EISA_IO);
185 arc_wired_enter_page(RD94_V_EISA_MEM, RD94_P_EISA_MEM,
186 MIPS3_PG_SIZE_MASK_TO_SIZE(MIPS3_PG_SIZE_16M));
187
188 /*
189 * Disable all interrupts. New masks will be set up
190 * during system configuration
191 */
192 out16(RD94_SYS_LB_IE1, 0);
193 out16(RD94_SYS_LB_IE2, 0);
194 out32(RD94_SYS_EXT_IMASK, 0);
195
196 /*
197 * common configuration between NEC EISA and PCI platforms
198 */
199 c_nec_jazz_init();
200
201 /* common configuration for Magnum derived and NEC EISA machines */
202 c_jazz_eisa_init();
203
204 /* chipset-dependent isa bus configuration */
205 isabr_conf = &isabr_nec_eisa_conf;
206
207 /* chipset-dependent jazzio bus configuration */
208 jazzio_conf = &jazzio_nec_eisa_conf;
209 }
210
211 void
c_nec_eisa_cons_init(void)212 c_nec_eisa_cons_init(void)
213 {
214
215 #if NVGA_ISA > 0
216 if (!com_console) {
217 if (strcmp(arc_displayc_id, "necvdfrb") == 0) {
218 /* NEC RISCserver 2200 R4400 EISA [NEC-R96] */
219 /* NEC Express5800/240 R4400 EISA [NEC-J96A] */
220 #ifdef VGA_RESET
221 struct vga_handle handle;
222
223 handle.vh_memt = &arc_bus_mem;
224 handle.vh_iot = &arc_bus_io;
225 vga_reset(&handle, gd54xx_initregs);
226 #endif
227
228 vga_no_builtinfont = 1;
229 }
230 }
231 #endif
232
233 c_jazz_eisa_cons_init();
234 }
235
236 #if NVGA_ISA > 0 && defined(VGA_RESET)
237
238 /* values to initialize cirrus GD54xx specific ext registers */
239 /* XXX these values are taken from PC XXX */
240 static const uint8_t vga_ts_gd54xx[] = {
241 0x0f, /* 05: ??? */
242 0x12, /* 06: enable ext reg (?) */
243 0x00, /* 07: reset ext sequence (?) */
244 0x00, /* 08: ??? */
245 0x5c, /* 09: ??? */
246 0x09, /* 0A: BIOS Scratch register for 542x (?) */
247 0x4a, /* 0B: ??? */
248 0x5b, /* 0C: ??? */
249 0x42, /* 0D: VCLK2 frequency */
250 0x00, /* 0E: VCLK3 frequency */
251 0x09, /* 0F: ??? */
252 0x00, /* 10: ??? */
253 0x00, /* 11: ??? */
254 0x00, /* 12: ??? */
255 0x00, /* 13: ??? */
256 0x00, /* 14: BIOS scratch register for 546x (?) */
257 0x00, /* 15: ??? */
258 0xd8, /* 16: ??? */
259 0x39, /* 17: ??? */
260 0x00, /* 18: ??? */
261 0x01, /* 19: ??? */
262 0x00, /* 1A: ??? */
263 0x2b, /* 1B: ??? */
264 0x2f, /* 1C: ??? */
265 0x1f, /* 1D: VCLK2 denominator and post-scalar value */
266 0x00, /* 1E: VCLK3 denominator and post-scalar value */
267 0x19 /* 1F: MCLK (?) */
268 };
269
270 static void
gd54xx_initregs(struct vga_handle * vh)271 gd54xx_initregs(struct vga_handle *vh)
272 {
273 int i;
274
275 /* disable video */
276 vga_ts_write(vh, mode, vga_ts_read(vh, mode) | VGA_TS_MODE_BLANK);
277
278 /* enable access to GD54xx ext regs */
279 _vga_ts_write(vh, 0x06, 0x12);
280
281 /* setup GD54xx ext regs */
282 for (i = 0; i < sizeof(vga_ts_gd54xx); i++)
283 _vga_ts_write(vh, VGA_TS_NREGS + i, vga_ts_gd54xx[i]);
284
285 /* disable access to GD54xx ext regs */
286 _vga_ts_write(vh, 0x06, 0x0);
287
288 /* reenable video */
289 vga_ts_write(vh, mode, vga_ts_read(vh, mode) & ~VGA_TS_MODE_BLANK);
290 }
291 #endif
292