1 /* $NetBSD: db_interface.c,v 1.64 2022/10/26 23:38:06 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 1996 Scott K. Stevens
5 *
6 * Mach Operating System
7 * Copyright (c) 1991,1990 Carnegie Mellon University
8 * All Rights Reserved.
9 *
10 * Permission to use, copy, modify and distribute this software and its
11 * documentation is hereby granted, provided that both the copyright
12 * notice and this permission notice appear in all copies of the
13 * software, derivative works or modified versions, and any portions
14 * thereof, and that both notices appear in supporting documentation.
15 *
16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19 *
20 * Carnegie Mellon requests users of this software to return to
21 *
22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23 * School of Computer Science
24 * Carnegie Mellon University
25 * Pittsburgh PA 15213-3890
26 *
27 * any improvements or extensions that they make and grant Carnegie the
28 * rights to redistribute these changes.
29 *
30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU)
31 */
32
33 /*
34 * Interface to new debugger.
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.64 2022/10/26 23:38:06 riastradh Exp $");
39
40 #include "opt_ddb.h"
41 #include "opt_kgdb.h"
42 #include "opt_multiprocessor.h"
43
44 #include <sys/param.h>
45
46 #include <sys/atomic.h>
47 #include <sys/exec.h>
48 #include <sys/intr.h>
49 #include <sys/proc.h>
50 #include <sys/reboot.h>
51 #include <sys/systm.h> /* just for boothowto */
52
53 #include <uvm/uvm_extern.h>
54
55 #include <arm/arm32/db_machdep.h>
56 #include <arm/undefined.h>
57
58 #include <ddb/db_access.h>
59 #include <ddb/db_active.h>
60 #include <ddb/db_command.h>
61 #include <ddb/db_output.h>
62 #include <ddb/db_variables.h>
63 #include <ddb/db_sym.h>
64 #include <ddb/db_extern.h>
65 #include <ddb/db_interface.h>
66
67 #include <dev/cons.h>
68
69 #if defined(KGDB) || !defined(DDB)
70 #define db_printf printf
71 #endif
72
73 u_int db_fetch_reg(int, db_regs_t *);
74
75 int db_trapper(u_int, u_int, trapframe_t *, int);
76
77 int db_active = 0;
78 db_regs_t ddb_regs; /* register state */
79 db_regs_t *ddb_regp;
80
81 #ifdef MULTIPROCESSOR
82 volatile struct cpu_info *db_onproc;
83 volatile struct cpu_info *db_newcpu;
84 #endif
85
86
87
88
89 #ifdef DDB
90 /*
91 * kdb_trap - field a TRACE or BPT trap
92 */
93 int
kdb_trap(int type,db_regs_t * regs)94 kdb_trap(int type, db_regs_t *regs)
95 {
96 struct cpu_info * const ci = curcpu();
97 db_regs_t dbreg;
98 int s;
99
100 switch (type) {
101 case T_BREAKPOINT: /* breakpoint */
102 case -1: /* keyboard interrupt */
103 break;
104 #ifdef MULTIPROCESSOR
105 case -2:
106 /*
107 * We called to enter ddb from another process but by the time
108 * we got here, no one was in ddb. So ignore the request.
109 */
110 if (db_onproc == NULL)
111 return 1;
112 break;
113 #endif
114 default:
115 if (db_recover != 0) {
116 /* This will longjmp back into db_command_loop() */
117 db_error("Faulted in DDB; continuing...\n");
118 /*NOTREACHED*/
119 }
120 }
121
122 /* Should switch to kdb`s own stack here. */
123
124 #ifdef MULTIPROCESSOR
125 const bool is_mp_p = ncpu > 1;
126 if (is_mp_p) {
127 /*
128 * Try to take ownership of DDB. If we do, tell all other
129 * CPUs to enter DDB too.
130 */
131 if (atomic_cas_ptr(&db_onproc, NULL, ci) == NULL) {
132 intr_ipi_send(NULL, IPI_DDB);
133 }
134 }
135 for (;;) {
136 if (is_mp_p) {
137 /*
138 * While we aren't the master, wait until the master
139 * gives control to us or exits. If it exited, we
140 * just exit too. Otherwise this cpu will enter DDB.
141 */
142 membar_consumer();
143 while (db_onproc != ci) {
144 if (db_onproc == NULL)
145 return 1;
146 #ifdef _ARM_ARCH_6
147 __asm __volatile("wfe");
148 membar_consumer();
149 #endif
150 if (db_onproc == ci) {
151 printf("%s: switching to %s\n",
152 __func__, ci->ci_cpuname);
153 }
154 }
155 }
156 #endif
157
158 s = splhigh();
159 ci->ci_ddb_regs = &dbreg;
160 ddb_regp = &dbreg;
161 ddb_regs = *regs;
162
163 atomic_inc_32(&db_active);
164 cnpollc(true);
165 db_trap(type, 0/*code*/);
166 cnpollc(false);
167 atomic_dec_32(&db_active);
168
169 ci->ci_ddb_regs = NULL;
170 ddb_regp = &dbreg;
171 *regs = ddb_regs;
172 splx(s);
173
174 #ifdef MULTIPROCESSOR
175 if (is_mp_p && db_newcpu != NULL) {
176 db_onproc = db_newcpu;
177 db_newcpu = NULL;
178 dsb(ishst);
179 sev();
180 continue;
181 }
182 break;
183 }
184
185 if (is_mp_p) {
186 /*
187 * We are exiting DDB so there is noone onproc. Tell
188 * the other CPUs to exit.
189 */
190 db_onproc = NULL;
191 dsb(ishst);
192 sev();
193 }
194 #endif
195
196 return 1;
197 }
198 #endif
199
200 int
db_validate_address(vaddr_t addr)201 db_validate_address(vaddr_t addr)
202 {
203 struct proc *p = curproc;
204 struct pmap *pmap;
205
206 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap ||
207 addr >= VM_MIN_KERNEL_ADDRESS
208 )
209 pmap = pmap_kernel();
210 else
211 pmap = p->p_vmspace->vm_map.pmap;
212
213 return pmap_extract(pmap, addr, NULL) == false;
214 }
215
216 /*
217 * Read bytes from kernel address space for debugger.
218 */
219 void
db_read_bytes(vaddr_t addr,size_t size,char * data)220 db_read_bytes(vaddr_t addr, size_t size, char *data)
221 {
222 char *src = (char *)addr;
223
224 if (db_validate_address((u_int)src)) {
225 db_printf("address %p is invalid\n", src);
226 return;
227 }
228
229 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) {
230 *((int*)data) = *((int*)src);
231 return;
232 }
233
234 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) {
235 *((short*)data) = *((short*)src);
236 return;
237 }
238
239 while (size-- > 0) {
240 if (db_validate_address((u_int)src)) {
241 db_printf("address %p is invalid\n", src);
242 return;
243 }
244 *data++ = *src++;
245 }
246 }
247
248 static void
db_write_text(vaddr_t addr,size_t size,const char * data)249 db_write_text(vaddr_t addr, size_t size, const char *data)
250 {
251
252 ktext_write((void *)addr, data, size);
253 }
254
255 /*
256 * Write bytes to kernel address space for debugger.
257 */
258 void
db_write_bytes(vaddr_t addr,size_t size,const char * data)259 db_write_bytes(vaddr_t addr, size_t size, const char *data)
260 {
261 extern char kernel_text[];
262 extern char etext[];
263 char *dst;
264 size_t loop;
265
266 /* If any part is in kernel text, use db_write_text() */
267 if (addr >= (vaddr_t) kernel_text && addr < (vaddr_t) etext) {
268 db_write_text(addr, size, data);
269 return;
270 }
271
272 dst = (char *)addr;
273 if (db_validate_address((u_int)dst)) {
274 db_printf("address %p is invalid\n", dst);
275 return;
276 }
277
278 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0)
279 *((int*)dst) = *((const int *)data);
280 else
281 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0)
282 *((short*)dst) = *((const short *)data);
283 else {
284 loop = size;
285 while (loop-- > 0) {
286 if (db_validate_address((u_int)dst)) {
287 db_printf("address %p is invalid\n", dst);
288 return;
289 }
290 *dst++ = *data++;
291 }
292 }
293
294 /* make sure the caches and memory are in sync */
295 cpu_icache_sync_range(addr, size);
296
297 /* In case the current page tables have been modified ... */
298 cpu_tlb_flushID();
299 cpu_cpwait();
300 }
301
302 #ifdef DDB
303 void
cpu_Debugger(void)304 cpu_Debugger(void)
305 {
306 #ifdef _ARM_ARCH_BE8
307 __asm(".word 0xffffffe7");
308 #else
309 __asm(".word 0xe7ffffff");
310 #endif
311 }
312
313 int
db_trapper(u_int addr,u_int inst,trapframe_t * frame,int fault_code)314 db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code)
315 {
316
317 if (fault_code == 0) {
318 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK))
319 kdb_trap(T_BREAKPOINT, frame);
320 else
321 kdb_trap(-1, frame);
322 } else
323 return 1;
324 return 0;
325 }
326
327 extern u_int esym;
328 extern u_int end;
329
330 static struct undefined_handler db_uh;
331
332 void
db_machine_init(void)333 db_machine_init(void)
334 {
335
336 /*
337 * We get called before malloc() is available, so supply a static
338 * struct undefined_handler.
339 */
340 db_uh.uh_handler = db_trapper;
341 install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &db_uh);
342 }
343 #endif
344
345 u_int
db_fetch_reg(int reg,db_regs_t * regs)346 db_fetch_reg(int reg, db_regs_t *regs)
347 {
348
349 switch (reg) {
350 case 0:
351 return regs->tf_r0;
352 case 1:
353 return regs->tf_r1;
354 case 2:
355 return regs->tf_r2;
356 case 3:
357 return regs->tf_r3;
358 case 4:
359 return regs->tf_r4;
360 case 5:
361 return regs->tf_r5;
362 case 6:
363 return regs->tf_r6;
364 case 7:
365 return regs->tf_r7;
366 case 8:
367 return regs->tf_r8;
368 case 9:
369 return regs->tf_r9;
370 case 10:
371 return regs->tf_r10;
372 case 11:
373 return regs->tf_r11;
374 case 12:
375 return regs->tf_r12;
376 case 13:
377 return regs->tf_svc_sp;
378 case 14:
379 return regs->tf_svc_lr;
380 case 15:
381 return regs->tf_pc;
382 default:
383 panic("db_fetch_reg: botch");
384 }
385 }
386
387 u_int
branch_taken(u_int insn,u_int pc,db_regs_t * regs)388 branch_taken(u_int insn, u_int pc, db_regs_t *regs)
389 {
390 u_int addr, nregs;
391
392 switch ((insn >> 24) & 0xf) {
393 case 0xa: /* b ... */
394 case 0xb: /* bl ... */
395 addr = ((insn << 2) & 0x03ffffff);
396 if (addr & 0x02000000)
397 addr |= 0xfc000000;
398 return pc + 8 + addr;
399 case 0x7: /* ldr pc, [pc, reg, lsl #2] */
400 addr = db_fetch_reg(insn & 0xf, regs);
401 addr = pc + 8 + (addr << 2);
402 db_read_bytes(addr, 4, (char *)&addr);
403 return addr;
404 case 0x5: /* ldr pc, [reg] */
405 addr = db_fetch_reg((insn >> 16) & 0xf, regs);
406 db_read_bytes(addr, 4, (char *)&addr);
407 return addr;
408 case 0x1: /* mov pc, reg */
409 addr = db_fetch_reg(insn & 0xf, regs);
410 return addr;
411 case 0x8: /* ldmxx reg, {..., pc} */
412 case 0x9:
413 addr = db_fetch_reg((insn >> 16) & 0xf, regs);
414 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555);
415 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333);
416 nregs = (nregs + (nregs >> 4)) & 0x0f0f;
417 nregs = (nregs + (nregs >> 8)) & 0x001f;
418 switch ((insn >> 23) & 0x3) {
419 case 0x0: /* ldmda */
420 addr = addr - 0;
421 break;
422 case 0x1: /* ldmia */
423 addr = addr + 0 + ((nregs - 1) << 2);
424 break;
425 case 0x2: /* ldmdb */
426 addr = addr - 4;
427 break;
428 case 0x3: /* ldmib */
429 addr = addr + 4 + ((nregs - 1) << 2);
430 break;
431 }
432 db_read_bytes(addr, 4, (char *)&addr);
433 return addr;
434 default:
435 panic("branch_taken: botch");
436 }
437 }
438