1 /* $NetBSD: rk_dwhdmi.c,v 1.8 2023/04/11 08:40:19 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: rk_dwhdmi.c,v 1.8 2023/04/11 08:40:19 riastradh Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/conf.h>
35 #include <sys/device.h>
36 #include <sys/intr.h>
37 #include <sys/kernel.h>
38 #include <sys/systm.h>
39
40 #include <dev/fdt/fdt_port.h>
41 #include <dev/fdt/fdtvar.h>
42 #include <dev/fdt/syscon.h>
43
44 #include <dev/ic/dw_hdmi.h>
45
46 #include <drm/drm_drv.h>
47 #include <drm/drm_crtc_helper.h>
48
49 #define RK3399_GRF_SOC_CON20 0x6250
50 #define HDMI_LCDC_SEL __BIT(6)
51
52 static const struct dwhdmi_mpll_config rk_dwhdmi_mpll_config[] = {
53 { 40000, 0x00b3, 0x0000, 0x0018 },
54 { 65000, 0x0072, 0x0001, 0x0028 },
55 { 66000, 0x013e, 0x0003, 0x0038 },
56 { 83500, 0x0072, 0x0001, 0x0028 },
57 { 146250, 0x0051, 0x0002, 0x0038 },
58 { 148500, 0x0051, 0x0003, 0x0000 },
59 { 272000, 0x0040, 0x0003, 0x0000 },
60 { 340000, 0x0040, 0x0003, 0x0000 },
61 { 0, 0x0051, 0x0003, 0x0000 },
62 };
63
64 static const struct dwhdmi_phy_config rk_dwhdmi_phy_config[] = {
65 { 74250, 0x8009, 0x0004, 0x0272 },
66 { 148500, 0x802b, 0x0004, 0x028d },
67 { 297000, 0x8039, 0x0005, 0x028d },
68 { 594000, 0x8039, 0x0000, 0x019d },
69 { 0, 0x0000, 0x0000, 0x0000 }
70 };
71
72 enum {
73 DWHDMI_PORT_INPUT = 0,
74 DWHDMI_PORT_OUTPUT = 1,
75 };
76
77 static const struct device_compatible_entry compat_data[] = {
78 { .compat = "rockchip,rk3399-dw-hdmi" },
79 DEVICE_COMPAT_EOL
80 };
81
82 struct rk_dwhdmi_softc {
83 struct dwhdmi_softc sc_base;
84 int sc_phandle;
85 struct clk *sc_clk_vpll;
86
87 struct fdt_device_ports sc_ports;
88 struct drm_display_mode sc_curmode;
89 struct drm_encoder sc_encoder;
90 struct syscon *sc_grf;
91
92 bool sc_activated;
93 };
94
95 #define to_rk_dwhdmi_softc(x) container_of(x, struct rk_dwhdmi_softc, sc_base)
96 #define to_rk_dwhdmi_encoder(x) container_of(x, struct rk_dwhdmi_softc, sc_encoder)
97
98 static void
rk_dwhdmi_select_input(struct rk_dwhdmi_softc * sc,u_int crtc_index)99 rk_dwhdmi_select_input(struct rk_dwhdmi_softc *sc, u_int crtc_index)
100 {
101 const uint32_t write_mask = HDMI_LCDC_SEL << 16;
102 const uint32_t write_val = crtc_index == 0 ? HDMI_LCDC_SEL : 0;
103
104 syscon_lock(sc->sc_grf);
105 syscon_write_4(sc->sc_grf, RK3399_GRF_SOC_CON20, write_mask | write_val);
106 syscon_unlock(sc->sc_grf);
107 }
108
109 static void
rk_dwhdmi_encoder_enable(struct drm_encoder * encoder)110 rk_dwhdmi_encoder_enable(struct drm_encoder *encoder)
111 {
112 struct rk_dwhdmi_softc * const sc = to_rk_dwhdmi_encoder(encoder);
113 const u_int crtc_index = drm_crtc_index(encoder->crtc);
114
115 rk_dwhdmi_select_input(sc, crtc_index);
116 }
117
118 static const struct drm_encoder_funcs rk_dwhdmi_encoder_funcs = {
119 .destroy = drm_encoder_cleanup,
120 };
121
122 static const struct drm_encoder_helper_funcs rk_dwhdmi_encoder_helper_funcs = {
123 .enable = rk_dwhdmi_encoder_enable,
124 };
125
126 static int
rk_dwhdmi_ep_activate(device_t dev,struct fdt_endpoint * ep,bool activate)127 rk_dwhdmi_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate)
128 {
129 struct rk_dwhdmi_softc * const sc = device_private(dev);
130 struct fdt_endpoint *in_ep = fdt_endpoint_remote(ep);
131 struct fdt_endpoint *out_ep, *out_rep;
132 struct drm_crtc *crtc;
133 int error;
134
135 if (sc->sc_activated != false) {
136 return 0;
137 }
138
139 if (!activate)
140 return EINVAL;
141
142 if (fdt_endpoint_port_index(ep) != DWHDMI_PORT_INPUT)
143 return EINVAL;
144
145 switch (fdt_endpoint_type(in_ep)) {
146 case EP_DRM_CRTC:
147 crtc = fdt_endpoint_get_data(in_ep);
148 break;
149 default:
150 crtc = NULL;
151 break;
152 }
153
154 if (crtc == NULL)
155 return EINVAL;
156
157 sc->sc_encoder.possible_crtcs = 3; // 1U << drm_crtc_index(crtc); /* XXX */
158 drm_encoder_init(crtc->dev, &sc->sc_encoder, &rk_dwhdmi_encoder_funcs,
159 DRM_MODE_ENCODER_TMDS, NULL);
160 drm_encoder_helper_add(&sc->sc_encoder, &rk_dwhdmi_encoder_helper_funcs);
161
162 sc->sc_base.sc_connector.base.connector_type = DRM_MODE_CONNECTOR_HDMIA;
163 error = dwhdmi_bind(&sc->sc_base, &sc->sc_encoder);
164 if (error != 0)
165 return error;
166 sc->sc_activated = true;
167
168 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, DWHDMI_PORT_OUTPUT, 0);
169 if (out_ep != NULL) {
170 /* Ignore downstream connectors, we have our own. */
171 out_rep = fdt_endpoint_remote(out_ep);
172 if (out_rep != NULL && fdt_endpoint_type(out_rep) == EP_DRM_CONNECTOR)
173 return 0;
174
175 error = fdt_endpoint_activate(out_ep, activate);
176 if (error != 0)
177 return error;
178 }
179
180 return 0;
181 }
182
183 static void *
rk_dwhdmi_ep_get_data(device_t dev,struct fdt_endpoint * ep)184 rk_dwhdmi_ep_get_data(device_t dev, struct fdt_endpoint *ep)
185 {
186 struct rk_dwhdmi_softc * const sc = device_private(dev);
187
188 return &sc->sc_encoder;
189 }
190
191 static void
rk_dwhdmi_enable(struct dwhdmi_softc * dsc)192 rk_dwhdmi_enable(struct dwhdmi_softc *dsc)
193 {
194
195 dwhdmi_phy_enable(dsc);
196 }
197
198 static void
rk_dwhdmi_mode_set(struct dwhdmi_softc * dsc,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)199 rk_dwhdmi_mode_set(struct dwhdmi_softc *dsc,
200 const struct drm_display_mode *mode, const struct drm_display_mode *adjusted_mode)
201 {
202 struct rk_dwhdmi_softc * const sc = to_rk_dwhdmi_softc(dsc);
203 int error;
204
205 if (sc->sc_clk_vpll != NULL) {
206 error = clk_set_rate(sc->sc_clk_vpll, adjusted_mode->clock * 1000);
207 if (error != 0)
208 device_printf(dsc->sc_dev, "couldn't set pixel clock to %u Hz: %d\n",
209 adjusted_mode->clock * 1000, error);
210 }
211
212 dwhdmi_phy_mode_set(dsc, mode, adjusted_mode);
213 }
214
215 static audio_dai_tag_t
rk_dwhdmi_dai_get_tag(device_t dev,const void * data,size_t len)216 rk_dwhdmi_dai_get_tag(device_t dev, const void *data, size_t len)
217 {
218 struct rk_dwhdmi_softc * const sc = device_private(dev);
219
220 if (len != 4)
221 return NULL;
222
223 return &sc->sc_base.sc_dai;
224 }
225
226 static struct fdtbus_dai_controller_func rk_dwhdmi_dai_funcs = {
227 .get_tag = rk_dwhdmi_dai_get_tag
228 };
229
230 static int
rk_dwhdmi_match(device_t parent,cfdata_t cf,void * aux)231 rk_dwhdmi_match(device_t parent, cfdata_t cf, void *aux)
232 {
233 struct fdt_attach_args * const faa = aux;
234
235 return of_compatible_match(faa->faa_phandle, compat_data);
236 }
237
238 static void
rk_dwhdmi_attach(device_t parent,device_t self,void * aux)239 rk_dwhdmi_attach(device_t parent, device_t self, void *aux)
240 {
241 struct rk_dwhdmi_softc * const sc = device_private(self);
242 struct fdt_attach_args * const faa = aux;
243 const int phandle = faa->faa_phandle;
244 bus_addr_t addr;
245 bus_size_t size;
246
247 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
248 aprint_error(": couldn't get registers\n");
249 return;
250 }
251
252 /* Required */
253 if (fdtbus_clock_enable(phandle, "iahb", true) != 0) {
254 aprint_error(": couldn't enable iahb clock\n");
255 return;
256 }
257
258 /* Required */
259 if (fdtbus_clock_enable(phandle, "isfr", true) != 0) {
260 aprint_error(": couldn't enable isfr clock\n");
261 return;
262 }
263
264 /* Optional */
265 sc->sc_clk_vpll = fdtbus_clock_get(phandle, "vpll");
266 if (sc->sc_clk_vpll != NULL && clk_enable(sc->sc_clk_vpll) != 0) {
267 aprint_error(": couldn't enable vpll clock\n");
268 return;
269 }
270
271 /* Optional */
272 if (fdtbus_clock_enable(phandle, "grf", false) != 0) {
273 aprint_error(": couldn't enable grf clock\n");
274 return;
275 }
276
277 /* Optional */
278 if (fdtbus_clock_enable(phandle, "cec", false) != 0) {
279 aprint_error(": couldn't enable cec clock\n");
280 return;
281 }
282
283 sc->sc_base.sc_dev = self;
284 if (of_getprop_uint32(phandle, "reg-io-width", &sc->sc_base.sc_reg_width) != 0)
285 sc->sc_base.sc_reg_width = 4;
286 sc->sc_base.sc_bst = faa->faa_bst;
287 if (bus_space_map(sc->sc_base.sc_bst, addr, size, 0, &sc->sc_base.sc_bsh) != 0) {
288 aprint_error(": couldn't map registers\n");
289 return;
290 }
291 sc->sc_phandle = faa->faa_phandle;
292 sc->sc_grf = fdtbus_syscon_acquire(phandle, "rockchip,grf");
293 if (sc->sc_grf == NULL) {
294 aprint_error(": couldn't get grf syscon\n");
295 return;
296 }
297
298 aprint_naive("\n");
299 aprint_normal(": HDMI TX\n");
300
301 sc->sc_base.sc_ic = fdtbus_i2c_acquire(phandle, "ddc-i2c-bus");
302 if (of_hasprop(phandle, "ddc-i2c-bus") && sc->sc_base.sc_ic == NULL) {
303 aprint_error_dev(self, "couldn't find external I2C master\n");
304 return;
305 }
306
307 sc->sc_base.sc_flags |= DWHDMI_USE_INTERNAL_PHY;
308 sc->sc_base.sc_detect = dwhdmi_phy_detect;
309 sc->sc_base.sc_enable = rk_dwhdmi_enable;
310 sc->sc_base.sc_disable = dwhdmi_phy_disable;
311 sc->sc_base.sc_mode_set = rk_dwhdmi_mode_set;
312 sc->sc_base.sc_mpll_config = rk_dwhdmi_mpll_config;
313 sc->sc_base.sc_phy_config = rk_dwhdmi_phy_config;
314
315 if (dwhdmi_attach(&sc->sc_base) != 0) {
316 aprint_error_dev(self, "failed to attach driver\n");
317 return;
318 }
319
320 sc->sc_ports.dp_ep_activate = rk_dwhdmi_ep_activate;
321 sc->sc_ports.dp_ep_get_data = rk_dwhdmi_ep_get_data;
322 fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_ENCODER);
323
324 fdtbus_register_dai_controller(self, phandle, &rk_dwhdmi_dai_funcs);
325 }
326
327 CFATTACH_DECL_NEW(rk_dwhdmi, sizeof(struct rk_dwhdmi_softc),
328 rk_dwhdmi_match, rk_dwhdmi_attach, NULL, NULL);
329