1 /* $NetBSD: zynq_uart.c,v 1.5 2022/10/27 07:57:46 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2012 Genetec Corporation. All rights reserved.
5 * Written by Hiroyuki Bessho, Hashimoto Kenichi for Genetec Corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30 /*
31 * derived from sys/dev/ic/com.c
32 */
33
34 /*-
35 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc.
36 * All rights reserved.
37 *
38 * This code is derived from software contributed to The NetBSD Foundation
39 * by Charles M. Hannum.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
43 * are met:
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60 * POSSIBILITY OF SUCH DAMAGE.
61 */
62
63 /*
64 * Copyright (c) 1991 The Regents of the University of California.
65 * All rights reserved.
66 *
67 * Redistribution and use in source and binary forms, with or without
68 * modification, are permitted provided that the following conditions
69 * are met:
70 * 1. Redistributions of source code must retain the above copyright
71 * notice, this list of conditions and the following disclaimer.
72 * 2. Redistributions in binary form must reproduce the above copyright
73 * notice, this list of conditions and the following disclaimer in the
74 * documentation and/or other materials provided with the distribution.
75 * 3. Neither the name of the University nor the names of its contributors
76 * may be used to endorse or promote products derived from this software
77 * without specific prior written permission.
78 *
79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
89 * SUCH DAMAGE.
90 *
91 * @(#)com.c 7.5 (Berkeley) 5/16/91
92 */
93
94 /*
95 * driver for UART in Zynq-7000.
96 */
97
98 #include <sys/cdefs.h>
99 __KERNEL_RCSID(0, "$NetBSD: zynq_uart.c,v 1.5 2022/10/27 07:57:46 skrll Exp $");
100
101 #include "opt_soc.h"
102 #include "opt_console.h"
103 #include "opt_com.h"
104 #include "opt_ddb.h"
105 #include "opt_kgdb.h"
106 #include "opt_ntp.h"
107
108 /*
109 * Override cnmagic(9) macro before including <sys/systm.h>.
110 * We need to know if cn_check_magic triggered debugger, so set a flag.
111 * Callers of cn_check_magic must declare int cn_trapped = 0;
112 * XXX: this is *ugly*!
113 */
114 #define cn_trap() \
115 do { \
116 console_debugger(); \
117 cn_trapped = 1; \
118 } while (/* CONSTCOND */ 0)
119
120 #include <sys/param.h>
121
122 #include <sys/bus.h>
123 #include <sys/conf.h>
124 #include <dev/cons.h>
125 #include <sys/device.h>
126 #include <sys/file.h>
127 #include <sys/kauth.h>
128 #include <sys/kernel.h>
129 #include <sys/kmem.h>
130 #include <sys/poll.h>
131 #include <sys/proc.h>
132 #include <sys/systm.h>
133 #include <sys/tty.h>
134
135 #include <ddb/db_active.h>
136
137 #ifdef RND_COM
138 #include <sys/rndsource.h>
139 #endif
140
141 #include <arm/xilinx/zynq_uartreg.h>
142 #include <arm/xilinx/zynq_uartvar.h>
143
144 #ifndef ZYNQUART_RING_SIZE
145 #define ZYNQUART_RING_SIZE 2048
146 #endif
147
148 #define UART_SIZE 0x00000048
149
150 typedef struct zynquart_softc {
151 device_t sc_dev;
152
153 struct zynquart_regs {
154 bus_space_tag_t ur_iot;
155 bus_space_handle_t ur_ioh;
156 bus_addr_t ur_iobase;
157 } sc_regs;
158
159 #define sc_bt sc_regs.ur_iot
160 #define sc_bh sc_regs.ur_ioh
161
162 uint32_t sc_intrspec_enb;
163 uint32_t sc_cr;
164 uint32_t sc_mcr;
165 uint32_t sc_msr;
166
167 uint sc_init_cnt;
168
169 bus_addr_t sc_addr;
170 bus_size_t sc_size;
171
172 u_char sc_hwflags;
173 /* Hardware flag masks */
174 #define ZYNQUART_HW_FLOW __BIT(0)
175 #define ZYNQUART_HW_DEV_OK __BIT(1)
176 #define ZYNQUART_HW_CONSOLE __BIT(2)
177 #define ZYNQUART_HW_KGDB __BIT(3)
178
179 bool enabled;
180
181 u_char sc_swflags;
182
183 u_char sc_rx_flags;
184 #define ZYNQUART_RX_TTY_BLOCKED __BIT(0)
185 #define ZYNQUART_RX_TTY_OVERFLOWED __BIT(1)
186 #define ZYNQUART_RX_IBUF_BLOCKED __BIT(2)
187 #define ZYNQUART_RX_IBUF_OVERFLOWED __BIT(3)
188 #define ZYNQUART_RX_ANY_BLOCK \
189 (ZYNQUART_RX_TTY_BLOCKED|ZYNQUART_RX_TTY_OVERFLOWED| \
190 ZYNQUART_RX_IBUF_BLOCKED|ZYNQUART_RX_IBUF_OVERFLOWED)
191
192 bool sc_tx_busy, sc_tx_done, sc_tx_stopped;
193 bool sc_rx_ready,sc_st_check;
194 u_short sc_txfifo_len, sc_txfifo_thresh;
195
196 uint16_t *sc_rbuf;
197 u_int sc_rbuf_size;
198 u_int sc_rbuf_in;
199 u_int sc_rbuf_out;
200 #define ZYNQUART_RBUF_AVAIL(sc) \
201 ((sc->sc_rbuf_out <= sc->sc_rbuf_in) ? \
202 (sc->sc_rbuf_in - sc->sc_rbuf_out) : \
203 (sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in)))
204
205 #define ZYNQUART_RBUF_SPACE(sc) \
206 ((sc->sc_rbuf_in <= sc->sc_rbuf_out ? \
207 sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in) : \
208 sc->sc_rbuf_in - sc->sc_rbuf_out) - 1)
209 /* increment ringbuffer pointer */
210 #define ZYNQUART_RBUF_INC(sc,v,i) (((v) + (i))&((sc->sc_rbuf_size)-1))
211 u_int sc_r_lowat;
212 u_int sc_r_hiwat;
213
214 /* output chunk */
215 u_char *sc_tba;
216 u_int sc_tbc;
217 u_int sc_heldtbc;
218 /* pending parameter changes */
219 u_char sc_pending;
220 #define ZYNQUART_PEND_PARAM __BIT(0)
221 #define ZYNQUART_PEND_SPEED __BIT(1)
222
223
224 struct callout sc_diag_callout;
225 kmutex_t sc_lock;
226 void *sc_ih; /* interrupt handler */
227 void *sc_si; /* soft interrupt */
228 struct tty *sc_tty;
229
230 /* power management hooks */
231 int (*enable)(struct zynquart_softc *);
232 void (*disable)(struct zynquart_softc *);
233
234 struct {
235 ulong err;
236 ulong brk;
237 ulong prerr;
238 ulong frmerr;
239 ulong ovrrun;
240 } sc_errors;
241
242 struct zynquart_baudrate_ratio {
243 uint16_t numerator; /* UBIR */
244 uint16_t modulator; /* UBMR */
245 } sc_ratio;
246
247 } zynquart_softc_t;
248
249
250 int zynquartspeed(long, struct zynquart_baudrate_ratio *);
251 int zynquartparam(struct tty *, struct termios *);
252 void zynquartstart(struct tty *);
253 int zynquarthwiflow(struct tty *, int);
254
255 void zynquart_shutdown(struct zynquart_softc *);
256 void zynquart_loadchannelregs(struct zynquart_softc *);
257 void zynquart_hwiflow(struct zynquart_softc *);
258 void zynquart_break(struct zynquart_softc *, bool);
259 void zynquart_modem(struct zynquart_softc *, int);
260 void tiocm_to_zynquart(struct zynquart_softc *, u_long, int);
261 int zynquart_to_tiocm(struct zynquart_softc *);
262 void zynquart_iflush(struct zynquart_softc *);
263
264 int zynquart_common_getc(dev_t, struct zynquart_regs *);
265 void zynquart_common_putc(dev_t, struct zynquart_regs *, int);
266
267
268 int zynquart_init(struct zynquart_regs *, int, tcflag_t);
269
270 int zynquartcngetc(dev_t);
271 void zynquartcnputc(dev_t, int);
272
273 static void zynquartintr_read(struct zynquart_softc *);
274 static void zynquartintr_send(struct zynquart_softc *);
275
276 static void zynquart_enable_debugport(struct zynquart_softc *);
277 static void zynquart_disable_all_interrupts(struct zynquart_softc *);
278 static void zynquart_control_rxint(struct zynquart_softc *, bool);
279 static void zynquart_control_txint(struct zynquart_softc *, bool);
280
281 static uint32_t cflag_to_zynquart(tcflag_t, uint32_t);
282
283 #define integrate static inline
284 void zynquartsoft(void *);
285 integrate void zynquart_rxsoft(struct zynquart_softc *, struct tty *);
286 integrate void zynquart_txsoft(struct zynquart_softc *, struct tty *);
287 integrate void zynquart_stsoft(struct zynquart_softc *, struct tty *);
288 integrate void zynquart_schedrx(struct zynquart_softc *);
289 void zynquartdiag(void *);
290 static void zynquart_load_speed(struct zynquart_softc *);
291 static void zynquart_load_params(struct zynquart_softc *);
292 integrate void zynquart_load_pendings(struct zynquart_softc *);
293
294
295 extern struct cfdriver zynquart_cd;
296
297 dev_type_open(zynquartopen);
298 dev_type_close(zynquartclose);
299 dev_type_read(zynquartread);
300 dev_type_write(zynquartwrite);
301 dev_type_ioctl(zynquartioctl);
302 dev_type_stop(zynquartstop);
303 dev_type_tty(zynquarttty);
304 dev_type_poll(zynquartpoll);
305
306 const struct cdevsw zynquart_cdevsw = {
307 .d_open = zynquartopen,
308 .d_close = zynquartclose,
309 .d_read = zynquartread,
310 .d_write = zynquartwrite,
311 .d_ioctl = zynquartioctl,
312 .d_stop = zynquartstop,
313 .d_tty = zynquarttty,
314 .d_poll = zynquartpoll,
315 .d_mmap = nommap,
316 .d_kqfilter = ttykqfilter,
317 .d_discard = nodiscard,
318 .d_flag = D_TTY
319 };
320
321 /*
322 * Make this an option variable one can patch.
323 * But be warned: this must be a power of 2!
324 */
325 u_int zynquart_rbuf_size = ZYNQUART_RING_SIZE;
326
327 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */
328 u_int zynquart_rbuf_hiwat = (ZYNQUART_RING_SIZE * 1) / 4;
329 u_int zynquart_rbuf_lowat = (ZYNQUART_RING_SIZE * 3) / 4;
330
331 static struct zynquart_regs zynquartconsregs;
332 static int zynquartconsattached;
333 static int zynquartconsrate;
334 static tcflag_t zynquartconscflag;
335 static struct cnm_state zynquart_cnm_state;
336
337 u_int zynquart_freq;
338 u_int zynquart_freqdiv;
339
340 #ifdef KGDB
341 #include <sys/kgdb.h>
342
343 static struct zynquart_regs zynquart_kgdb_regs;
344 static int zynquart_kgdb_attached;
345
346 int zynquart_kgdb_getc(void *);
347 void zynquart_kgdb_putc(void *, int);
348 #endif /* KGDB */
349
350 #define ZYNQUART_UNIT_MASK 0x7ffff
351 #define ZYNQUART_DIALOUT_MASK 0x80000
352
353 #define ZYNQUART_UNIT(x) (minor(x) & ZYNQUART_UNIT_MASK)
354 #define ZYNQUART_DIALOUT(x) (minor(x) & ZYNQUART_DIALOUT_MASK)
355
356 #define ZYNQUART_ISALIVE(sc) ((sc)->enabled != 0 && \
357 device_is_active((sc)->sc_dev))
358
359 #define BR BUS_SPACE_BARRIER_READ
360 #define BW BUS_SPACE_BARRIER_WRITE
361 #define ZYNQUART_BARRIER(r, f) \
362 bus_space_barrier((r)->ur_iot, (r)->ur_ioh, 0, UART_SIZE, (f))
363
364 CFATTACH_DECL_NEW(zynquart, sizeof(struct zynquart_softc),
365 zynquart_match, zynquart_attach, NULL, NULL);
366
367 void
zynquart_attach_common(device_t parent,device_t self,bus_space_tag_t iot,paddr_t iobase,size_t size,int flags)368 zynquart_attach_common(device_t parent, device_t self,
369 bus_space_tag_t iot, paddr_t iobase, size_t size, int flags)
370 {
371 zynquart_softc_t *sc = device_private(self);
372 struct zynquart_regs *regsp = &sc->sc_regs;
373 struct tty *tp;
374 bus_space_handle_t ioh;
375
376 aprint_naive("\n");
377 aprint_normal("\n");
378
379 sc->sc_dev = self;
380
381 if (size <= 0)
382 size = UART_SIZE;
383
384 regsp->ur_iot = iot;
385 regsp->ur_iobase = iobase;
386
387 if (bus_space_map(iot, regsp->ur_iobase, size, 0, &ioh)) {
388 return;
389 }
390 regsp->ur_ioh = ioh;
391
392 callout_init(&sc->sc_diag_callout, 0);
393 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
394
395 sc->sc_cr = bus_space_read_4(iot, ioh, UART_CONTROL);
396 sc->sc_cr |= CR_TXEN | CR_RXEN;
397 sc->sc_cr &= ~(CR_TXDIS | CR_RXDIS);
398 bus_space_write_4(iot, ioh, UART_CONTROL, sc->sc_cr);
399
400 /* Disable interrupts before configuring the device. */
401 zynquart_disable_all_interrupts(sc);
402
403 if (regsp->ur_iobase == zynquartconsregs.ur_iobase) {
404 zynquartconsattached = 1;
405
406 /* Make sure the console is always "hardwired". */
407 SET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE);
408 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
409 }
410
411 tp = tty_alloc();
412 tp->t_oproc = zynquartstart;
413 tp->t_param = zynquartparam;
414 tp->t_hwiflow = zynquarthwiflow;
415
416 sc->sc_tty = tp;
417 sc->sc_rbuf = kmem_alloc(sizeof (*sc->sc_rbuf) * zynquart_rbuf_size,
418 KM_SLEEP);
419 sc->sc_rbuf_size = zynquart_rbuf_size;
420 sc->sc_rbuf_in = sc->sc_rbuf_out = 0;
421 sc->sc_txfifo_len = 64;
422 sc->sc_txfifo_thresh = 32;
423
424 tty_attach(tp);
425
426 if (ISSET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE)) {
427 int maj;
428
429 /* locate the major number */
430 maj = cdevsw_lookup_major(&zynquart_cdevsw);
431
432 if (maj != NODEVMAJOR) {
433 tp->t_dev = cn_tab->cn_dev = makedev(maj,
434 device_unit(sc->sc_dev));
435
436 aprint_normal_dev(sc->sc_dev, "console\n");
437 }
438 }
439
440 /* reset receive time out */
441 bus_space_write_4(iot, ioh, UART_RCVR_TIMEOUT, 0);
442 bus_space_write_4(iot, ioh, UART_RCVR_FIFO_TRIGGER, 1);
443
444 #ifdef KGDB
445 /*
446 * Allow kgdb to "take over" this port. If this is
447 * not the console and is the kgdb device, it has
448 * exclusive use. If it's the console _and_ the
449 * kgdb device, it doesn't.
450 */
451 if (regsp->ur_iobase == zynquart_kgdb_regs.ur_iobase) {
452 if (!ISSET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE)) {
453 zynquart_kgdb_attached = 1;
454
455 SET(sc->sc_hwflags, ZYNQUART_HW_KGDB);
456 }
457 aprint_normal_dev(sc->sc_dev, "kgdb\n");
458 }
459 #endif
460
461 sc->sc_si = softint_establish(SOFTINT_SERIAL, zynquartsoft, sc);
462
463 #ifdef RND_COM
464 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
465 RND_TYPE_TTY, 0);
466 #endif
467
468 /* if there are no enable/disable functions, assume the device
469 is always enabled */
470 if (!sc->enable)
471 sc->enabled = 1;
472
473 zynquart_enable_debugport(sc);
474
475 SET(sc->sc_hwflags, ZYNQUART_HW_DEV_OK);
476 }
477
478 int
zynquartspeed(long speed,struct zynquart_baudrate_ratio * ratio)479 zynquartspeed(long speed, struct zynquart_baudrate_ratio *ratio)
480 {
481 return 0;
482 }
483
484 #ifdef ZYNQUART_DEBUG
485 int zynquart_debug = 0;
486
487 void zynquartstatus(struct zynquart_softc *, const char *);
488 void
zynquartstatus(struct zynquart_softc * sc,const char * str)489 zynquartstatus(struct zynquart_softc *sc, const char *str)
490 {
491 struct tty *tp = sc->sc_tty;
492
493 aprint_normal_dev(sc->sc_dev,
494 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n",
495 str,
496 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-',
497 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-',
498 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-',
499 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-',
500 sc->sc_tx_stopped ? '+' : '-');
501
502 aprint_normal_dev(sc->sc_dev,
503 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n",
504 str,
505 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-',
506 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-',
507 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-',
508 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-',
509 sc->sc_rx_flags);
510 }
511 #endif
512
513 #if 0
514 int
515 zynquart_detach(device_t self, int flags)
516 {
517 struct zynquart_softc *sc = device_private(self);
518 int maj, mn;
519
520 if (ISSET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE))
521 return EBUSY;
522
523 /* locate the major number */
524 maj = cdevsw_lookup_major(&zynquart_cdevsw);
525
526 /* Nuke the vnodes for any open instances. */
527 mn = device_unit(self);
528 vdevgone(maj, mn, mn, VCHR);
529
530 mn |= ZYNQUART_DIALOUT_MASK;
531 vdevgone(maj, mn, mn, VCHR);
532
533 if (sc->sc_rbuf == NULL) {
534 /*
535 * Ring buffer allocation failed in the zynquart_attach_subr,
536 * only the tty is allocated, and nothing else.
537 */
538 tty_free(sc->sc_tty);
539 return 0;
540 }
541
542 /* Free the receive buffer. */
543 kmem_free(sc->sc_rbuf, sizeof(*sc->sc_rbuf) * sc->sc_rbuf_size);
544
545 /* Detach and free the tty. */
546 tty_detach(sc->sc_tty);
547 tty_free(sc->sc_tty);
548
549 /* Unhook the soft interrupt handler. */
550 softint_disestablish(sc->sc_si);
551
552 #ifdef RND_COM
553 /* Unhook the entropy source. */
554 rnd_detach_source(&sc->rnd_source);
555 #endif
556 callout_destroy(&sc->sc_diag_callout);
557
558 /* Destroy the lock. */
559 mutex_destroy(&sc->sc_lock);
560
561 return (0);
562 }
563 #endif
564
565 #ifdef notyet
566 int
zynquart_activate(device_t self,enum devact act)567 zynquart_activate(device_t self, enum devact act)
568 {
569 struct zynquart_softc *sc = device_private(self);
570 int rv = 0;
571
572 switch (act) {
573 case DVACT_ACTIVATE:
574 rv = EOPNOTSUPP;
575 break;
576
577 case DVACT_DEACTIVATE:
578 if (sc->sc_hwflags & (ZYNQUART_HW_CONSOLE|ZYNQUART_HW_KGDB)) {
579 rv = EBUSY;
580 break;
581 }
582
583 if (sc->disable != NULL && sc->enabled != 0) {
584 (*sc->disable)(sc);
585 sc->enabled = 0;
586 }
587 break;
588 }
589
590 return (rv);
591 }
592 #endif
593
594 void
zynquart_shutdown(struct zynquart_softc * sc)595 zynquart_shutdown(struct zynquart_softc *sc)
596 {
597 struct tty *tp = sc->sc_tty;
598
599 mutex_spin_enter(&sc->sc_lock);
600
601 /* If we were asserting flow control, then deassert it. */
602 SET(sc->sc_rx_flags, ZYNQUART_RX_IBUF_BLOCKED);
603 zynquart_hwiflow(sc);
604
605 /* Clear any break condition set with TIOCSBRK. */
606 zynquart_break(sc, false);
607
608 /*
609 * Hang up if necessary. Wait a bit, so the other side has time to
610 * notice even if we immediately open the port again.
611 * Avoid tsleeping above splhigh().
612 */
613 if (ISSET(tp->t_cflag, HUPCL)) {
614 zynquart_modem(sc, 0);
615 mutex_spin_exit(&sc->sc_lock);
616 /* XXX will only timeout */
617 (void) kpause(ttclos, false, hz, NULL);
618 mutex_spin_enter(&sc->sc_lock);
619 }
620
621 /* Turn off interrupts. */
622 zynquart_disable_all_interrupts(sc);
623 /* re-enable recv interrupt for console or kgdb port */
624 zynquart_enable_debugport(sc);
625
626 mutex_spin_exit(&sc->sc_lock);
627
628 #ifdef notyet
629 if (sc->disable) {
630 #ifdef DIAGNOSTIC
631 if (!sc->enabled)
632 panic("zynquart_shutdown: not enabled?");
633 #endif
634 (*sc->disable)(sc);
635 sc->enabled = 0;
636 }
637 #endif
638 }
639
640 int
zynquartopen(dev_t dev,int flag,int mode,struct lwp * l)641 zynquartopen(dev_t dev, int flag, int mode, struct lwp *l)
642 {
643 struct zynquart_softc *sc;
644 struct tty *tp;
645 int s;
646 int error;
647
648 sc = device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev));
649 if (sc == NULL || !ISSET(sc->sc_hwflags, ZYNQUART_HW_DEV_OK) ||
650 sc->sc_rbuf == NULL)
651 return (ENXIO);
652
653 if (!device_is_active(sc->sc_dev))
654 return (ENXIO);
655
656 #ifdef KGDB
657 /*
658 * If this is the kgdb port, no other use is permitted.
659 */
660 if (ISSET(sc->sc_hwflags, ZYNQUART_HW_KGDB))
661 return (EBUSY);
662 #endif
663
664 tp = sc->sc_tty;
665
666 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
667 return (EBUSY);
668
669 s = spltty();
670
671 /*
672 * Do the following iff this is a first open.
673 */
674 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
675 struct termios t;
676
677 tp->t_dev = dev;
678
679
680 #ifdef notyet
681 if (sc->enable) {
682 if ((*sc->enable)(sc)) {
683 splx(s);
684 aprint_error_dev(sc->sc_dev,
685 "device enable failed\n");
686 return (EIO);
687 }
688 sc->enabled = 1;
689 }
690 #endif
691
692 mutex_spin_enter(&sc->sc_lock);
693
694 zynquart_disable_all_interrupts(sc);
695
696 /* Fetch the current modem control status, needed later. */
697
698 #ifdef ZYNQUART_PPS
699 /* Clear PPS capture state on first open. */
700 mutex_spin_enter(&timecounter_lock);
701 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state));
702 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
703 pps_init(&sc->sc_pps_state);
704 mutex_spin_exit(&timecounter_lock);
705 #endif
706
707 mutex_spin_exit(&sc->sc_lock);
708
709 /*
710 * Initialize the termios status to the defaults. Add in the
711 * sticky bits from TIOCSFLAGS.
712 */
713 if (ISSET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE)) {
714 t.c_ospeed = zynquartconsrate;
715 t.c_cflag = zynquartconscflag;
716 } else {
717 t.c_ospeed = TTYDEF_SPEED;
718 t.c_cflag = TTYDEF_CFLAG;
719 }
720 t.c_ispeed = t.c_ospeed;
721 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
722 SET(t.c_cflag, CLOCAL);
723 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
724 SET(t.c_cflag, CRTSCTS);
725 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF))
726 SET(t.c_cflag, MDMBUF);
727 /* Make sure zynquartparam() will do something. */
728 tp->t_ospeed = 0;
729 (void) zynquartparam(tp, &t);
730 tp->t_iflag = TTYDEF_IFLAG;
731 tp->t_oflag = TTYDEF_OFLAG;
732 tp->t_lflag = TTYDEF_LFLAG;
733 ttychars(tp);
734 ttsetwater(tp);
735
736 mutex_spin_enter(&sc->sc_lock);
737
738 /*
739 * Turn on DTR. We must always do this, even if carrier is not
740 * present, because otherwise we'd have to use TIOCSDTR
741 * immediately after setting CLOCAL, which applications do not
742 * expect. We always assert DTR while the device is open
743 * unless explicitly requested to deassert it.
744 */
745 zynquart_modem(sc, 1);
746
747 /* Clear the input ring, and unblock. */
748 sc->sc_rbuf_in = sc->sc_rbuf_out = 0;
749 zynquart_iflush(sc);
750 CLR(sc->sc_rx_flags, ZYNQUART_RX_ANY_BLOCK);
751 zynquart_hwiflow(sc);
752
753 /* Turn on interrupts. */
754 zynquart_control_rxint(sc, true);
755
756 #ifdef ZYNQUART_DEBUG
757 if (zynquart_debug)
758 zynquartstatus(sc, "zynquartopen ");
759 #endif
760
761 mutex_spin_exit(&sc->sc_lock);
762 }
763
764 splx(s);
765
766 #if 0
767 error = ttyopen(tp, ZYNQUART_DIALOUT(dev), ISSET(flag, O_NONBLOCK));
768 #else
769 error = ttyopen(tp, 1, ISSET(flag, O_NONBLOCK));
770 #endif
771 if (error)
772 goto bad;
773
774 error = (*tp->t_linesw->l_open)(dev, tp);
775 if (error)
776 goto bad;
777
778 return (0);
779
780 bad:
781 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
782 /*
783 * We failed to open the device, and nobody else had it opened.
784 * Clean up the state as appropriate.
785 */
786 zynquart_shutdown(sc);
787 }
788
789 return (error);
790 }
791
792 int
zynquartclose(dev_t dev,int flag,int mode,struct lwp * l)793 zynquartclose(dev_t dev, int flag, int mode, struct lwp *l)
794 {
795 struct zynquart_softc *sc =
796 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev));
797 struct tty *tp = sc->sc_tty;
798
799 /* XXX This is for cons.c. */
800 if (!ISSET(tp->t_state, TS_ISOPEN))
801 return (0);
802
803 (*tp->t_linesw->l_close)(tp, flag);
804 ttyclose(tp);
805
806 if (ZYNQUART_ISALIVE(sc) == 0)
807 return (0);
808
809 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
810 /*
811 * Although we got a last close, the device may still be in
812 * use; e.g. if this was the dialout node, and there are still
813 * processes waiting for carrier on the non-dialout node.
814 */
815 zynquart_shutdown(sc);
816 }
817
818 return (0);
819 }
820
821 int
zynquartread(dev_t dev,struct uio * uio,int flag)822 zynquartread(dev_t dev, struct uio *uio, int flag)
823 {
824 struct zynquart_softc *sc =
825 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev));
826 struct tty *tp = sc->sc_tty;
827
828 if (ZYNQUART_ISALIVE(sc) == 0)
829 return (EIO);
830
831 return ((*tp->t_linesw->l_read)(tp, uio, flag));
832 }
833
834 int
zynquartwrite(dev_t dev,struct uio * uio,int flag)835 zynquartwrite(dev_t dev, struct uio *uio, int flag)
836 {
837 struct zynquart_softc *sc =
838 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev));
839 struct tty *tp = sc->sc_tty;
840
841 if (ZYNQUART_ISALIVE(sc) == 0)
842 return (EIO);
843
844 return ((*tp->t_linesw->l_write)(tp, uio, flag));
845 }
846
847 int
zynquartpoll(dev_t dev,int events,struct lwp * l)848 zynquartpoll(dev_t dev, int events, struct lwp *l)
849 {
850 struct zynquart_softc *sc =
851 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev));
852 struct tty *tp = sc->sc_tty;
853
854 if (ZYNQUART_ISALIVE(sc) == 0)
855 return (POLLHUP);
856
857 return ((*tp->t_linesw->l_poll)(tp, events, l));
858 }
859
860 struct tty *
zynquarttty(dev_t dev)861 zynquarttty(dev_t dev)
862 {
863 struct zynquart_softc *sc =
864 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev));
865 struct tty *tp = sc->sc_tty;
866
867 return (tp);
868 }
869
870 int
zynquartioctl(dev_t dev,u_long cmd,void * data,int flag,struct lwp * l)871 zynquartioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
872 {
873 struct zynquart_softc *sc;
874 struct tty *tp;
875 int error;
876
877 sc = device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(dev));
878 if (sc == NULL)
879 return ENXIO;
880 if (ZYNQUART_ISALIVE(sc) == 0)
881 return (EIO);
882
883 tp = sc->sc_tty;
884
885 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l);
886 if (error != EPASSTHROUGH)
887 return (error);
888
889 error = ttioctl(tp, cmd, data, flag, l);
890 if (error != EPASSTHROUGH)
891 return (error);
892
893 error = 0;
894 switch (cmd) {
895 case TIOCSFLAGS:
896 error = kauth_authorize_device_tty(l->l_cred,
897 KAUTH_DEVICE_TTY_PRIVSET, tp);
898 break;
899 default:
900 /* nothing */
901 break;
902 }
903 if (error) {
904 return error;
905 }
906
907 mutex_spin_enter(&sc->sc_lock);
908
909 switch (cmd) {
910 case TIOCSBRK:
911 zynquart_break(sc, true);
912 break;
913
914 case TIOCCBRK:
915 zynquart_break(sc, false);
916 break;
917
918 case TIOCSDTR:
919 zynquart_modem(sc, 1);
920 break;
921
922 case TIOCCDTR:
923 zynquart_modem(sc, 0);
924 break;
925
926 case TIOCGFLAGS:
927 *(int *)data = sc->sc_swflags;
928 break;
929
930 case TIOCSFLAGS:
931 sc->sc_swflags = *(int *)data;
932 break;
933
934 case TIOCMSET:
935 case TIOCMBIS:
936 case TIOCMBIC:
937 tiocm_to_zynquart(sc, cmd, *(int *)data);
938 break;
939
940 case TIOCMGET:
941 *(int *)data = zynquart_to_tiocm(sc);
942 break;
943
944 #ifdef notyet
945 case PPS_IOC_CREATE:
946 case PPS_IOC_DESTROY:
947 case PPS_IOC_GETPARAMS:
948 case PPS_IOC_SETPARAMS:
949 case PPS_IOC_GETCAP:
950 case PPS_IOC_FETCH:
951 #ifdef PPS_SYNC
952 case PPS_IOC_KCBIND:
953 #endif
954 mutex_spin_enter(&timecounter_lock);
955 error = pps_ioctl(cmd, data, &sc->sc_pps_state);
956 mutex_spin_exit(&timecounter_lock);
957 break;
958
959 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */
960 mutex_spin_enter(&timecounter_lock);
961 #ifndef PPS_TRAILING_EDGE
962 TIMESPEC_TO_TIMEVAL((struct timeval *)data,
963 &sc->sc_pps_state.ppsinfo.assert_timestamp);
964 #else
965 TIMESPEC_TO_TIMEVAL((struct timeval *)data,
966 &sc->sc_pps_state.ppsinfo.clear_timestamp);
967 #endif
968 mutex_spin_exit(&timecounter_lock);
969 break;
970 #endif
971
972 default:
973 error = EPASSTHROUGH;
974 break;
975 }
976
977 mutex_spin_exit(&sc->sc_lock);
978
979 #ifdef ZYNQUART_DEBUG
980 if (zynquart_debug)
981 zynquartstatus(sc, "zynquartioctl ");
982 #endif
983
984 return (error);
985 }
986
987 integrate void
zynquart_schedrx(struct zynquart_softc * sc)988 zynquart_schedrx(struct zynquart_softc *sc)
989 {
990 sc->sc_rx_ready = 1;
991
992 /* Wake up the poller. */
993 softint_schedule(sc->sc_si);
994 }
995
996 void
zynquart_break(struct zynquart_softc * sc,bool onoff)997 zynquart_break(struct zynquart_softc *sc, bool onoff)
998 {
999 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1000 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1001
1002 if (onoff)
1003 SET(sc->sc_cr, CR_STPBRK);
1004 else
1005 CLR(sc->sc_cr, CR_STPBRK);
1006
1007 bus_space_write_4(iot, ioh, UART_CONTROL, sc->sc_cr);
1008 }
1009
1010 void
zynquart_modem(struct zynquart_softc * sc,int onoff)1011 zynquart_modem(struct zynquart_softc *sc, int onoff)
1012 {
1013 #ifdef notyet
1014 if (sc->sc_mcr_dtr == 0)
1015 return;
1016
1017 if (onoff)
1018 SET(sc->sc_mcr, sc->sc_mcr_dtr);
1019 else
1020 CLR(sc->sc_mcr, sc->sc_mcr_dtr);
1021
1022 if (!sc->sc_heldchange) {
1023 if (sc->sc_tx_busy) {
1024 sc->sc_heldtbc = sc->sc_tbc;
1025 sc->sc_tbc = 0;
1026 sc->sc_heldchange = 1;
1027 } else
1028 zynquart_loadchannelregs(sc);
1029 }
1030 #endif
1031 }
1032
1033 void
tiocm_to_zynquart(struct zynquart_softc * sc,u_long how,int ttybits)1034 tiocm_to_zynquart(struct zynquart_softc *sc, u_long how, int ttybits)
1035 {
1036 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1037 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1038
1039 u_char combits;
1040
1041 combits = 0;
1042 if (ISSET(ttybits, TIOCM_DTR))
1043 SET(combits, MODEMCR_DTR);
1044 if (ISSET(ttybits, TIOCM_RTS))
1045 SET(combits, MODEMCR_RTS);
1046
1047 switch (how) {
1048 case TIOCMBIC:
1049 CLR(sc->sc_mcr, combits);
1050 break;
1051
1052 case TIOCMBIS:
1053 SET(sc->sc_mcr, combits);
1054 break;
1055
1056 case TIOCMSET:
1057 CLR(sc->sc_mcr, MODEMCR_DTR | MODEMCR_RTS);
1058 SET(sc->sc_mcr, combits);
1059 break;
1060 }
1061
1062 bus_space_write_4(iot, ioh, UART_MODEM_CTRL, sc->sc_mcr);
1063 }
1064
1065 int
zynquart_to_tiocm(struct zynquart_softc * sc)1066 zynquart_to_tiocm(struct zynquart_softc *sc)
1067 {
1068 #ifdef notyet
1069 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1070 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1071 #endif
1072 uint32_t combits;
1073 int ttybits = 0;
1074
1075 combits = sc->sc_mcr;
1076 if (ISSET(combits, MODEMCR_DTR))
1077 SET(ttybits, TIOCM_DTR);
1078 if (ISSET(combits, MODEMCR_RTS))
1079 SET(ttybits, TIOCM_RTS);
1080
1081 combits = sc->sc_msr;
1082 if (ISSET(combits, MODEMSR_DCD))
1083 SET(ttybits, TIOCM_CD);
1084 if (ISSET(combits, MODEMSR_CTS))
1085 SET(ttybits, TIOCM_CTS);
1086 if (ISSET(combits, MODEMSR_DSR))
1087 SET(ttybits, TIOCM_DSR);
1088 if (ISSET(combits, MODEMSR_RI | MODEMSR_TERI))
1089 SET(ttybits, TIOCM_RI);
1090
1091 #ifdef notyet
1092 combits = bus_space_read_4(iot, ioh, UART_INTRPT_MASK);
1093 if (ISSET(sc->sc_imr, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC))
1094 SET(ttybits, TIOCM_LE);
1095 #endif
1096
1097 return (ttybits);
1098 }
1099
1100 static uint32_t
cflag_to_zynquart(tcflag_t cflag,uint32_t oldval)1101 cflag_to_zynquart(tcflag_t cflag, uint32_t oldval)
1102 {
1103 uint32_t val = oldval;
1104
1105 CLR(val, MR_CHMODE | MR_NBSTOP | MR_PAR | MR_CHRL | MR_CLKS);
1106
1107 switch (cflag & CSIZE) {
1108 case CS5:
1109 /* not suppreted. use 7-bits */
1110 case CS6:
1111 SET(val, CHRL_6BIT);
1112 break;
1113 case CS7:
1114 SET(val, CHRL_7BIT);
1115 break;
1116 case CS8:
1117 SET(val, CHRL_8BIT);
1118 break;
1119 }
1120
1121 if (ISSET(cflag, PARENB)) {
1122 /* odd parity */
1123 if (!ISSET(cflag, PARODD))
1124 SET(val, PAR_ODD);
1125 else
1126 SET(val, PAR_EVEN);
1127 } else {
1128 SET(val, PAR_NONE);
1129 }
1130
1131 if (ISSET(cflag, CSTOPB))
1132 SET(val, NBSTOP_2);
1133
1134 return val;
1135 }
1136
1137 int
zynquartparam(struct tty * tp,struct termios * t)1138 zynquartparam(struct tty *tp, struct termios *t)
1139 {
1140 struct zynquart_softc *sc =
1141 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(tp->t_dev));
1142 struct zynquart_baudrate_ratio ratio;
1143 uint32_t mcr;
1144 bool change_speed = tp->t_ospeed != t->c_ospeed;
1145
1146 if (ZYNQUART_ISALIVE(sc) == 0)
1147 return (EIO);
1148
1149 /* Check requested parameters. */
1150 if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
1151 return (EINVAL);
1152
1153 /*
1154 * For the console, always force CLOCAL and !HUPCL, so that the port
1155 * is always active.
1156 */
1157 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
1158 ISSET(sc->sc_hwflags, ZYNQUART_HW_CONSOLE)) {
1159 SET(t->c_cflag, CLOCAL);
1160 CLR(t->c_cflag, HUPCL);
1161 }
1162
1163 /*
1164 * If there were no changes, don't do anything. This avoids dropping
1165 * input and improves performance when all we did was frob things like
1166 * VMIN and VTIME.
1167 */
1168 if ( !change_speed && tp->t_cflag == t->c_cflag)
1169 return (0);
1170
1171 if (change_speed) {
1172 /* calculate baudrate modulator value */
1173 if (zynquartspeed(t->c_ospeed, &ratio) < 0)
1174 return (EINVAL);
1175 sc->sc_ratio = ratio;
1176 }
1177
1178 mcr = cflag_to_zynquart(t->c_cflag, sc->sc_mcr);
1179
1180 mutex_spin_enter(&sc->sc_lock);
1181
1182 #if 0
1183 /* flow control stuff. not yet */
1184 /*
1185 * If we're not in a mode that assumes a connection is present, then
1186 * ignore carrier changes.
1187 */
1188 if (ISSET(t->c_cflag, CLOCAL | MDMBUF))
1189 sc->sc_msr_dcd = 0;
1190 else
1191 sc->sc_msr_dcd = MSR_DCD;
1192 /*
1193 * Set the flow control pins depending on the current flow control
1194 * mode.
1195 */
1196 if (ISSET(t->c_cflag, CRTSCTS)) {
1197 sc->sc_mcr_dtr = MCR_DTR;
1198 sc->sc_mcr_rts = MCR_RTS;
1199 sc->sc_msr_cts = MSR_CTS;
1200 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS;
1201 } else if (ISSET(t->c_cflag, MDMBUF)) {
1202 /*
1203 * For DTR/DCD flow control, make sure we don't toggle DTR for
1204 * carrier detection.
1205 */
1206 sc->sc_mcr_dtr = 0;
1207 sc->sc_mcr_rts = MCR_DTR;
1208 sc->sc_msr_cts = MSR_DCD;
1209 sc->sc_efr = 0;
1210 } else {
1211 /*
1212 * If no flow control, then always set RTS. This will make
1213 * the other side happy if it mistakenly thinks we're doing
1214 * RTS/CTS flow control.
1215 */
1216 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS;
1217 sc->sc_mcr_rts = 0;
1218 sc->sc_msr_cts = 0;
1219 sc->sc_efr = 0;
1220 if (ISSET(sc->sc_mcr, MCR_DTR))
1221 SET(sc->sc_mcr, MCR_RTS);
1222 else
1223 CLR(sc->sc_mcr, MCR_RTS);
1224 }
1225 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd;
1226 #endif
1227
1228 /* And copy to tty. */
1229 tp->t_ispeed = t->c_ospeed;
1230 tp->t_ospeed = t->c_ospeed;
1231 tp->t_cflag = t->c_cflag;
1232
1233 if (!change_speed && mcr == sc->sc_mcr) {
1234 /* noop */
1235 } else if (!sc->sc_pending && !sc->sc_tx_busy) {
1236 if (mcr != sc->sc_mcr) {
1237 sc->sc_mcr = mcr;
1238 zynquart_load_params(sc);
1239 }
1240 if (change_speed)
1241 zynquart_load_speed(sc);
1242 } else {
1243 if (!sc->sc_pending) {
1244 sc->sc_heldtbc = sc->sc_tbc;
1245 sc->sc_tbc = 0;
1246 }
1247 sc->sc_pending |=
1248 (mcr == sc->sc_mcr ? 0 : ZYNQUART_PEND_PARAM) |
1249 (change_speed ? 0 : ZYNQUART_PEND_SPEED);
1250 sc->sc_mcr = mcr;
1251 }
1252
1253 if (!ISSET(t->c_cflag, CHWFLOW)) {
1254 /* Disable the high water mark. */
1255 sc->sc_r_hiwat = 0;
1256 sc->sc_r_lowat = 0;
1257 if (ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED)) {
1258 CLR(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED);
1259 zynquart_schedrx(sc);
1260 }
1261 if (ISSET(sc->sc_rx_flags,
1262 ZYNQUART_RX_TTY_BLOCKED|ZYNQUART_RX_IBUF_BLOCKED)) {
1263 CLR(sc->sc_rx_flags,
1264 ZYNQUART_RX_TTY_BLOCKED|ZYNQUART_RX_IBUF_BLOCKED);
1265 zynquart_hwiflow(sc);
1266 }
1267 } else {
1268 sc->sc_r_hiwat = zynquart_rbuf_hiwat;
1269 sc->sc_r_lowat = zynquart_rbuf_lowat;
1270 }
1271
1272 mutex_spin_exit(&sc->sc_lock);
1273
1274 /*
1275 * Update the tty layer's idea of the carrier bit, in case we changed
1276 * CLOCAL or MDMBUF. We don't hang up here; we only do that by
1277 * explicit request.
1278 */
1279 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MODEMSR_DCD));
1280
1281 #ifdef ZYNQUART_DEBUG
1282 if (zynquart_debug)
1283 zynquartstatus(sc, "zynquartparam ");
1284 #endif
1285
1286 if (!ISSET(t->c_cflag, CHWFLOW)) {
1287 if (sc->sc_tx_stopped) {
1288 sc->sc_tx_stopped = 0;
1289 zynquartstart(tp);
1290 }
1291 }
1292
1293 return (0);
1294 }
1295
1296 void
zynquart_iflush(struct zynquart_softc * sc)1297 zynquart_iflush(struct zynquart_softc *sc)
1298 {
1299 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1300 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1301 #ifdef DIAGNOSTIC
1302 uint32_t reg = 0xffff;
1303 #endif
1304 int timo;
1305
1306 timo = 50000;
1307 /* flush any pending I/O */
1308 while (!ISSET(bus_space_read_4(iot, ioh, UART_CHANNEL_STS), STS_REMPTY) &&
1309 --timo)
1310 #ifdef DIAGNOSTIC
1311 reg =
1312 #else
1313 (void)
1314 #endif
1315 bus_space_read_4(iot, ioh, UART_TX_RX_FIFO);
1316
1317 #ifdef DIAGNOSTIC
1318 if (!timo)
1319 aprint_error_dev(sc->sc_dev, "zynquart_iflush timeout %02x\n", reg);
1320 #endif
1321 }
1322
1323 int
zynquarthwiflow(struct tty * tp,int block)1324 zynquarthwiflow(struct tty *tp, int block)
1325 {
1326 struct zynquart_softc *sc =
1327 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(tp->t_dev));
1328
1329 if (ZYNQUART_ISALIVE(sc) == 0)
1330 return (0);
1331
1332 #ifdef notyet
1333 if (sc->sc_mcr_rts == 0)
1334 return (0);
1335 #endif
1336
1337 mutex_spin_enter(&sc->sc_lock);
1338
1339 if (block) {
1340 if (!ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_BLOCKED)) {
1341 SET(sc->sc_rx_flags, ZYNQUART_RX_TTY_BLOCKED);
1342 zynquart_hwiflow(sc);
1343 }
1344 } else {
1345 if (ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED)) {
1346 CLR(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED);
1347 zynquart_schedrx(sc);
1348 }
1349 if (ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_BLOCKED)) {
1350 CLR(sc->sc_rx_flags, ZYNQUART_RX_TTY_BLOCKED);
1351 zynquart_hwiflow(sc);
1352 }
1353 }
1354
1355 mutex_spin_exit(&sc->sc_lock);
1356 return (1);
1357 }
1358
1359 /*
1360 * (un)block input via hw flowcontrol
1361 */
1362 void
zynquart_hwiflow(struct zynquart_softc * sc)1363 zynquart_hwiflow(struct zynquart_softc *sc)
1364 {
1365 #ifdef notyet
1366 struct zynquart_regs *regsp= &sc->sc_regs;
1367
1368 if (sc->sc_mcr_rts == 0)
1369 return;
1370
1371 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) {
1372 CLR(sc->sc_mcr, sc->sc_mcr_rts);
1373 CLR(sc->sc_mcr_active, sc->sc_mcr_rts);
1374 } else {
1375 SET(sc->sc_mcr, sc->sc_mcr_rts);
1376 SET(sc->sc_mcr_active, sc->sc_mcr_rts);
1377 }
1378 UR_WRITE_1(regsp, ZYNQUART_REG_MCR, sc->sc_mcr_active);
1379 #endif
1380 }
1381
1382
1383 void
zynquartstart(struct tty * tp)1384 zynquartstart(struct tty *tp)
1385 {
1386 struct zynquart_softc *sc =
1387 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(tp->t_dev));
1388 int s;
1389 u_char *tba;
1390 int tbc;
1391 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1392 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1393
1394 if (ZYNQUART_ISALIVE(sc) == 0)
1395 return;
1396
1397 s = spltty();
1398 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
1399 goto out;
1400 if (sc->sc_tx_stopped)
1401 goto out;
1402 if (!ttypull(tp))
1403 goto out;
1404
1405 /* Grab the first contiguous region of buffer space. */
1406 tba = tp->t_outq.c_cf;
1407 tbc = ndqb(&tp->t_outq, 0);
1408
1409 mutex_spin_enter(&sc->sc_lock);
1410
1411 sc->sc_tba = tba;
1412 sc->sc_tbc = tbc;
1413
1414 SET(tp->t_state, TS_BUSY);
1415 sc->sc_tx_busy = 1;
1416
1417 while (sc->sc_tbc > 0 &&
1418 !(bus_space_read_4(iot, ioh, UART_CHANNEL_STS) & STS_TFUL)) {
1419 bus_space_write_4(iot, ioh, UART_TX_RX_FIFO, *sc->sc_tba);
1420 sc->sc_tbc--;
1421 sc->sc_tba++;
1422 }
1423
1424 /* Enable transmit completion interrupts */
1425 zynquart_control_txint(sc, true);
1426
1427 mutex_spin_exit(&sc->sc_lock);
1428 out:
1429 splx(s);
1430 return;
1431 }
1432
1433 /*
1434 * Stop output on a line.
1435 */
1436 void
zynquartstop(struct tty * tp,int flag)1437 zynquartstop(struct tty *tp, int flag)
1438 {
1439 struct zynquart_softc *sc =
1440 device_lookup_private(&zynquart_cd, ZYNQUART_UNIT(tp->t_dev));
1441
1442 mutex_spin_enter(&sc->sc_lock);
1443 if (ISSET(tp->t_state, TS_BUSY)) {
1444 /* Stop transmitting at the next chunk. */
1445 sc->sc_tbc = 0;
1446 sc->sc_heldtbc = 0;
1447 if (!ISSET(tp->t_state, TS_TTSTOP))
1448 SET(tp->t_state, TS_FLUSH);
1449 }
1450 mutex_spin_exit(&sc->sc_lock);
1451 }
1452
1453 void
zynquartdiag(void * arg)1454 zynquartdiag(void *arg)
1455 {
1456 #ifdef notyet
1457 struct zynquart_softc *sc = arg;
1458 int overflows, floods;
1459
1460 mutex_spin_enter(&sc->sc_lock);
1461 overflows = sc->sc_overflows;
1462 sc->sc_overflows = 0;
1463 floods = sc->sc_floods;
1464 sc->sc_floods = 0;
1465 sc->sc_errors = 0;
1466 mutex_spin_exit(&sc->sc_lock);
1467
1468 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n",
1469 device_xname(sc->sc_dev),
1470 overflows, overflows == 1 ? "" : "s",
1471 floods, floods == 1 ? "" : "s");
1472 #endif
1473 }
1474
1475 integrate void
zynquart_rxsoft(struct zynquart_softc * sc,struct tty * tp)1476 zynquart_rxsoft(struct zynquart_softc *sc, struct tty *tp)
1477 {
1478 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint;
1479 u_int cc, scc, outp;
1480 uint16_t data;
1481 u_int code;
1482
1483 scc = cc = ZYNQUART_RBUF_AVAIL(sc);
1484
1485 #if 0
1486 if (cc == zynquart_rbuf_size-1) {
1487 sc->sc_floods++;
1488 if (sc->sc_errors++ == 0)
1489 callout_reset(&sc->sc_diag_callout, 60 * hz,
1490 zynquartdiag, sc);
1491 }
1492 #endif
1493
1494 /* If not yet open, drop the entire buffer content here */
1495 if (!ISSET(tp->t_state, TS_ISOPEN)) {
1496 sc->sc_rbuf_out = sc->sc_rbuf_in;
1497 cc = 0;
1498 }
1499
1500 outp = sc->sc_rbuf_out;
1501
1502 #define ERRBITS (INT_PARE|INT_FRAME|INT_ROVR)
1503
1504 while (cc) {
1505 data = sc->sc_rbuf[outp];
1506 code = data & 0xff;
1507 if (ISSET(__SHIFTOUT(data, ERROR_BITS), ERRBITS)) {
1508 if (sc->sc_errors.err == 0)
1509 callout_reset(&sc->sc_diag_callout,
1510 60 * hz, zynquartdiag, sc);
1511 if (ISSET(__SHIFTOUT(data, ERROR_BITS), INT_ROVR))
1512 sc->sc_errors.ovrrun++;
1513 if (ISSET(__SHIFTOUT(data, ERROR_BITS), INT_FRAME)) {
1514 sc->sc_errors.frmerr++;
1515 SET(code, TTY_FE);
1516 }
1517 if (ISSET(__SHIFTOUT(data, ERROR_BITS), INT_PARE)) {
1518 sc->sc_errors.prerr++;
1519 SET(code, TTY_PE);
1520 }
1521 }
1522 if ((*rint)(code, tp) == -1) {
1523 /*
1524 * The line discipline's buffer is out of space.
1525 */
1526 if (!ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_BLOCKED)) {
1527 /*
1528 * We're either not using flow control, or the
1529 * line discipline didn't tell us to block for
1530 * some reason. Either way, we have no way to
1531 * know when there's more space available, so
1532 * just drop the rest of the data.
1533 */
1534 sc->sc_rbuf_out = sc->sc_rbuf_in;
1535 cc = 0;
1536 } else {
1537 /*
1538 * Don't schedule any more receive processing
1539 * until the line discipline tells us there's
1540 * space available (through zynquarthwiflow()).
1541 * Leave the rest of the data in the input
1542 * buffer.
1543 */
1544 SET(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED);
1545 }
1546 break;
1547 }
1548 outp = ZYNQUART_RBUF_INC(sc, outp, 1);
1549 cc--;
1550 }
1551
1552 if (cc != scc) {
1553 sc->sc_rbuf_out = outp;
1554 mutex_spin_enter(&sc->sc_lock);
1555
1556 cc = ZYNQUART_RBUF_SPACE(sc);
1557
1558 /* Buffers should be ok again, release possible block. */
1559 if (cc >= sc->sc_r_lowat) {
1560 if (ISSET(sc->sc_rx_flags, ZYNQUART_RX_IBUF_OVERFLOWED)) {
1561 CLR(sc->sc_rx_flags, ZYNQUART_RX_IBUF_OVERFLOWED);
1562 zynquart_control_rxint(sc, true);
1563 }
1564 if (ISSET(sc->sc_rx_flags, ZYNQUART_RX_IBUF_BLOCKED)) {
1565 CLR(sc->sc_rx_flags, ZYNQUART_RX_IBUF_BLOCKED);
1566 zynquart_hwiflow(sc);
1567 }
1568 }
1569 mutex_spin_exit(&sc->sc_lock);
1570 }
1571 }
1572
1573 integrate void
zynquart_txsoft(struct zynquart_softc * sc,struct tty * tp)1574 zynquart_txsoft(struct zynquart_softc *sc, struct tty *tp)
1575 {
1576
1577 CLR(tp->t_state, TS_BUSY);
1578 if (ISSET(tp->t_state, TS_FLUSH))
1579 CLR(tp->t_state, TS_FLUSH);
1580 else
1581 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf));
1582 (*tp->t_linesw->l_start)(tp);
1583 }
1584
1585 integrate void
zynquart_stsoft(struct zynquart_softc * sc,struct tty * tp)1586 zynquart_stsoft(struct zynquart_softc *sc, struct tty *tp)
1587 {
1588 #ifdef notyet
1589 u_char msr, delta;
1590
1591 mutex_spin_enter(&sc->sc_lock);
1592 msr = sc->sc_msr;
1593 delta = sc->sc_msr_delta;
1594 sc->sc_msr_delta = 0;
1595 mutex_spin_exit(&sc->sc_lock);
1596
1597 if (ISSET(delta, sc->sc_msr_dcd)) {
1598 /*
1599 * Inform the tty layer that carrier detect changed.
1600 */
1601 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD));
1602 }
1603
1604 if (ISSET(delta, sc->sc_msr_cts)) {
1605 /* Block or unblock output according to flow control. */
1606 if (ISSET(msr, sc->sc_msr_cts)) {
1607 sc->sc_tx_stopped = 0;
1608 (*tp->t_linesw->l_start)(tp);
1609 } else {
1610 sc->sc_tx_stopped = 1;
1611 }
1612 }
1613
1614 #endif
1615 #ifdef ZYNQUART_DEBUG
1616 if (zynquart_debug)
1617 zynquartstatus(sc, "zynquart_stsoft");
1618 #endif
1619 }
1620
1621 void
zynquartsoft(void * arg)1622 zynquartsoft(void *arg)
1623 {
1624 struct zynquart_softc *sc = arg;
1625 struct tty *tp;
1626
1627 if (ZYNQUART_ISALIVE(sc) == 0)
1628 return;
1629
1630 tp = sc->sc_tty;
1631
1632 if (sc->sc_rx_ready) {
1633 sc->sc_rx_ready = 0;
1634 zynquart_rxsoft(sc, tp);
1635 }
1636
1637 if (sc->sc_st_check) {
1638 sc->sc_st_check = 0;
1639 zynquart_stsoft(sc, tp);
1640 }
1641
1642 if (sc->sc_tx_done) {
1643 sc->sc_tx_done = 0;
1644 zynquart_txsoft(sc, tp);
1645 }
1646 }
1647
1648 int
zynquartintr(void * arg)1649 zynquartintr(void *arg)
1650 {
1651 struct zynquart_softc *sc = arg;
1652 uint32_t sts;
1653 uint32_t int_sts;
1654 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1655 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1656
1657 if (ZYNQUART_ISALIVE(sc) == 0)
1658 return (0);
1659
1660 mutex_spin_enter(&sc->sc_lock);
1661
1662 int_sts = bus_space_read_4(iot, ioh, UART_CHNL_INT_STS);
1663 do {
1664 sts = bus_space_read_4(iot, ioh, UART_CHANNEL_STS);
1665 if (!(sts & STS_REMPTY))
1666 zynquartintr_read(sc);
1667 } while (!(sts & STS_REMPTY));
1668
1669 if (sts & STS_TEMPTY)
1670 zynquartintr_send(sc);
1671
1672 bus_space_write_4(iot, ioh, UART_CHNL_INT_STS, int_sts);
1673
1674 mutex_spin_exit(&sc->sc_lock);
1675
1676 /* Wake up the poller. */
1677 softint_schedule(sc->sc_si);
1678
1679 #ifdef RND_COM
1680 rnd_add_uint32(&sc->rnd_source, iir | lsr);
1681 #endif
1682
1683 return (1);
1684 }
1685
1686
1687 /*
1688 * called when there is least one character in rxfifo
1689 *
1690 */
1691
1692 static void
zynquartintr_read(struct zynquart_softc * sc)1693 zynquartintr_read(struct zynquart_softc *sc)
1694 {
1695 int cc;
1696 uint16_t rd;
1697 uint32_t sts;
1698 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1699 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1700
1701 cc = ZYNQUART_RBUF_SPACE(sc);
1702
1703 /* clear aging timer interrupt */
1704 bus_space_write_4(iot, ioh, UART_CHNL_INT_STS, INT_TIMEOUT);
1705
1706 while (cc > 0) {
1707 int cn_trapped = 0;
1708
1709 sc->sc_rbuf[sc->sc_rbuf_in] = rd =
1710 bus_space_read_4(iot, ioh, UART_TX_RX_FIFO);
1711
1712 cn_check_magic(sc->sc_tty->t_dev,
1713 rd & 0xff, zynquart_cnm_state);
1714
1715 if (!cn_trapped) {
1716 sc->sc_rbuf_in = ZYNQUART_RBUF_INC(sc, sc->sc_rbuf_in, 1);
1717 cc--;
1718 }
1719
1720 sts = bus_space_read_4(iot, ioh, UART_CHANNEL_STS);
1721 if (sts & STS_REMPTY)
1722 break;
1723 }
1724
1725 /*
1726 * Current string of incoming characters ended because
1727 * no more data was available or we ran out of space.
1728 * Schedule a receive event if any data was received.
1729 * If we're out of space, turn off receive interrupts.
1730 */
1731 if (!ISSET(sc->sc_rx_flags, ZYNQUART_RX_TTY_OVERFLOWED))
1732 sc->sc_rx_ready = 1;
1733 /*
1734 * See if we are in danger of overflowing a buffer. If
1735 * so, use hardware flow control to ease the pressure.
1736 */
1737 if (!ISSET(sc->sc_rx_flags, ZYNQUART_RX_IBUF_BLOCKED) &&
1738 cc < sc->sc_r_hiwat) {
1739 sc->sc_rx_flags |= ZYNQUART_RX_IBUF_BLOCKED;
1740 zynquart_hwiflow(sc);
1741 }
1742
1743 /*
1744 * If we're out of space, disable receive interrupts
1745 * until the queue has drained a bit.
1746 */
1747 if (!cc) {
1748 sc->sc_rx_flags |= ZYNQUART_RX_IBUF_OVERFLOWED;
1749 zynquart_control_rxint(sc, false);
1750 }
1751 }
1752
1753 void
zynquartintr_send(struct zynquart_softc * sc)1754 zynquartintr_send(struct zynquart_softc *sc)
1755 {
1756 uint32_t sts;
1757 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1758 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1759
1760 sts = bus_space_read_4(iot, ioh, UART_CHANNEL_STS);
1761
1762 if (sc->sc_pending) {
1763 if (sts & STS_TEMPTY) {
1764 zynquart_load_pendings(sc);
1765 sc->sc_tbc = sc->sc_heldtbc;
1766 sc->sc_heldtbc = 0;
1767 } else {
1768 /* wait for TX fifo empty */
1769 zynquart_control_txint(sc, true);
1770 return;
1771 }
1772 }
1773
1774 while (sc->sc_tbc > 0 &&
1775 !(bus_space_read_4(iot, ioh, UART_CHANNEL_STS) & STS_TFUL)) {
1776 bus_space_write_4(iot, ioh, UART_TX_RX_FIFO, *sc->sc_tba);
1777 sc->sc_tbc--;
1778 sc->sc_tba++;
1779 }
1780
1781 if (sc->sc_tbc > 0)
1782 zynquart_control_txint(sc, true);
1783 else {
1784 /* no more chars to send.
1785 we don't need tx interrupt any more. */
1786 zynquart_control_txint(sc, false);
1787 if (sc->sc_tx_busy) {
1788 sc->sc_tx_busy = 0;
1789 sc->sc_tx_done = 1;
1790 }
1791 }
1792 }
1793
1794 static void
zynquart_disable_all_interrupts(struct zynquart_softc * sc)1795 zynquart_disable_all_interrupts(struct zynquart_softc *sc)
1796 {
1797 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1798 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1799
1800 bus_space_write_4(iot, ioh, UART_INTRPT_DIS, 0xffffffff);
1801 }
1802
1803 static void
zynquart_control_rxint(struct zynquart_softc * sc,bool enable)1804 zynquart_control_rxint(struct zynquart_softc *sc, bool enable)
1805 {
1806 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1807 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1808 uint32_t mask = INT_TIMEOUT | INT_PARE | INT_FRAME | INT_ROVR | INT_RFUL | INT_RTRIG;
1809 uint32_t sts;
1810
1811 /* clear */
1812 sts = bus_space_read_4(iot, ioh, UART_CHNL_INT_STS);
1813 bus_space_write_4(iot, ioh, UART_CHNL_INT_STS, sts);
1814
1815 if (enable)
1816 bus_space_write_4(iot, ioh, UART_INTRPT_EN, mask);
1817 else
1818 bus_space_write_4(iot, ioh, UART_INTRPT_DIS, mask);
1819 }
1820
1821 static void
zynquart_control_txint(struct zynquart_softc * sc,bool enable)1822 zynquart_control_txint(struct zynquart_softc *sc, bool enable)
1823 {
1824 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1825 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1826 uint32_t mask = INT_TEMPTY;
1827
1828 if (enable)
1829 bus_space_write_4(iot, ioh, UART_INTRPT_EN, mask);
1830 else
1831 bus_space_write_4(iot, ioh, UART_INTRPT_DIS, mask);
1832 }
1833
1834
1835 static void
zynquart_load_params(struct zynquart_softc * sc)1836 zynquart_load_params(struct zynquart_softc *sc)
1837 {
1838 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1839 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1840
1841 bus_space_write_4(iot, ioh, UART_MODE, sc->sc_mcr);
1842 }
1843
1844 static void
zynquart_load_speed(struct zynquart_softc * sc)1845 zynquart_load_speed(struct zynquart_softc *sc)
1846 {
1847 /* bus_space_tag_t iot = sc->sc_regs.ur_iot; */
1848 /* bus_space_handle_t ioh = sc->sc_regs.ur_ioh; */
1849
1850 /* XXX */
1851 }
1852
1853
1854 static void
zynquart_load_pendings(struct zynquart_softc * sc)1855 zynquart_load_pendings(struct zynquart_softc *sc)
1856 {
1857 if (sc->sc_pending & ZYNQUART_PEND_PARAM)
1858 zynquart_load_params(sc);
1859 if (sc->sc_pending & ZYNQUART_PEND_SPEED)
1860 zynquart_load_speed(sc);
1861 sc->sc_pending = 0;
1862 }
1863
1864 /*
1865 * The following functions are polled getc and putc routines, shared
1866 * by the console and kgdb glue.
1867 *
1868 * The read-ahead code is so that you can detect pending in-band
1869 * cn_magic in polled mode while doing output rather than having to
1870 * wait until the kernel decides it needs input.
1871 */
1872
1873 #define READAHEAD_RING_LEN 16
1874 static int zynquart_readahead[READAHEAD_RING_LEN];
1875 static int zynquart_readahead_in = 0;
1876 static int zynquart_readahead_out = 0;
1877 #define READAHEAD_IS_EMPTY() (zynquart_readahead_in==zynquart_readahead_out)
1878 #define READAHEAD_IS_FULL() \
1879 (((zynquart_readahead_in+1) & (READAHEAD_RING_LEN-1)) ==zynquart_readahead_out)
1880
1881 int
zynquart_common_getc(dev_t dev,struct zynquart_regs * regsp)1882 zynquart_common_getc(dev_t dev, struct zynquart_regs *regsp)
1883 {
1884 int s = splserial();
1885 u_char c;
1886 bus_space_tag_t iot = regsp->ur_iot;
1887 bus_space_handle_t ioh = regsp->ur_ioh;
1888 uint32_t sts;
1889
1890 /* got a character from reading things earlier */
1891 if (zynquart_readahead_in != zynquart_readahead_out) {
1892
1893 c = zynquart_readahead[zynquart_readahead_out];
1894 zynquart_readahead_out = (zynquart_readahead_out + 1) &
1895 (READAHEAD_RING_LEN-1);
1896 splx(s);
1897 return (c);
1898 }
1899
1900 /* block until a character becomes available */
1901 while ((sts = bus_space_read_4(iot, ioh, UART_CHANNEL_STS))
1902 & STS_REMPTY)
1903 continue;
1904
1905 c = 0xff & bus_space_read_4(iot, ioh, UART_TX_RX_FIFO);
1906
1907 if (!db_active) {
1908 int cn_trapped __unused = 0;
1909 cn_check_magic(dev, c, zynquart_cnm_state);
1910 }
1911 splx(s);
1912 return (c);
1913 }
1914
1915 void
zynquart_common_putc(dev_t dev,struct zynquart_regs * regsp,int c)1916 zynquart_common_putc(dev_t dev, struct zynquart_regs *regsp, int c)
1917 {
1918 int s = splserial();
1919 int cin, timo;
1920 bus_space_tag_t iot = regsp->ur_iot;
1921 bus_space_handle_t ioh = regsp->ur_ioh;
1922
1923 if (!READAHEAD_IS_FULL() &&
1924 !(bus_space_read_4(iot, ioh, UART_CHANNEL_STS) & STS_REMPTY)) {
1925 int cn_trapped __unused = 0;
1926
1927 cin = bus_space_read_4(iot, ioh, UART_TX_RX_FIFO);
1928 cn_check_magic(dev, cin & 0xff, zynquart_cnm_state);
1929 zynquart_readahead_in = (zynquart_readahead_in + 1) &
1930 (READAHEAD_RING_LEN-1);
1931 }
1932
1933 /* wait for any pending transmission to finish */
1934 timo = 150000;
1935 do {
1936 if (!(bus_space_read_4(iot, ioh, UART_CHANNEL_STS) & STS_TFUL)) {
1937 bus_space_write_4(iot, ioh, UART_TX_RX_FIFO, c);
1938 break;
1939 }
1940 } while(--timo > 0);
1941
1942 ZYNQUART_BARRIER(regsp, BR | BW);
1943
1944 splx(s);
1945 }
1946
1947 /*
1948 * Initialize UART for use as console or KGDB line.
1949 */
1950 int
zynquart_init(struct zynquart_regs * regsp,int rate,tcflag_t cflag)1951 zynquart_init(struct zynquart_regs *regsp, int rate, tcflag_t cflag)
1952 {
1953 struct zynquart_baudrate_ratio ratio;
1954
1955 if (bus_space_map(regsp->ur_iot, regsp->ur_iobase, UART_SIZE, 0,
1956 ®sp->ur_ioh))
1957 return ENOMEM; /* ??? */
1958
1959 if (zynquartspeed(rate, &ratio) < 0)
1960 return EINVAL;
1961
1962 /* clear status registers */
1963 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, UART_CHNL_INT_STS, 0xffff);
1964 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, UART_CHANNEL_STS, 0xffff);
1965
1966 return (0);
1967 }
1968
1969
1970
1971 /*
1972 * Following are all routines needed for UART to act as console
1973 */
1974 struct consdev zynquartcons = {
1975 .cn_getc = zynquartcngetc,
1976 .cn_putc = zynquartcnputc,
1977 .cn_pollc = nullcnpollc
1978 };
1979
1980
1981 int
zynquart_cons_attach(bus_space_tag_t iot,paddr_t iobase,u_int rate,tcflag_t cflag)1982 zynquart_cons_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate,
1983 tcflag_t cflag)
1984 {
1985 struct zynquart_regs regs;
1986 int res;
1987
1988 regs.ur_iot = iot;
1989 regs.ur_iobase = iobase;
1990
1991 res = zynquart_init(®s, rate, cflag);
1992 if (res)
1993 return (res);
1994
1995 cn_tab = &zynquartcons;
1996 cn_init_magic(&zynquart_cnm_state);
1997 cn_set_magic("\047\001"); /* default magic is BREAK */
1998
1999 zynquartconsrate = rate;
2000 zynquartconscflag = cflag;
2001
2002 zynquartconsregs = regs;
2003
2004 return 0;
2005 }
2006
2007 int
zynquartcngetc(dev_t dev)2008 zynquartcngetc(dev_t dev)
2009 {
2010 return (zynquart_common_getc(dev, &zynquartconsregs));
2011 }
2012
2013 /*
2014 * Console kernel output character routine.
2015 */
2016 void
zynquartcnputc(dev_t dev,int c)2017 zynquartcnputc(dev_t dev, int c)
2018 {
2019 zynquart_common_putc(dev, &zynquartconsregs, c);
2020 }
2021
2022 #ifdef KGDB
2023 int
zynquart_kgdb_attach(bus_space_tag_t iot,paddr_t iobase,u_int rate,tcflag_t cflag)2024 zynquart_kgdb_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate,
2025 tcflag_t cflag)
2026 {
2027 int res;
2028
2029 if (iot == zynquartconsregs.ur_iot &&
2030 iobase == zynquartconsregs.ur_iobase) {
2031 #if !defined(DDB)
2032 return (EBUSY); /* cannot share with console */
2033 #else
2034 zynquart_kgdb_regs.ur_iot = iot;
2035 zynquart_kgdb_regs.ur_ioh = zynquartconsregs.ur_ioh;
2036 zynquart_kgdb_regs.ur_iobase = iobase;
2037 #endif
2038 } else {
2039 zynquart_kgdb_regs.ur_iot = iot;
2040 zynquart_kgdb_regs.ur_iobase = iobase;
2041
2042 res = zynquart_init(&zynquart_kgdb_regs, rate, cflag);
2043 if (res)
2044 return (res);
2045
2046 /*
2047 * XXXfvdl this shouldn't be needed, but the cn_magic goo
2048 * expects this to be initialized
2049 */
2050 cn_init_magic(&zynquart_cnm_state);
2051 cn_set_magic("\047\001");
2052 }
2053
2054 kgdb_attach(zynquart_kgdb_getc, zynquart_kgdb_putc, &zynquart_kgdb_regs);
2055 kgdb_dev = 123; /* unneeded, only to satisfy some tests */
2056
2057 return (0);
2058 }
2059
2060 /* ARGSUSED */
2061 int
zynquart_kgdb_getc(void * arg)2062 zynquart_kgdb_getc(void *arg)
2063 {
2064 struct zynquart_regs *regs = arg;
2065
2066 return (zynquart_common_getc(NODEV, regs));
2067 }
2068
2069 /* ARGSUSED */
2070 void
zynquart_kgdb_putc(void * arg,int c)2071 zynquart_kgdb_putc(void *arg, int c)
2072 {
2073 struct zynquart_regs *regs = arg;
2074
2075 zynquart_common_putc(NODEV, regs, c);
2076 }
2077 #endif /* KGDB */
2078
2079 /* helper function to identify the zynquart ports used by
2080 console or KGDB (and not yet autoconf attached) */
2081 int
zynquart_is_console(bus_space_tag_t iot,bus_addr_t iobase,bus_space_handle_t * ioh)2082 zynquart_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh)
2083 {
2084 bus_space_handle_t help;
2085
2086 if (!zynquartconsattached &&
2087 iot == zynquartconsregs.ur_iot && iobase == zynquartconsregs.ur_iobase)
2088 help = zynquartconsregs.ur_ioh;
2089 #ifdef KGDB
2090 else if (!zynquart_kgdb_attached &&
2091 iot == zynquart_kgdb_regs.ur_iot && iobase == zynquart_kgdb_regs.ur_iobase)
2092 help = zynquart_kgdb_regs.ur_ioh;
2093 #endif
2094 else
2095 return (0);
2096
2097 if (ioh)
2098 *ioh = help;
2099 return (1);
2100 }
2101
2102 #ifdef notyet
2103
2104 bool
zynquart_cleanup(device_t self,int how)2105 zynquart_cleanup(device_t self, int how)
2106 {
2107 /*
2108 * this routine exists to serve as a shutdown hook for systems that
2109 * have firmware which doesn't interact properly with a zynquart device in
2110 * FIFO mode.
2111 */
2112 struct zynquart_softc *sc = device_private(self);
2113
2114 if (ISSET(sc->sc_hwflags, ZYNQUART_HW_FIFO))
2115 UR_WRITE_1(&sc->sc_regs, ZYNQUART_REG_FIFO, 0);
2116
2117 return true;
2118 }
2119 #endif
2120
2121 #ifdef notyet
2122 bool
zynquart_suspend(device_t self PMF_FN_ARGS)2123 zynquart_suspend(device_t self PMF_FN_ARGS)
2124 {
2125 struct zynquart_softc *sc = device_private(self);
2126
2127 UR_WRITE_1(&sc->sc_regs, ZYNQUART_REG_IER, 0);
2128 (void)CSR_READ_1(&sc->sc_regs, ZYNQUART_REG_IIR);
2129
2130 return true;
2131 }
2132 #endif
2133
2134 #ifdef notyet
2135 bool
zynquart_resume(device_t self PMF_FN_ARGS)2136 zynquart_resume(device_t self PMF_FN_ARGS)
2137 {
2138 struct zynquart_softc *sc = device_private(self);
2139
2140 mutex_spin_enter(&sc->sc_lock);
2141 zynquart_loadchannelregs(sc);
2142 mutex_spin_exit(&sc->sc_lock);
2143
2144 return true;
2145 }
2146 #endif
2147
2148 static void
zynquart_enable_debugport(struct zynquart_softc * sc)2149 zynquart_enable_debugport(struct zynquart_softc *sc)
2150 {
2151 /* bus_space_tag_t iot = sc->sc_regs.ur_iot; */
2152 /* bus_space_handle_t ioh = sc->sc_regs.ur_ioh; */
2153 }
2154
2155
2156 void
zynquart_set_frequency(u_int freq,u_int div)2157 zynquart_set_frequency(u_int freq, u_int div)
2158 {
2159 zynquart_freq = freq;
2160 zynquart_freqdiv = div;
2161 }
2162