1 /* $NetBSD: gxiic.c,v 1.12 2022/06/18 22:11:00 andvar Exp $ */
2 /*
3 * Copyright (c) 2007 KIYOHARA Takashi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: gxiic.c,v 1.12 2022/06/18 22:11:00 andvar Exp $");
29
30 #include <sys/param.h>
31 #include <sys/device.h>
32 #include <sys/errno.h>
33 #include <sys/mutex.h>
34
35 #include <arm/xscale/pxa2x0var.h>
36 #include <arm/xscale/pxa2x0_i2c.h>
37
38 #include <evbarm/gumstix/gumstixvar.h>
39
40 #include <dev/i2c/i2cvar.h>
41
42
43 struct gxiic_softc {
44 struct pxa2x0_i2c_softc sc_pxa_i2c;
45
46 struct i2c_controller sc_i2c;
47 };
48
49
50 static int gxiicmatch(device_t, cfdata_t, void *);
51 static void gxiicattach(device_t, device_t, void *);
52
53 /* functions for i2c_controller */
54 static int gxiic_acquire_bus(void *, int);
55 static void gxiic_release_bus(void *, int);
56 static int gxiic_exec(void *cookie, i2c_op_t, i2c_addr_t, const void *, size_t,
57 void *, size_t, int);
58
59
60 CFATTACH_DECL_NEW(gxiic, sizeof(struct gxiic_softc),
61 gxiicmatch, gxiicattach, NULL, NULL);
62
63
64 /* ARGSUSED */
65 static int
gxiicmatch(device_t parent,cfdata_t match,void * aux)66 gxiicmatch(device_t parent, cfdata_t match, void *aux)
67 {
68 struct pxaip_attach_args *pxa = aux;
69
70 if (strcmp(pxa->pxa_name, match->cf_name) != 0)
71 return 0;
72
73 pxa->pxa_size = PXA2X0_I2C_SIZE;
74 return 1;
75 }
76
77 /* ARGSUSED */
78 static void
gxiicattach(device_t parent,device_t self,void * aux)79 gxiicattach(device_t parent, device_t self, void *aux)
80 {
81 struct pxaip_attach_args *pxa = aux;
82 struct gxiic_softc *sc = device_private(self);
83 struct i2cbus_attach_args iba;
84
85 aprint_normal("\n");
86 aprint_naive("\n");
87
88 sc->sc_pxa_i2c.sc_dev = self;
89 sc->sc_pxa_i2c.sc_iot = pxa->pxa_iot;
90 sc->sc_pxa_i2c.sc_addr = pxa->pxa_addr;
91 sc->sc_pxa_i2c.sc_size = pxa->pxa_size;
92 sc->sc_pxa_i2c.sc_flags = 0;
93 if (pxa2x0_i2c_attach_sub(&sc->sc_pxa_i2c)) {
94 aprint_error_dev(self, "unable to attach PXA I2C\n");
95 return;
96 }
97
98 /* Initialize i2c_controller */
99 iic_tag_init(&sc->sc_i2c);
100 sc->sc_i2c.ic_cookie = sc;
101 sc->sc_i2c.ic_acquire_bus = gxiic_acquire_bus;
102 sc->sc_i2c.ic_release_bus = gxiic_release_bus;
103 sc->sc_i2c.ic_exec = gxiic_exec;
104
105 memset(&iba, 0, sizeof(iba));
106 iba.iba_tag = &sc->sc_i2c;
107 pxa2x0_i2c_open(&sc->sc_pxa_i2c);
108 config_found(sc->sc_pxa_i2c.sc_dev, &iba, iicbus_print, CFARGS_NONE);
109 pxa2x0_i2c_close(&sc->sc_pxa_i2c);
110 }
111
112 static int
gxiic_acquire_bus(void * cookie,int flags)113 gxiic_acquire_bus(void *cookie, int flags)
114 {
115 struct gxiic_softc *sc = cookie;
116
117 pxa2x0_i2c_open(&sc->sc_pxa_i2c);
118
119 return 0;
120 }
121
122 static void
gxiic_release_bus(void * cookie,int flags)123 gxiic_release_bus(void *cookie, int flags)
124 {
125 struct gxiic_softc *sc = cookie;
126
127 pxa2x0_i2c_close(&sc->sc_pxa_i2c);
128 }
129
130 static int
gxiic_exec(void * cookie,i2c_op_t op,i2c_addr_t addr,const void * vcmd,size_t cmdlen,void * vbuf,size_t buflen,int flags)131 gxiic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *vcmd,
132 size_t cmdlen, void *vbuf, size_t buflen, int flags)
133 {
134 struct gxiic_softc *sc = cookie;
135 int rv = -1;
136
137 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1))
138 rv = pxa2x0_i2c_read(&sc->sc_pxa_i2c, addr, (u_char *)vbuf);
139
140 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) {
141 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c, addr, *(u_char *)vbuf);
142 if (rv == 0)
143 rv = pxa2x0_i2c_read(&sc->sc_pxa_i2c,
144 addr, (u_char *)vbuf);
145 }
146
147 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 2)) {
148 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c, addr, *(u_char *)vbuf);
149 if (rv == 0)
150 rv = pxa2x0_i2c_read(&sc->sc_pxa_i2c,
151 addr, (u_char *)vbuf);
152 if (rv == 0)
153 rv = pxa2x0_i2c_read(&sc->sc_pxa_i2c,
154 addr, (u_char *)(vbuf) + 1);
155 }
156
157 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1))
158 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c, addr, *(u_char *)vbuf);
159
160 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) {
161 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c,
162 addr, *(const u_char *)vcmd);
163 if (rv == 0)
164 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c,
165 addr, *(u_char *)vbuf);
166 }
167
168 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 2)) {
169 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c,
170 addr, *(const u_char *)vcmd);
171 if (rv == 0)
172 rv = pxa2x0_i2c_write_2(&sc->sc_pxa_i2c,
173 addr, *(u_short *)vbuf);
174 }
175
176 /* Handle quick_read/quick_write ops - XXX Untested XXX */
177 if ((cmdlen == 0) && (buflen == 0))
178 rv = pxa2x0_i2c_quick(&sc->sc_pxa_i2c, addr,
179 I2C_OP_READ_P(op)?1:0);
180
181 return rv;
182 }
183