1/* $NetBSD: iq80321_start.S,v 1.5 2011/01/31 06:28:03 matt Exp $ */ 2 3/* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#include <machine/asm.h> 39#include <arm/armreg.h> 40#include "assym.h" 41 42RCSID("$NetBSD: iq80321_start.S,v 1.5 2011/01/31 06:28:03 matt Exp $") 43 44 .section .start,"ax",%progbits 45 46 .global _C_LABEL(iq80321_start) 47_C_LABEL(iq80321_start): 48 /* 49 * We will go ahead and disable the MMU here so that we don't 50 * have to worry about flushing caches, etc. 51 * 52 * Note that we may not currently be running VA==PA, which means 53 * we'll need to leap to the next insn after disabing the MMU. 54 */ 55 adr r8, Lunmapped 56 bic r8, r8, #0xff000000 /* clear upper 8 bits */ 57 orr r8, r8, #0xa0000000 /* OR in physical base address */ 58 59 mrc p15, 0, r2, c1, c0, 0 60 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 61 mcr p15, 0, r2, c1, c0, 0 62 63 nop 64 nop 65 nop 66 67 mov pc, r8 /* Heave-ho! */ 68 69Lunmapped: 70 /* 71 * We want to construct a memory map that maps us 72 * VA==PA (SDRAM at 0xa0000000) and also double-maps 73 * that space at 0xc0000000 (where the kernel address 74 * space starts). We create these mappings uncached 75 * and unbuffered to be safe. 76 * 77 * We also want to map the various devices we want to 78 * talk to VA==PA during bootstrap. 79 * 80 * We just use section mappings for all of this to make it easy. 81 * 82 * We will put the L1 table to do all this at 0xa0004000, which 83 * is also where RedBoot puts it. 84 */ 85 86 /* 87 * Step 1: Map the entire address space VA==PA. 88 */ 89 adr r0, Ltable 90 ldr r0, [r0] /* r0 = &l1table */ 91 92 mov r3, #(L1_S_AP_KRW) 93 orr r3, r3, #(L1_TYPE_S) 94 mov r2, #0x100000 /* advance by 1MB */ 95 mov r1, #0x1000 /* 4096MB */ 961: 97 str r3, [r0], #0x04 98 add r3, r3, r2 99 subs r1, r1, #1 100 bgt 1b 101 102 /* 103 * Step 2: Map VA 0xc0000000->0xc3ffffff to PA 0xa0000000->0xa3ffffff. 104 */ 105 adr r0, Ltable /* r0 = &l1table */ 106 ldr r0, [r0] 107 108 mov r3, #(L1_S_AP_KRW) 109 orr r3, r3, #(L1_TYPE_S) 110 orr r3, r3, #0xa0000000 111 add r0, r0, #(0xc00 * 4) /* offset to 0xc00xxxxx */ 112 mov r1, #0x40 /* 64MB */ 1131: 114 str r3, [r0], #0x04 115 add r3, r3, r2 116 subs r1, r1, #1 117 bgt 1b 118 119 /* OK! Page table is set up. Give it to the CPU. */ 120 adr r0, Ltable 121 ldr r0, [r0] 122 mcr p15, 0, r0, c2, c0, 0 123 124 /* Flush the old TLBs, just in case. */ 125 mcr p15, 0, r0, c8, c7, 0 126 127 /* Set the Domain Access register. Very important! */ 128 mov r0, #1 129 mcr p15, 0, r0, c3, c0, 0 130 131 /* Get ready to jump to the "real" kernel entry point... */ 132 ldr r0, Lstart 133 134 /* OK, let's enable the MMU. */ 135 mrc p15, 0, r2, c1, c0, 0 136 orr r2, r2, #CPU_CONTROL_MMU_ENABLE 137 mcr p15, 0, r2, c1, c0, 0 138 139 nop 140 nop 141 nop 142 143 /* CPWAIT sequence to make sure the MMU is on... */ 144 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 145 mov r2, r2 /* force it to complete */ 146 mov pc, r0 /* leap to kernel entry point! */ 147 148Ltable: 149 .word 0xa0004000 150 151Lstart: 152 .word start 153