1 /* $NetBSD: octeonreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Simon Burge. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #ifndef _OCTEONREG_H_ 34 #define _OCTEONREG_H_ 35 36 #define OCTEON_PLL_REF_CLK 50000000 /* defined as 50MHz */ 37 38 /* ---- virtual addressing */ 39 40 /* CVMSEG virtual addresses */ 41 #define OCTEON_CVMSEG_LM UINT64_C(0xffffffffffff8000) 42 #define OCTEON_CVMSEG_IO UINT64_C(0xffffffffffffa000) 43 44 #define OCTEON_IOBDMA_GLOBAL_ADDR UINT64_C(0xffffffffffffa200) 45 #define OCTEON_IOBDMA_LOCAL_ADDR UINT64_C(0xffffffffffffb200) 46 #define OCTEON_LMTDMA_GLOBAL_ADDR UINT64_C(0xffffffffffffa400) 47 #define OCTEON_LMTDMA_LOCAL_ADDR UINT64_C(0xffffffffffffb400) 48 /* use globally ordered by default */ 49 #define OCTEON_IOBDMA_ADDR OCTEON_IOBDMA_GLOBAL_ADDR 50 #define OCTEON_LMTDMA_ADDR OCTEON_LMTDMA_GLOBAL_ADDR 51 52 /* ---- physical addressing */ 53 54 /* 55 * Cavium Octeon has a 49 bit physical address space. 56 * 57 * Bit 48 == 0 defines a L2 or DRAM address 58 * Bit 48 == 1 defines an IO address 59 * 60 * For IO addresses: 61 * Bits 47-43: Major DID - directs request to correct hardware block 62 * Bits 42-40: Sub DID - directs request within the hardware block 63 * Bits 39-38: reserved - 0 64 * Bits 37-36: reserved - 0 (on Octeon and Octeon Plus) 65 * Bits 37-36: Node - selects node/chip (Octeon II) 66 * Bits 35- 0: IO bus device address with the DID 67 */ 68 #define OCTEON_ADDR_IO __BIT(48) 69 #define OCTEON_ADDR_MAJOR_DID __BITS(47,43) 70 #define OCTEON_ADDR_SUB_DID __BITS(42,40) 71 #define OCTEON_ADDR_NODE __BITS(37,36) 72 #define OCTEON_ADDR_OFFSET __BITS(35,0) 73 74 #define OCTEON_ADDR_DID(major, sub) ( \ 75 __SHIFTIN((major), OCTEON_ADDR_MAJOR_DID) | \ 76 __SHIFTIN((sub), OCTEON_ADDR_SUB_DID)) 77 78 /* used to build addresses for load/store operations */ 79 #define OCTEON_ADDR_IO_DID(major, sub) \ 80 (OCTEON_ADDR_IO | OCTEON_ADDR_DID((major), (sub))) 81 82 83 /* ---- core specific registers */ 84 85 /* OCTEON II */ 86 #define MIO_RST_BOOT UINT64_C(0x1180000001600) 87 #define MIO_RST_BOOT_C_MUL __BITS(36,30) 88 #define MIO_RST_BOOT_PNR_MUL __BITS(29,24) 89 90 91 /* OCTEON III */ 92 #define MIO_FUS_PDF UINT64_C(0x1180000001428) 93 #define MIO_FUS_PDF_IS_71XX __BIT(32) 94 95 #define RST_BOOT UINT64_C(0x1180006001600) 96 #define RST_BOOT_C_MUL __BITS(36,30) 97 #define RST_BOOT_PNR_MUL __BITS(29,24) 98 #define RST_DELAY UINT64_C(0x1180006001608) 99 #define RST_CFG UINT64_C(0x1180006001610) 100 #define RST_OCX UINT64_C(0x1180006001618) 101 #define RST_INT UINT64_C(0x1180006001628) 102 #define RST_CKILL UINT64_C(0x1180006001638) 103 #define RST_CTL(n) (UINT64_C(0x1180006001640) + (n) * 0x8) 104 #define RST_SOFT_RST UINT64_C(0x1180006001680) 105 #define RST_SOFT_PRST(n) (UINT64_C(0x11800060016c0) + (n) * 0x8) 106 #define RST_PP_POWER UINT64_C(0x1180006001700) 107 #define RST_POWER_DBG UINT64_C(0x1180006001708) 108 #define RST_REF_CNTR UINT64_C(0x1180006001758) 109 #define RST_COLD_DATA(n) (UINT64_C(0x11800060017c0) + (n) * 0x8) 110 111 112 /* ---- IOBDMA */ 113 114 /* 4.7 IOBDMA Operations */ 115 #define IOBDMA_SCRADDR __BITS(63,56) 116 #define IOBDMA_LEN __BITS(55,48) 117 /* IOBDMA_MAJOR_DID same as OCTEON_MAJOR_DID */ 118 /* IOBDMA_SUB_DID same as OCTEON_SUB_DID */ 119 /* reserved 39:38 */ 120 #define IOBDMA_NODE __BITS(37,36) /* Octeon 3 only */ 121 #define IOBDMA_OFFSET __BITS(35,0) 122 /* technically __BITS(2,0) are reserved as 0, address must be 64-bit aligned */ 123 124 #define IOBDMA_CREATE(major, sub, scr, len, offset) ( \ 125 OCTEON_ADDR_DID((major), (sub)) | \ 126 __SHIFTIN((scr), IOBDMA_SCRADDR) | \ 127 __SHIFTIN((len), IOBDMA_LEN) | \ 128 __SHIFTIN((offset), IOBDMA_OFFSET)) 129 130 131 #endif /* !_OCTEONREG_H_ */ 132