1 /* $NetBSD: cpu_subr.c,v 1.93 2018/05/04 17:01:29 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.93 2018/05/04 17:01:29 macallan Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_ppccache.h" 41 #include "opt_multiprocessor.h" 42 #include "opt_altivec.h" 43 #include "sysmon_envsys.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/types.h> 49 #include <sys/lwp.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/pcb.h> 55 #include <powerpc/psl.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/hid.h> 58 #include <powerpc/oea/hid_601.h> 59 #include <powerpc/oea/spr.h> 60 #include <powerpc/oea/cpufeat.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 static void cpu_enable_l2cr(register_t); 65 static void cpu_enable_l3cr(register_t); 66 static void cpu_config_l2cr(int); 67 static void cpu_config_l3cr(int); 68 static void cpu_probe_speed(struct cpu_info *); 69 static void cpu_idlespin(void); 70 static void cpu_set_dfs_xcall(void *, void *); 71 #if NSYSMON_ENVSYS > 0 72 static void cpu_tau_setup(struct cpu_info *); 73 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 74 #endif 75 76 int cpu = -1; 77 int ncpus; 78 79 struct fmttab { 80 register_t fmt_mask; 81 register_t fmt_value; 82 const char *fmt_string; 83 }; 84 85 /* 86 * This should be one per CPU but since we only support it on 750 variants it 87 * doesn't really matter since none of them support SMP 88 */ 89 envsys_data_t sensor; 90 91 static const struct fmttab cpu_7450_l2cr_formats[] = { 92 { L2CR_L2E, 0, " disabled" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 96 { L2CR_L2E, ~0, " 256KB L2 cache" }, 97 { L2CR_L2PE, 0, " no parity" }, 98 { L2CR_L2PE, ~0, " parity enabled" }, 99 { 0, 0, NULL } 100 }; 101 102 static const struct fmttab cpu_7448_l2cr_formats[] = { 103 { L2CR_L2E, 0, " disabled" }, 104 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 107 { L2CR_L2E, ~0, " 1MB L2 cache" }, 108 { L2CR_L2PE, 0, " no parity" }, 109 { L2CR_L2PE, ~0, " parity enabled" }, 110 { 0, 0, NULL } 111 }; 112 113 static const struct fmttab cpu_7457_l2cr_formats[] = { 114 { L2CR_L2E, 0, " disabled" }, 115 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 116 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 117 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 118 { L2CR_L2E, ~0, " 512KB L2 cache" }, 119 { L2CR_L2PE, 0, " no parity" }, 120 { L2CR_L2PE, ~0, " parity enabled" }, 121 { 0, 0, NULL } 122 }; 123 124 static const struct fmttab cpu_7450_l3cr_formats[] = { 125 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 126 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 127 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 128 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 129 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 130 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 131 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 132 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 133 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 134 { L3CR_L3SIZ, ~0, " L3 cache" }, 135 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 136 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 137 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 138 { L3CR_L3CLK, ~0, " at" }, 139 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 140 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 141 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 142 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 143 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 144 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 145 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 146 { L3CR_L3CLK, ~0, " ratio" }, 147 { 0, 0, NULL }, 148 }; 149 150 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 151 { L2CR_L2E, 0, " disabled" }, 152 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 153 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 154 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 155 { 0, ~0, " 512KB" }, 156 { L2CR_L2WT, L2CR_L2WT, " WT" }, 157 { L2CR_L2WT, 0, " WB" }, 158 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 159 { 0, ~0, " L2 cache" }, 160 { 0, 0, NULL } 161 }; 162 163 static const struct fmttab cpu_l2cr_formats[] = { 164 { L2CR_L2E, 0, " disabled" }, 165 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 166 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 167 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 168 { L2CR_L2PE, L2CR_L2PE, " parity" }, 169 { L2CR_L2PE, 0, " no-parity" }, 170 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 171 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 172 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 173 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 174 { L2CR_L2WT, L2CR_L2WT, " WT" }, 175 { L2CR_L2WT, 0, " WB" }, 176 { L2CR_L2E, ~0, " L2 cache" }, 177 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 178 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 179 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 180 { L2CR_L2CLK, ~0, " at" }, 181 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 182 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 183 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 184 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 185 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 186 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 187 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 188 { L2CR_L2CLK, ~0, " ratio" }, 189 { 0, 0, NULL } 190 }; 191 192 static void cpu_fmttab_print(const struct fmttab *, register_t); 193 194 struct cputab { 195 const char name[8]; 196 uint16_t version; 197 uint16_t revfmt; 198 }; 199 #define REVFMT_MAJMIN 1 /* %u.%u */ 200 #define REVFMT_HEX 2 /* 0x%04x */ 201 #define REVFMT_DEC 3 /* %u */ 202 static const struct cputab models[] = { 203 { "601", MPC601, REVFMT_DEC }, 204 { "602", MPC602, REVFMT_DEC }, 205 { "603", MPC603, REVFMT_MAJMIN }, 206 { "603e", MPC603e, REVFMT_MAJMIN }, 207 { "603ev", MPC603ev, REVFMT_MAJMIN }, 208 { "G2", MPCG2, REVFMT_MAJMIN }, 209 { "604", MPC604, REVFMT_MAJMIN }, 210 { "604e", MPC604e, REVFMT_MAJMIN }, 211 { "604ev", MPC604ev, REVFMT_MAJMIN }, 212 { "620", MPC620, REVFMT_HEX }, 213 { "750", MPC750, REVFMT_MAJMIN }, 214 { "750FX", IBM750FX, REVFMT_MAJMIN }, 215 { "750GX", IBM750GX, REVFMT_MAJMIN }, 216 { "7400", MPC7400, REVFMT_MAJMIN }, 217 { "7410", MPC7410, REVFMT_MAJMIN }, 218 { "7450", MPC7450, REVFMT_MAJMIN }, 219 { "7455", MPC7455, REVFMT_MAJMIN }, 220 { "7457", MPC7457, REVFMT_MAJMIN }, 221 { "7447A", MPC7447A, REVFMT_MAJMIN }, 222 { "7448", MPC7448, REVFMT_MAJMIN }, 223 { "8240", MPC8240, REVFMT_MAJMIN }, 224 { "8245", MPC8245, REVFMT_MAJMIN }, 225 { "970", IBM970, REVFMT_MAJMIN }, 226 { "970FX", IBM970FX, REVFMT_MAJMIN }, 227 { "970MP", IBM970MP, REVFMT_MAJMIN }, 228 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 229 { "", 0, REVFMT_HEX } 230 }; 231 232 #ifdef MULTIPROCESSOR 233 struct cpu_info cpu_info[CPU_MAXNUM] = { 234 [0] = { 235 .ci_curlwp = &lwp0, 236 }, 237 }; 238 volatile struct cpu_hatch_data *cpu_hatch_data; 239 volatile int cpu_hatch_stack; 240 #define HATCH_STACK_SIZE 0x1000 241 extern int ticks_per_intr; 242 #include <powerpc/oea/bat.h> 243 #include <powerpc/pic/picvar.h> 244 #include <powerpc/pic/ipivar.h> 245 extern struct bat battable[]; 246 #else 247 struct cpu_info cpu_info[1] = { 248 [0] = { 249 .ci_curlwp = &lwp0, 250 }, 251 }; 252 #endif /*MULTIPROCESSOR*/ 253 254 int cpu_altivec; 255 register_t cpu_psluserset; 256 register_t cpu_pslusermod; 257 register_t cpu_pslusermask = 0xffff; 258 259 /* This is to be called from locore.S, and nowhere else. */ 260 261 void 262 cpu_model_init(void) 263 { 264 u_int pvr, vers; 265 266 pvr = mfpvr(); 267 vers = pvr >> 16; 268 269 oeacpufeat = 0; 270 271 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 272 vers == IBMCELL || vers == IBMPOWER6P5) { 273 oeacpufeat |= OEACPU_64; 274 oeacpufeat |= OEACPU_64_BRIDGE; 275 oeacpufeat |= OEACPU_NOBAT; 276 277 } else if (vers == MPC601) { 278 oeacpufeat |= OEACPU_601; 279 280 } else if (MPC745X_P(vers)) { 281 register_t hid1 = mfspr(SPR_HID1); 282 283 if (vers != MPC7450) { 284 register_t hid0 = mfspr(SPR_HID0); 285 286 /* Enable more SPRG registers */ 287 oeacpufeat |= OEACPU_HIGHSPRG; 288 289 /* Enable more BAT registers */ 290 oeacpufeat |= OEACPU_HIGHBAT; 291 hid0 |= HID0_HIGH_BAT_EN; 292 293 /* Enable larger BAT registers */ 294 oeacpufeat |= OEACPU_XBSEN; 295 hid0 |= HID0_XBSEN; 296 297 mtspr(SPR_HID0, hid0); 298 __asm volatile("sync;isync"); 299 } 300 301 /* Enable address broadcasting for MP systems */ 302 hid1 |= HID1_SYNCBE | HID1_ABE; 303 304 mtspr(SPR_HID1, hid1); 305 __asm volatile("sync;isync"); 306 307 } else if (vers == IBM750FX || vers == IBM750GX) { 308 oeacpufeat |= OEACPU_HIGHBAT; 309 } 310 } 311 312 void 313 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 314 { 315 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 316 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 317 (data & fmt->fmt_mask) == fmt->fmt_value) 318 aprint_normal("%s", fmt->fmt_string); 319 } 320 } 321 322 void 323 cpu_idlespin(void) 324 { 325 register_t msr; 326 327 if (powersave <= 0) 328 return; 329 330 __asm volatile( 331 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 332 "dssall;" 333 #endif 334 "sync;" 335 "mfmsr %0;" 336 "oris %0,%0,%1@h;" /* enter power saving mode */ 337 "mtmsr %0;" 338 "isync;" 339 : "=r"(msr) 340 : "J"(PSL_POW)); 341 } 342 343 void 344 cpu_probe_cache(void) 345 { 346 u_int assoc, pvr, vers; 347 348 pvr = mfpvr(); 349 vers = pvr >> 16; 350 351 352 /* Presently common across almost all implementations. */ 353 curcpu()->ci_ci.dcache_line_size = 32; 354 curcpu()->ci_ci.icache_line_size = 32; 355 356 357 switch (vers) { 358 #define K *1024 359 case IBM750FX: 360 case IBM750GX: 361 case MPC601: 362 case MPC750: 363 case MPC7400: 364 case MPC7447A: 365 case MPC7448: 366 case MPC7450: 367 case MPC7455: 368 case MPC7457: 369 curcpu()->ci_ci.dcache_size = 32 K; 370 curcpu()->ci_ci.icache_size = 32 K; 371 assoc = 8; 372 break; 373 case MPC603: 374 curcpu()->ci_ci.dcache_size = 8 K; 375 curcpu()->ci_ci.icache_size = 8 K; 376 assoc = 2; 377 break; 378 case MPC603e: 379 case MPC603ev: 380 case MPC604: 381 case MPC8240: 382 case MPC8245: 383 case MPCG2: 384 curcpu()->ci_ci.dcache_size = 16 K; 385 curcpu()->ci_ci.icache_size = 16 K; 386 assoc = 4; 387 break; 388 case MPC604e: 389 case MPC604ev: 390 curcpu()->ci_ci.dcache_size = 32 K; 391 curcpu()->ci_ci.icache_size = 32 K; 392 assoc = 4; 393 break; 394 case IBMPOWER3II: 395 curcpu()->ci_ci.dcache_size = 64 K; 396 curcpu()->ci_ci.icache_size = 32 K; 397 curcpu()->ci_ci.dcache_line_size = 128; 398 curcpu()->ci_ci.icache_line_size = 128; 399 assoc = 128; /* not a typo */ 400 break; 401 case IBM970: 402 case IBM970FX: 403 case IBM970MP: 404 curcpu()->ci_ci.dcache_size = 32 K; 405 curcpu()->ci_ci.icache_size = 64 K; 406 curcpu()->ci_ci.dcache_line_size = 128; 407 curcpu()->ci_ci.icache_line_size = 128; 408 assoc = 2; 409 break; 410 411 default: 412 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 413 curcpu()->ci_ci.icache_size = PAGE_SIZE; 414 assoc = 1; 415 #undef K 416 } 417 418 /* 419 * Possibly recolor. 420 */ 421 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 422 } 423 424 struct cpu_info * 425 cpu_attach_common(device_t self, int id) 426 { 427 struct cpu_info *ci; 428 u_int pvr, vers; 429 430 ci = &cpu_info[id]; 431 #ifndef MULTIPROCESSOR 432 /* 433 * If this isn't the primary CPU, print an error message 434 * and just bail out. 435 */ 436 if (id != 0) { 437 aprint_naive("\n"); 438 aprint_normal(": ID %d\n", id); 439 aprint_normal_dev(self, 440 "processor off-line; " 441 "multiprocessor support not present in kernel\n"); 442 return (NULL); 443 } 444 #endif 445 446 ci->ci_cpuid = id; 447 ci->ci_idepth = -1; 448 ci->ci_dev = self; 449 ci->ci_idlespin = cpu_idlespin; 450 451 pvr = mfpvr(); 452 vers = (pvr >> 16) & 0xffff; 453 454 switch (id) { 455 case 0: 456 /* load my cpu_number to PIR */ 457 switch (vers) { 458 case MPC601: 459 case MPC604: 460 case MPC604e: 461 case MPC604ev: 462 case MPC7400: 463 case MPC7410: 464 case MPC7447A: 465 case MPC7448: 466 case MPC7450: 467 case MPC7455: 468 case MPC7457: 469 mtspr(SPR_PIR, id); 470 } 471 cpu_setup(self, ci); 472 break; 473 default: 474 aprint_naive("\n"); 475 if (id >= CPU_MAXNUM) { 476 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 477 panic("cpuattach"); 478 } 479 #ifndef MULTIPROCESSOR 480 aprint_normal(" not configured\n"); 481 return NULL; 482 #else 483 mi_cpu_attach(ci); 484 break; 485 #endif 486 } 487 return (ci); 488 } 489 490 void 491 cpu_setup(device_t self, struct cpu_info *ci) 492 { 493 u_int pvr, vers; 494 const char * const xname = device_xname(self); 495 const char *bitmask; 496 char hidbuf[128]; 497 char model[80]; 498 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 499 char hidbuf_u[128]; 500 const char *bitmasku = NULL; 501 volatile uint64_t hid64_0, hid64_0_save; 502 #endif 503 #if !defined(_ARCH_PPC64) 504 register_t hid0 = 0, hid0_save = 0; 505 #endif 506 507 pvr = mfpvr(); 508 vers = (pvr >> 16) & 0xffff; 509 510 cpu_identify(model, sizeof(model)); 511 aprint_naive("\n"); 512 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 513 cpu_number() == 0 ? " (primary)" : ""); 514 515 /* set the cpu number */ 516 ci->ci_cpuid = cpu_number(); 517 #if defined(_ARCH_PPC64) 518 __asm volatile("mfspr %0,%1" : "=r"(hid64_0) : "K"(SPR_HID0)); 519 hid64_0_save = hid64_0; 520 #else 521 #if defined(PPC_OEA64_BRIDGE) 522 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) 523 hid64_0_save = hid64_0 = mfspr(SPR_HID0); 524 else 525 #endif 526 hid0_save = hid0 = mfspr(SPR_HID0); 527 #endif 528 529 530 cpu_probe_cache(); 531 532 /* 533 * Configure power-saving mode. 534 */ 535 switch (vers) { 536 #if !defined(_ARCH_PPC64) 537 case MPC604: 538 case MPC604e: 539 case MPC604ev: 540 /* 541 * Do not have HID0 support settings, but can support 542 * MSR[POW] off 543 */ 544 powersave = 1; 545 break; 546 547 case MPC603: 548 case MPC603e: 549 case MPC603ev: 550 case MPC7400: 551 case MPC7410: 552 case MPC8240: 553 case MPC8245: 554 case MPCG2: 555 /* Select DOZE mode. */ 556 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 557 hid0 |= HID0_DOZE | HID0_DPM; 558 powersave = 1; 559 break; 560 561 case MPC750: 562 case IBM750FX: 563 case IBM750GX: 564 /* Select NAP mode. */ 565 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 566 hid0 |= HID0_NAP | HID0_DPM; 567 powersave = 1; 568 break; 569 570 case MPC7447A: 571 case MPC7448: 572 case MPC7457: 573 case MPC7455: 574 case MPC7450: 575 /* Enable the 7450 branch caches */ 576 hid0 |= HID0_SGE | HID0_BTIC; 577 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 578 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 579 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 580 hid0 &= ~HID0_BTIC; 581 /* Select NAP mode. */ 582 hid0 &= ~HID0_SLEEP; 583 hid0 |= HID0_NAP | HID0_DPM; 584 powersave = 1; 585 break; 586 #endif 587 588 case IBM970: 589 case IBM970FX: 590 case IBM970MP: 591 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 592 #if !defined(_ARCH_PPC64) 593 KASSERT((oeacpufeat & OEACPU_64_BRIDGE) != 0); 594 #endif 595 hid64_0 &= ~(HID0_64_DOZE | HID0_64_NAP | HID0_64_DEEPNAP); 596 hid64_0 |= HID0_64_NAP | HID0_64_DPM | HID0_64_EX_TBEN | 597 HID0_64_TB_CTRL | HID0_64_EN_MCHK; 598 powersave = 1; 599 break; 600 #endif 601 case IBMPOWER3II: 602 default: 603 /* No power-saving mode is available. */ ; 604 } 605 606 #ifdef NAPMODE 607 switch (vers) { 608 case IBM750FX: 609 case IBM750GX: 610 case MPC750: 611 case MPC7400: 612 /* Select NAP mode. */ 613 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 614 hid0 |= HID0_NAP; 615 break; 616 } 617 #endif 618 619 switch (vers) { 620 case IBM750FX: 621 case IBM750GX: 622 case MPC750: 623 hid0 &= ~HID0_DBP; /* XXX correct? */ 624 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 625 break; 626 627 case MPC7400: 628 case MPC7410: 629 hid0 &= ~HID0_SPD; 630 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 631 hid0 |= HID0_EIEC; 632 break; 633 } 634 635 /* 636 * according to the 603e manual this is necessary for an external L2 637 * cache to work properly 638 */ 639 switch (vers) { 640 case MPC603e: 641 hid0 |= HID0_ABE; 642 } 643 644 #if defined(_ARCH_PPC64) || defined(PPC_OEA64_BRIDGE) 645 #if defined(PPC_OEA64_BRIDGE) 646 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 647 #endif 648 if (hid64_0 != hid64_0_save) { 649 mtspr64(SPR_HID0, hid64_0); 650 } 651 #if defined(PPC_OEA64_BRIDGE) 652 } else { 653 #endif 654 #endif 655 656 #if !defined(_ARCH_PPC64) 657 if (hid0 != hid0_save) { 658 mtspr(SPR_HID0, hid0); 659 __asm volatile("sync;isync"); 660 } 661 #endif 662 #if defined(PPC_OEA64_BRIDGE) 663 } 664 #endif 665 666 switch (vers) { 667 case MPC601: 668 bitmask = HID0_601_BITMASK; 669 break; 670 case MPC7447A: 671 case MPC7448: 672 case MPC7450: 673 case MPC7455: 674 case MPC7457: 675 bitmask = HID0_7450_BITMASK; 676 break; 677 case IBM970: 678 case IBM970FX: 679 case IBM970MP: 680 bitmask = HID0_970_BITMASK; 681 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 682 bitmasku = HID0_970_BITMASK_U; 683 #endif 684 break; 685 default: 686 bitmask = HID0_BITMASK; 687 break; 688 } 689 690 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 691 if (bitmasku != NULL) { 692 snprintb(hidbuf, sizeof hidbuf, bitmask, hid64_0 & 0xffffffff); 693 snprintb(hidbuf_u, sizeof hidbuf_u, bitmasku, hid64_0 >> 32); 694 aprint_normal_dev(self, "HID0 %s %s, powersave: %d\n", 695 hidbuf_u, hidbuf, powersave); 696 } else 697 #endif 698 { 699 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 700 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", 701 hidbuf, powersave); 702 } 703 704 ci->ci_khz = 0; 705 706 /* 707 * Display speed and cache configuration. 708 */ 709 switch (vers) { 710 case MPC604: 711 case MPC604e: 712 case MPC604ev: 713 case MPC750: 714 case IBM750FX: 715 case IBM750GX: 716 case MPC7400: 717 case MPC7410: 718 case MPC7447A: 719 case MPC7448: 720 case MPC7450: 721 case MPC7455: 722 case MPC7457: 723 aprint_normal_dev(self, ""); 724 cpu_probe_speed(ci); 725 aprint_normal("%u.%02u MHz", 726 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 727 switch (vers) { 728 case MPC7450: /* 7441 does not have L3! */ 729 case MPC7455: /* 7445 does not have L3! */ 730 case MPC7457: /* 7447 does not have L3! */ 731 cpu_config_l3cr(vers); 732 break; 733 case IBM750FX: 734 case IBM750GX: 735 case MPC750: 736 case MPC7400: 737 case MPC7410: 738 case MPC7447A: 739 case MPC7448: 740 cpu_config_l2cr(pvr); 741 break; 742 default: 743 break; 744 } 745 aprint_normal("\n"); 746 break; 747 } 748 749 #if NSYSMON_ENVSYS > 0 750 /* 751 * Attach MPC750 temperature sensor to the envsys subsystem. 752 * XXX the 74xx series also has this sensor, but it is not 753 * XXX supported by Motorola and may return values that are off by 754 * XXX 35-55 degrees C. 755 */ 756 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 757 cpu_tau_setup(ci); 758 #endif 759 760 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 761 NULL, xname, "clock"); 762 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 763 NULL, xname, "traps"); 764 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 765 &ci->ci_ev_traps, xname, "kernel DSI traps"); 766 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 767 &ci->ci_ev_traps, xname, "user DSI traps"); 768 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 769 &ci->ci_ev_udsi, xname, "user DSI failures"); 770 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 771 &ci->ci_ev_traps, xname, "kernel ISI traps"); 772 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 773 &ci->ci_ev_traps, xname, "user ISI traps"); 774 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 775 &ci->ci_ev_isi, xname, "user ISI failures"); 776 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 777 &ci->ci_ev_traps, xname, "system call traps"); 778 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 779 &ci->ci_ev_traps, xname, "PGM traps"); 780 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 781 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 782 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 783 &ci->ci_ev_fpu, xname, "FPU context switches"); 784 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 785 &ci->ci_ev_traps, xname, "user alignment traps"); 786 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 787 &ci->ci_ev_ali, xname, "user alignment traps"); 788 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 789 &ci->ci_ev_umchk, xname, "user MCHK failures"); 790 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 791 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 792 #ifdef ALTIVEC 793 if (cpu_altivec) { 794 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 795 &ci->ci_ev_vec, xname, "AltiVec context switches"); 796 } 797 #endif 798 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 799 NULL, xname, "IPIs"); 800 } 801 802 /* 803 * According to a document labeled "PVR Register Settings": 804 ** For integrated microprocessors the PVR register inside the device 805 ** will identify the version of the microprocessor core. You must also 806 ** read the Device ID, PCI register 02, to identify the part and the 807 ** Revision ID, PCI register 08, to identify the revision of the 808 ** integrated microprocessor. 809 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 810 */ 811 812 void 813 cpu_identify(char *str, size_t len) 814 { 815 u_int pvr, major, minor; 816 uint16_t vers, rev, revfmt; 817 const struct cputab *cp; 818 size_t n; 819 820 pvr = mfpvr(); 821 vers = pvr >> 16; 822 rev = pvr; 823 824 switch (vers) { 825 case MPC7410: 826 minor = (pvr >> 0) & 0xff; 827 major = minor <= 4 ? 1 : 2; 828 break; 829 case MPCG2: /*XXX see note above */ 830 major = (pvr >> 4) & 0xf; 831 minor = (pvr >> 0) & 0xf; 832 break; 833 default: 834 major = (pvr >> 8) & 0xf; 835 minor = (pvr >> 0) & 0xf; 836 } 837 838 for (cp = models; cp->name[0] != '\0'; cp++) { 839 if (cp->version == vers) 840 break; 841 } 842 843 if (cpu == -1) 844 cpu = vers; 845 846 revfmt = cp->revfmt; 847 if (rev == MPC750 && pvr == 15) { 848 revfmt = REVFMT_HEX; 849 } 850 851 if (cp->name[0] != '\0') { 852 n = snprintf(str, len, "%s (Revision ", cp->name); 853 } else { 854 n = snprintf(str, len, "Version %#x (Revision ", vers); 855 } 856 if (len > n) { 857 switch (revfmt) { 858 case REVFMT_MAJMIN: 859 snprintf(str + n, len - n, "%u.%u)", major, minor); 860 break; 861 case REVFMT_HEX: 862 snprintf(str + n, len - n, "0x%04x)", rev); 863 break; 864 case REVFMT_DEC: 865 snprintf(str + n, len - n, "%u)", rev); 866 break; 867 } 868 } 869 } 870 871 #ifdef L2CR_CONFIG 872 u_int l2cr_config = L2CR_CONFIG; 873 #else 874 u_int l2cr_config = 0; 875 #endif 876 877 #ifdef L3CR_CONFIG 878 u_int l3cr_config = L3CR_CONFIG; 879 #else 880 u_int l3cr_config = 0; 881 #endif 882 883 void 884 cpu_enable_l2cr(register_t l2cr) 885 { 886 register_t msr, x; 887 uint16_t vers; 888 889 vers = mfpvr() >> 16; 890 891 /* Disable interrupts and set the cache config bits. */ 892 msr = mfmsr(); 893 mtmsr(msr & ~PSL_EE); 894 #ifdef ALTIVEC 895 if (cpu_altivec) 896 __asm volatile("dssall"); 897 #endif 898 __asm volatile("sync"); 899 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 900 __asm volatile("sync"); 901 902 /* Wait for L2 clock to be stable (640 L2 clocks). */ 903 delay(100); 904 905 /* Invalidate all L2 contents. */ 906 if (MPC745X_P(vers)) { 907 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 908 do { 909 x = mfspr(SPR_L2CR); 910 } while (x & L2CR_L2I); 911 } else { 912 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 913 do { 914 x = mfspr(SPR_L2CR); 915 } while (x & L2CR_L2IP); 916 } 917 /* Enable L2 cache. */ 918 l2cr |= L2CR_L2E; 919 mtspr(SPR_L2CR, l2cr); 920 mtmsr(msr); 921 } 922 923 void 924 cpu_enable_l3cr(register_t l3cr) 925 { 926 register_t x; 927 928 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 929 930 /* 931 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 932 * L3CLKEN. (also mask off reserved bits in case they were included 933 * in L3CR_CONFIG) 934 */ 935 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 936 mtspr(SPR_L3CR, l3cr); 937 938 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 939 l3cr |= 0x04000000; 940 mtspr(SPR_L3CR, l3cr); 941 942 /* 3: Set L3CLKEN to 1*/ 943 l3cr |= L3CR_L3CLKEN; 944 mtspr(SPR_L3CR, l3cr); 945 946 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 947 __asm volatile("dssall;sync"); 948 /* L3 cache is already disabled, no need to clear L3E */ 949 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 950 do { 951 x = mfspr(SPR_L3CR); 952 } while (x & L3CR_L3I); 953 954 /* 6: Clear L3CLKEN to 0 */ 955 l3cr &= ~L3CR_L3CLKEN; 956 mtspr(SPR_L3CR, l3cr); 957 958 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 959 __asm volatile("sync"); 960 delay(100); 961 962 /* 8: Set L3E and L3CLKEN */ 963 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 964 mtspr(SPR_L3CR, l3cr); 965 966 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 967 __asm volatile("sync"); 968 delay(100); 969 } 970 971 void 972 cpu_config_l2cr(int pvr) 973 { 974 register_t l2cr; 975 u_int vers = (pvr >> 16) & 0xffff; 976 977 l2cr = mfspr(SPR_L2CR); 978 979 /* 980 * For MP systems, the firmware may only configure the L2 cache 981 * on the first CPU. In this case, assume that the other CPUs 982 * should use the same value for L2CR. 983 */ 984 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 985 l2cr_config = l2cr; 986 } 987 988 /* 989 * Configure L2 cache if not enabled. 990 */ 991 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 992 cpu_enable_l2cr(l2cr_config); 993 l2cr = mfspr(SPR_L2CR); 994 } 995 996 if ((l2cr & L2CR_L2E) == 0) { 997 aprint_normal(" L2 cache present but not enabled "); 998 return; 999 } 1000 aprint_normal(","); 1001 1002 switch (vers) { 1003 case IBM750FX: 1004 case IBM750GX: 1005 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1006 break; 1007 case MPC750: 1008 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 1009 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 1010 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1011 else 1012 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1013 break; 1014 case MPC7447A: 1015 case MPC7457: 1016 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1017 return; 1018 case MPC7448: 1019 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1020 return; 1021 case MPC7450: 1022 case MPC7455: 1023 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1024 break; 1025 default: 1026 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1027 break; 1028 } 1029 } 1030 1031 void 1032 cpu_config_l3cr(int vers) 1033 { 1034 register_t l2cr; 1035 register_t l3cr; 1036 1037 l2cr = mfspr(SPR_L2CR); 1038 1039 /* 1040 * For MP systems, the firmware may only configure the L2 cache 1041 * on the first CPU. In this case, assume that the other CPUs 1042 * should use the same value for L2CR. 1043 */ 1044 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1045 l2cr_config = l2cr; 1046 } 1047 1048 /* 1049 * Configure L2 cache if not enabled. 1050 */ 1051 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1052 cpu_enable_l2cr(l2cr_config); 1053 l2cr = mfspr(SPR_L2CR); 1054 } 1055 1056 aprint_normal(","); 1057 switch (vers) { 1058 case MPC7447A: 1059 case MPC7457: 1060 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1061 return; 1062 case MPC7448: 1063 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1064 return; 1065 default: 1066 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1067 break; 1068 } 1069 1070 l3cr = mfspr(SPR_L3CR); 1071 1072 /* 1073 * For MP systems, the firmware may only configure the L3 cache 1074 * on the first CPU. In this case, assume that the other CPUs 1075 * should use the same value for L3CR. 1076 */ 1077 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 1078 l3cr_config = l3cr; 1079 } 1080 1081 /* 1082 * Configure L3 cache if not enabled. 1083 */ 1084 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1085 cpu_enable_l3cr(l3cr_config); 1086 l3cr = mfspr(SPR_L3CR); 1087 } 1088 1089 if (l3cr & L3CR_L3E) { 1090 aprint_normal(","); 1091 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1092 } 1093 } 1094 1095 void 1096 cpu_probe_speed(struct cpu_info *ci) 1097 { 1098 uint64_t cps; 1099 1100 mtspr(SPR_MMCR0, MMCR0_FC); 1101 mtspr(SPR_PMC1, 0); 1102 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1103 delay(100000); 1104 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1105 1106 mtspr(SPR_MMCR0, MMCR0_FC); 1107 1108 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1109 } 1110 1111 /* 1112 * Read the Dynamic Frequency Switching state and return a divisor for 1113 * the maximum frequency. 1114 */ 1115 int 1116 cpu_get_dfs(void) 1117 { 1118 u_int pvr, vers; 1119 1120 pvr = mfpvr(); 1121 vers = pvr >> 16; 1122 1123 switch (vers) { 1124 case MPC7448: 1125 if (mfspr(SPR_HID1) & HID1_DFS4) 1126 return 4; 1127 case MPC7447A: 1128 if (mfspr(SPR_HID1) & HID1_DFS2) 1129 return 2; 1130 } 1131 return 1; 1132 } 1133 1134 /* 1135 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1136 */ 1137 void 1138 cpu_set_dfs(int div) 1139 { 1140 uint64_t where; 1141 u_int dfs_mask, pvr, vers; 1142 1143 pvr = mfpvr(); 1144 vers = pvr >> 16; 1145 dfs_mask = 0; 1146 1147 switch (vers) { 1148 case MPC7448: 1149 dfs_mask |= HID1_DFS4; 1150 case MPC7447A: 1151 dfs_mask |= HID1_DFS2; 1152 break; 1153 default: 1154 printf("cpu_set_dfs: DFS not supported\n"); 1155 return; 1156 1157 } 1158 1159 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1160 xc_wait(where); 1161 } 1162 1163 static void 1164 cpu_set_dfs_xcall(void *arg1, void *arg2) 1165 { 1166 u_int dfs_mask, hid1, old_hid1; 1167 int *divisor, s; 1168 1169 divisor = arg1; 1170 dfs_mask = *(u_int *)arg2; 1171 1172 s = splhigh(); 1173 hid1 = old_hid1 = mfspr(SPR_HID1); 1174 1175 switch (*divisor) { 1176 case 1: 1177 hid1 &= ~dfs_mask; 1178 break; 1179 case 2: 1180 hid1 &= ~(dfs_mask & HID1_DFS4); 1181 hid1 |= dfs_mask & HID1_DFS2; 1182 break; 1183 case 4: 1184 hid1 &= ~(dfs_mask & HID1_DFS2); 1185 hid1 |= dfs_mask & HID1_DFS4; 1186 break; 1187 } 1188 1189 if (hid1 != old_hid1) { 1190 __asm volatile("sync"); 1191 mtspr(SPR_HID1, hid1); 1192 __asm volatile("sync;isync"); 1193 } 1194 1195 splx(s); 1196 } 1197 1198 #if NSYSMON_ENVSYS > 0 1199 void 1200 cpu_tau_setup(struct cpu_info *ci) 1201 { 1202 struct sysmon_envsys *sme; 1203 int error, therm_delay; 1204 1205 mtspr(SPR_THRM1, SPR_THRM_VALID); 1206 mtspr(SPR_THRM2, 0); 1207 1208 /* 1209 * we need to figure out how much 20+us in units of CPU clock cycles 1210 * are 1211 */ 1212 1213 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1214 1215 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1216 1217 sme = sysmon_envsys_create(); 1218 1219 sensor.units = ENVSYS_STEMP; 1220 sensor.state = ENVSYS_SINVALID; 1221 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1222 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1223 sysmon_envsys_destroy(sme); 1224 return; 1225 } 1226 1227 sme->sme_name = device_xname(ci->ci_dev); 1228 sme->sme_cookie = ci; 1229 sme->sme_refresh = cpu_tau_refresh; 1230 1231 if ((error = sysmon_envsys_register(sme)) != 0) { 1232 aprint_error_dev(ci->ci_dev, 1233 " unable to register with sysmon (%d)\n", error); 1234 sysmon_envsys_destroy(sme); 1235 } 1236 } 1237 1238 /* Find the temperature of the CPU. */ 1239 void 1240 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1241 { 1242 int i, threshold, count; 1243 1244 threshold = 64; /* Half of the 7-bit sensor range */ 1245 1246 /* Successive-approximation code adapted from Motorola 1247 * application note AN1800/D, "Programming the Thermal Assist 1248 * Unit in the MPC750 Microprocessor". 1249 */ 1250 for (i = 5; i >= 0 ; i--) { 1251 mtspr(SPR_THRM1, 1252 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1253 count = 0; 1254 while ((count < 100000) && 1255 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1256 count++; 1257 delay(1); 1258 } 1259 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1260 /* The interrupt bit was set, meaning the 1261 * temperature was above the threshold 1262 */ 1263 threshold += 1 << i; 1264 } else { 1265 /* Temperature was below the threshold */ 1266 threshold -= 1 << i; 1267 } 1268 } 1269 threshold += 2; 1270 1271 /* Convert the temperature in degrees C to microkelvin */ 1272 edata->value_cur = (threshold * 1000000) + 273150000; 1273 edata->state = ENVSYS_SVALID; 1274 } 1275 #endif /* NSYSMON_ENVSYS > 0 */ 1276 1277 #ifdef MULTIPROCESSOR 1278 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1279 1280 int 1281 cpu_spinup(device_t self, struct cpu_info *ci) 1282 { 1283 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1284 struct pglist mlist; 1285 int i, error; 1286 char *hp; 1287 1288 KASSERT(ci != curcpu()); 1289 1290 /* Now allocate a hatch stack */ 1291 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1292 &mlist, 1, 1); 1293 if (error) { 1294 aprint_error(": unable to allocate hatch stack\n"); 1295 return -1; 1296 } 1297 1298 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1299 memset(hp, 0, HATCH_STACK_SIZE); 1300 1301 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1302 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1303 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1304 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1305 1306 cpu_hatch_data = h; 1307 h->hatch_running = 0; 1308 h->hatch_self = self; 1309 h->hatch_ci = ci; 1310 h->hatch_pir = ci->ci_cpuid; 1311 1312 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1313 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1314 1315 /* copy special registers */ 1316 1317 h->hatch_hid0 = mfspr(SPR_HID0); 1318 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 1319 h->hatch_hid4 = mfspr(SPR_HID4); 1320 h->hatch_hid5 = mfspr(SPR_HID5); 1321 printf("HIDs: %016llx %016llx\n", h->hatch_hid4, h->hatch_hid5); 1322 #endif 1323 1324 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1325 for (i = 0; i < 16; i++) { 1326 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1327 "r"(i << ADDR_SR_SHFT)); 1328 } 1329 if (oeacpufeat & OEACPU_64) 1330 h->hatch_asr = mfspr(SPR_ASR); 1331 else 1332 h->hatch_asr = 0; 1333 1334 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1335 /* copy the bat regs */ 1336 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1337 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1338 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1339 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1340 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1341 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1342 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1343 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1344 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1345 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1346 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1347 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1348 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1349 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1350 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1351 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1352 __asm volatile ("sync; isync"); 1353 } 1354 1355 if (md_setup_trampoline(h, ci) == -1) 1356 return -1; 1357 md_presync_timebase(h); 1358 md_start_timebase(h); 1359 1360 /* wait for secondary printf */ 1361 1362 delay(200000); 1363 1364 #ifdef CACHE_PROTO_MEI 1365 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1366 __asm volatile ("sync; isync"); 1367 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1368 __asm volatile ("sync; isync"); 1369 #endif 1370 if (h->hatch_running < 1) { 1371 #ifdef CACHE_PROTO_MEI 1372 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1373 __asm volatile ("sync; isync"); 1374 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1375 __asm volatile ("sync; isync"); 1376 #endif 1377 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1378 ci->ci_cpuid, cpu_spinstart_ack); 1379 Debugger(); 1380 return -1; 1381 } 1382 1383 /* Register IPI Interrupt */ 1384 if (ipiops.ppc_establish_ipi) 1385 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1386 1387 return 0; 1388 } 1389 1390 static volatile int start_secondary_cpu; 1391 1392 register_t 1393 cpu_hatch(void) 1394 { 1395 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1396 struct cpu_info * const ci = h->hatch_ci; 1397 struct pcb *pcb; 1398 u_int msr; 1399 int i; 1400 1401 /* Initialize timebase. */ 1402 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1403 1404 /* 1405 * Set PIR (Processor Identification Register). i.e. whoami 1406 * Note that PIR is read-only on some CPU versions, so we write to it 1407 * only if it has a different value than we need. 1408 */ 1409 1410 msr = mfspr(SPR_PIR); 1411 if (msr != h->hatch_pir) 1412 mtspr(SPR_PIR, h->hatch_pir); 1413 1414 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1415 curlwp = ci->ci_curlwp; 1416 cpu_spinstart_ack = 0; 1417 1418 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1419 /* Initialize MMU. */ 1420 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1421 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1422 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1423 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1424 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1425 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1426 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1427 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1428 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1429 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1430 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1431 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1432 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1433 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1434 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1435 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1436 } 1437 1438 #ifdef PPC_OEA64_BRIDGE 1439 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 1440 1441 mtspr64(SPR_HID0, h->hatch_hid0); 1442 mtspr64(SPR_HID4, h->hatch_hid4); 1443 mtspr64(SPR_HID5, h->hatch_hid5); 1444 mtspr64(SPR_HIOR, 0); 1445 } else 1446 #endif 1447 mtspr(SPR_HID0, h->hatch_hid0); 1448 1449 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1450 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1451 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1452 } 1453 1454 __asm volatile ("sync"); 1455 for (i = 0; i < 16; i++) 1456 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1457 __asm volatile ("sync; isync"); 1458 1459 if (oeacpufeat & OEACPU_64) 1460 mtspr(SPR_ASR, h->hatch_asr); 1461 1462 cpu_spinstart_ack = 1; 1463 __asm ("ptesync"); 1464 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1465 __asm volatile ("sync; isync"); 1466 1467 cpu_spinstart_ack = 5; 1468 for (i = 0; i < 16; i++) 1469 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1470 "r"(i << ADDR_SR_SHFT)); 1471 1472 /* Enable I/D address translations. */ 1473 msr = mfmsr(); 1474 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1475 mtmsr(msr); 1476 __asm volatile ("sync; isync"); 1477 cpu_spinstart_ack = 2; 1478 1479 md_sync_timebase(h); 1480 1481 cpu_setup(h->hatch_self, ci); 1482 1483 h->hatch_running = 1; 1484 __asm volatile ("sync; isync"); 1485 1486 while (start_secondary_cpu == 0) 1487 ; 1488 1489 __asm volatile ("sync; isync"); 1490 1491 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1492 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1493 1494 md_setup_interrupts(); 1495 1496 ci->ci_ipending = 0; 1497 ci->ci_cpl = 0; 1498 1499 mtmsr(mfmsr() | PSL_EE); 1500 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1501 return pcb->pcb_sp; 1502 } 1503 1504 void 1505 cpu_boot_secondary_processors(void) 1506 { 1507 start_secondary_cpu = 1; 1508 __asm volatile ("sync"); 1509 } 1510 1511 #endif /*MULTIPROCESSOR*/ 1512