1 /* $NetBSD: pic_mpcsoc.c,v 1.9 2022/02/23 21:54:40 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 2007 Michael Lorenz
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: pic_mpcsoc.c,v 1.9 2022/02/23 21:54:40 andvar Exp $");
31
32 #ifdef _KERNEL_OPT
33 #include "opt_interrupt.h"
34 #endif
35
36 #include <sys/param.h>
37 #include <sys/kmem.h>
38 #include <sys/kernel.h>
39
40 #include <uvm/uvm_extern.h>
41
42 #include <machine/pio.h>
43 #include <powerpc/openpic.h>
44
45 #include <powerpc/pic/picvar.h>
46
47 static void mpcpic_enable_irq(struct pic_ops *, int, int);
48 static void mpcpic_disable_irq(struct pic_ops *, int);
49 static void mpcpic_establish_irq(struct pic_ops *, int, int, int);
50 static void mpcpic_finish_setup(struct pic_ops *);
51
52 static u_int steer8245[] = {
53 0x10200, /* external irq 0 direct/serial */
54 0x10220, /* external irq 1 direct/serial */
55 0x10240, /* external irq 2 direct/serial */
56 0x10260, /* external irq 3 direct/serial */
57 0x10280, /* external irq 4 direct/serial */
58 0x102a0, /* external irq 5 serial mode */
59 0x102c0, /* external irq 6 serial mode */
60 0x102e0, /* external irq 7 serial mode */
61 0x10300, /* external irq 8 serial mode */
62 0x10320, /* external irq 9 serial mode */
63 0x10340, /* external irq 10 serial mode */
64 0x10360, /* external irq 11 serial mode */
65 0x10380, /* external irq 12 serial mode */
66 0x103a0, /* external irq 13 serial mode */
67 0x103c0, /* external irq 14 serial mode */
68 0x103e0, /* external irq 15 serial mode */
69 0x11020, /* I2C */
70 0x11040, /* DMA 0 */
71 0x11060, /* DMA 1 */
72 0x110c0, /* MU/I2O */
73 0x01120, /* Timer 0 */
74 0x01160, /* Timer 1 */
75 0x011a0, /* Timer 2 */
76 0x011e0, /* Timer 3 */
77 0x11120, /* DUART 0, MPC8245 */
78 0x11140, /* DUART 1, MPC8245 */
79 };
80 #define MPCPIC_IVEC(n) (steer8245[(n)])
81 #define MPCPIC_IDST(n) (steer8245[(n)] + 0x10)
82
83 static int i8259iswired = 0;
84
85 struct pic_ops *
setup_mpcpic(void * addr)86 setup_mpcpic(void *addr)
87 {
88 struct openpic_ops *ops;
89 struct pic_ops *self;
90 int irq;
91 u_int x;
92
93 openpic_base = addr;
94 ops = kmem_alloc(sizeof(*ops), KM_SLEEP);
95 self = &ops->pic;
96
97 x = openpic_read(OPENPIC_FEATURE);
98 if (((x & 0x07ff0000) >> 16) == 0)
99 panic("setup_mpcpic() called on distributed openpic");
100
101 aprint_normal("OpenPIC Version 1.%d: "
102 "Supports %d CPUs and %d interrupt sources.\n",
103 x & 0xff, ((x & 0x1f00) >> 8) + 1, ((x & 0x07ff0000) >> 16) + 1);
104
105 #ifdef PIC_I8259
106 i8259iswired = 1;
107 #endif
108 self->pic_numintrs = ((x & 0x07ff0000) >> 16) + 1;
109 self->pic_cookie = addr;
110 self->pic_enable_irq = mpcpic_enable_irq;
111 self->pic_reenable_irq = mpcpic_enable_irq;
112 self->pic_disable_irq = mpcpic_disable_irq;
113 self->pic_get_irq = opic_get_irq;
114 self->pic_ack_irq = opic_ack_irq;
115 self->pic_establish_irq = mpcpic_establish_irq;
116 self->pic_finish_setup = mpcpic_finish_setup;
117 ops->isu = NULL;
118 ops->nrofisus = 0; /* internal only */
119 ops->flags = 0; /* no flags (yet) */
120 ops->irq_per = NULL; /* internal ISU only */
121 strcpy(self->pic_name, "mpcpic");
122 pic_add(self);
123
124 openpic_set_priority(0, 15);
125 for (irq = 0; irq < self->pic_numintrs; irq++) {
126 /* make sure to keep disabled */
127 openpic_write(MPCPIC_IVEC(irq), OPENPIC_IMASK);
128 /* send all interrupts to CPU 0 */
129 openpic_write(MPCPIC_IDST(irq), 1 << 0);
130 }
131 openpic_write(OPENPIC_SPURIOUS_VECTOR, 0xff);
132 openpic_set_priority(0, 0);
133
134 /* clear all pending interrupts */
135 for (irq = 0; irq < self->pic_numintrs; irq++) {
136 openpic_read_irq(0);
137 openpic_eoi(0);
138 }
139
140 #if 0
141 printf("timebase freq=%d\n", openpic_read(0x10f0));
142 #endif
143 return self;
144 }
145
146 void
mpcpic_reserv16(void)147 mpcpic_reserv16(void)
148 {
149 extern int max_base; /* intr.c */
150
151 /*
152 * reserve 16 irq slot for the case when no i8259 exists to use.
153 */
154 max_base += 16;
155 }
156
157 static void
mpcpic_establish_irq(struct pic_ops * pic,int irq,int type,int pri)158 mpcpic_establish_irq(struct pic_ops *pic, int irq, int type, int pri)
159 {
160 int realpri = uimax(1, uimin(15, pri));
161 u_int x;
162
163 x = irq;
164 x |= OPENPIC_IMASK;
165
166 if ((i8259iswired && irq == 0) ||
167 type == IST_EDGE_RISING || type == IST_LEVEL_HIGH)
168 x |= OPENPIC_POLARITY_POSITIVE;
169 else
170 x |= OPENPIC_POLARITY_NEGATIVE;
171
172 if (type == IST_EDGE_FALLING || type == IST_EDGE_RISING)
173 x |= OPENPIC_SENSE_EDGE;
174 else
175 x |= OPENPIC_SENSE_LEVEL;
176
177 x |= realpri << OPENPIC_PRIORITY_SHIFT;
178 openpic_write(MPCPIC_IVEC(irq), x);
179
180 aprint_debug("%s: setting IRQ %d to priority %d\n", __func__, irq,
181 realpri);
182 }
183
184 static void
mpcpic_enable_irq(struct pic_ops * pic,int irq,int type)185 mpcpic_enable_irq(struct pic_ops *pic, int irq, int type)
186 {
187 u_int x;
188
189 x = openpic_read(MPCPIC_IVEC(irq));
190 x &= ~OPENPIC_IMASK;
191 openpic_write(MPCPIC_IVEC(irq), x);
192 }
193
194 static void
mpcpic_disable_irq(struct pic_ops * pic,int irq)195 mpcpic_disable_irq(struct pic_ops *pic, int irq)
196 {
197 u_int x;
198
199 x = openpic_read(MPCPIC_IVEC(irq));
200 x |= OPENPIC_IMASK;
201 openpic_write(MPCPIC_IVEC(irq), x);
202 }
203
204 static void
mpcpic_finish_setup(struct pic_ops * pic)205 mpcpic_finish_setup(struct pic_ops *pic)
206 {
207 uint32_t cpumask = 1;
208 int i;
209
210 for (i = 0; i < pic->pic_numintrs; i++) {
211 /* send all interrupts to all active CPUs */
212 openpic_write(MPCPIC_IDST(i), cpumask);
213 }
214 }
215