1 /* $NetBSD: if_mvgbe.c,v 1.66 2022/05/21 10:33:05 rin Exp $ */
2 /*
3 * Copyright (c) 2007, 2008, 2013 KIYOHARA Takashi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.66 2022/05/21 10:33:05 rin Exp $");
29
30 #include "opt_multiprocessor.h"
31
32 #if defined MULTIPROCESSOR
33 #warning Queue Management Method 'Counters' not support. Please use mvxpe instead of this.
34 #endif
35
36 #include <sys/param.h>
37 #include <sys/bus.h>
38 #include <sys/callout.h>
39 #include <sys/device.h>
40 #include <sys/endian.h>
41 #include <sys/errno.h>
42 #include <sys/evcnt.h>
43 #include <sys/kernel.h>
44 #include <sys/kmem.h>
45 #include <sys/mutex.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
48
49 #include <dev/marvell/marvellreg.h>
50 #include <dev/marvell/marvellvar.h>
51 #include <dev/marvell/mvgbereg.h>
52
53 #include <net/if.h>
54 #include <net/if_ether.h>
55 #include <net/if_media.h>
56
57 #include <netinet/in.h>
58 #include <netinet/in_systm.h>
59 #include <netinet/ip.h>
60
61 #include <net/bpf.h>
62 #include <sys/rndsource.h>
63
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
66
67 #include "locators.h"
68
69 /* #define MVGBE_DEBUG 3 */
70 #ifdef MVGBE_DEBUG
71 #define DPRINTF(x) if (mvgbe_debug) printf x
72 #define DPRINTFN(n, x) if (mvgbe_debug >= (n)) printf x
73 int mvgbe_debug = MVGBE_DEBUG;
74 #else
75 #define DPRINTF(x)
76 #define DPRINTFN(n, x)
77 #endif
78
79
80 #define MVGBE_READ(sc, reg) \
81 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
82 #define MVGBE_WRITE(sc, reg, val) \
83 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
84 #define MVGBE_READ_FILTER(sc, reg, val, c) \
85 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c))
86 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \
87 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c))
88
89 #define MVGBE_LINKUP_READ(sc) \
90 bus_space_read_4((sc)->sc_iot, (sc)->sc_linkup.ioh, 0)
91 #define MVGBE_IS_LINKUP(sc) (MVGBE_LINKUP_READ(sc) & (sc)->sc_linkup.bit)
92
93 #define MVGBE_TX_RING_CNT 256
94 #define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1)
95 #define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK)
96 #define MVGBE_RX_RING_CNT 256
97 #define MVGBE_RX_RING_MSK (MVGBE_RX_RING_CNT - 1)
98 #define MVGBE_RX_RING_NEXT(x) (((x) + 1) & MVGBE_RX_RING_MSK)
99
100 CTASSERT(MVGBE_TX_RING_CNT > 1 && MVGBE_TX_RING_NEXT(MVGBE_TX_RING_CNT) ==
101 (MVGBE_TX_RING_CNT + 1) % MVGBE_TX_RING_CNT);
102 CTASSERT(MVGBE_RX_RING_CNT > 1 && MVGBE_RX_RING_NEXT(MVGBE_RX_RING_CNT) ==
103 (MVGBE_RX_RING_CNT + 1) % MVGBE_RX_RING_CNT);
104
105 #define MVGBE_JSLOTS 384 /* XXXX */
106 #define MVGBE_JLEN \
107 ((MVGBE_MRU + MVGBE_HWHEADER_SIZE + MVGBE_RXBUF_ALIGN - 1) & \
108 ~MVGBE_RXBUF_MASK)
109 #define MVGBE_NTXSEG 30
110 #define MVGBE_JPAGESZ PAGE_SIZE
111 #define MVGBE_RESID \
112 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ)
113 #define MVGBE_JMEM \
114 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID)
115
116 #define MVGBE_TX_RING_ADDR(sc, i) \
117 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \
118 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)]))
119
120 #define MVGBE_RX_RING_ADDR(sc, i) \
121 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \
122 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)]))
123
124 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x)
125 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)])
126 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)])
127
128 #define MVGBE_CDTXSYNC(sc, x, n, ops) \
129 do { \
130 int __x, __n; \
131 const int __descsize = sizeof(struct mvgbe_tx_desc); \
132 \
133 __x = (x); \
134 __n = (n); \
135 \
136 /* If it will wrap around, sync to the end of the ring. */ \
137 if ((__x + __n) > MVGBE_TX_RING_CNT) { \
138 bus_dmamap_sync((sc)->sc_dmat, \
139 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \
140 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \
141 __n -= (MVGBE_TX_RING_CNT - __x); \
142 __x = 0; \
143 } \
144 \
145 /* Now sync whatever is left. */ \
146 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \
147 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \
148 } while (0 /*CONSTCOND*/)
149
150 #define MVGBE_CDRXSYNC(sc, x, ops) \
151 do { \
152 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \
153 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \
154 } while (/*CONSTCOND*/0)
155
156 #define MVGBE_IPGINTTX_DEFAULT 768
157 #define MVGBE_IPGINTRX_DEFAULT 768
158
159 #ifdef MVGBE_EVENT_COUNTERS
160 #define MVGBE_EVCNT_INCR(ev) (ev)->ev_count++
161 #define MVGBE_EVCNT_ADD(ev, val) (ev)->ev_count += (val)
162 #else
163 #define MVGBE_EVCNT_INCR(ev) /* nothing */
164 #define MVGBE_EVCNT_ADD(ev, val) /* nothing */
165 #endif
166
167 struct mvgbe_jpool_entry {
168 int slot;
169 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries;
170 };
171
172 struct mvgbe_chain {
173 void *mvgbe_desc;
174 struct mbuf *mvgbe_mbuf;
175 struct mvgbe_chain *mvgbe_next;
176 };
177
178 struct mvgbe_txmap_entry {
179 bus_dmamap_t dmamap;
180 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link;
181 };
182
183 struct mvgbe_chain_data {
184 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT];
185 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT];
186 int mvgbe_tx_prod;
187 int mvgbe_tx_cons;
188 int mvgbe_tx_cnt;
189
190 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT];
191 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT];
192 bus_dmamap_t mvgbe_rx_jumbo_map;
193 int mvgbe_rx_prod;
194 int mvgbe_rx_cons;
195 int mvgbe_rx_cnt;
196
197 /* Stick the jumbo mem management stuff here too. */
198 void *mvgbe_jslots[MVGBE_JSLOTS];
199 void *mvgbe_jumbo_buf;
200 };
201
202 struct mvgbe_ring_data {
203 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT];
204 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT];
205 };
206
207 struct mvgbec_softc {
208 device_t sc_dev;
209
210 bus_space_tag_t sc_iot;
211 bus_space_handle_t sc_ioh;
212
213 kmutex_t sc_mtx;
214
215 int sc_flags;
216 };
217
218 struct mvgbe_softc {
219 device_t sc_dev;
220 int sc_port;
221 uint32_t sc_version;
222
223 bus_space_tag_t sc_iot;
224 bus_space_handle_t sc_ioh;
225 bus_space_handle_t sc_dafh; /* dest address filter handle */
226 bus_dma_tag_t sc_dmat;
227
228 struct ethercom sc_ethercom;
229 struct mii_data sc_mii;
230 uint8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */
231
232 callout_t sc_tick_ch; /* tick callout */
233
234 struct mvgbe_chain_data sc_cdata;
235 struct mvgbe_ring_data *sc_rdata;
236 bus_dmamap_t sc_ring_map;
237 u_short sc_if_flags;
238 unsigned int sc_ipginttx;
239 unsigned int sc_ipgintrx;
240 int sc_wdogsoft;
241
242 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead;
243 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead;
244 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head;
245
246 struct {
247 bus_space_handle_t ioh;
248 uint32_t bit;
249 } sc_linkup;
250 uint32_t sc_cmdsts_opts;
251
252 krndsource_t sc_rnd_source;
253 struct sysctllog *mvgbe_clog;
254 #ifdef MVGBE_EVENT_COUNTERS
255 struct evcnt sc_ev_rxoverrun;
256 struct evcnt sc_ev_wdogsoft;
257 #endif
258 };
259
260
261 /* Gigabit Ethernet Unit Global part functions */
262
263 static int mvgbec_match(device_t, struct cfdata *, void *);
264 static void mvgbec_attach(device_t, device_t, void *);
265
266 static int mvgbec_print(void *, const char *);
267 static int mvgbec_search(device_t, cfdata_t, const int *, void *);
268
269 /* MII funcstions */
270 static int mvgbec_miibus_readreg(device_t, int, int, uint16_t *);
271 static int mvgbec_miibus_writereg(device_t, int, int, uint16_t);
272 static void mvgbec_miibus_statchg(struct ifnet *);
273
274 static void mvgbec_wininit(struct mvgbec_softc *, enum marvell_tags *);
275
276 /* Gigabit Ethernet Port part functions */
277
278 static int mvgbe_match(device_t, struct cfdata *, void *);
279 static void mvgbe_attach(device_t, device_t, void *);
280
281 static void mvgbe_tick(void *);
282 static int mvgbe_intr(void *);
283
284 static void mvgbe_start(struct ifnet *);
285 static int mvgbe_ioctl(struct ifnet *, u_long, void *);
286 static int mvgbe_init(struct ifnet *);
287 static void mvgbe_stop(struct ifnet *, int);
288 static void mvgbe_watchdog(struct ifnet *);
289
290 static int mvgbe_ifflags_cb(struct ethercom *);
291
292 static int mvgbe_mediachange(struct ifnet *);
293 static void mvgbe_mediastatus(struct ifnet *, struct ifmediareq *);
294
295 static int mvgbe_init_rx_ring(struct mvgbe_softc *);
296 static int mvgbe_init_tx_ring(struct mvgbe_softc *);
297 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t);
298 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *);
299 static void *mvgbe_jalloc(struct mvgbe_softc *);
300 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *);
301 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *);
302 static void mvgbe_rxeof(struct mvgbe_softc *);
303 static void mvgbe_txeof(struct mvgbe_softc *);
304 static uint8_t mvgbe_crc8(const uint8_t *, size_t);
305 static void mvgbe_filter_setup(struct mvgbe_softc *);
306 #ifdef MVGBE_DEBUG
307 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int);
308 #endif
309 static int mvgbe_ipginttx(struct mvgbec_softc *, struct mvgbe_softc *,
310 unsigned int);
311 static int mvgbe_ipgintrx(struct mvgbec_softc *, struct mvgbe_softc *,
312 unsigned int);
313 static void sysctl_mvgbe_init(struct mvgbe_softc *);
314 static int mvgbe_sysctl_ipginttx(SYSCTLFN_PROTO);
315 static int mvgbe_sysctl_ipgintrx(SYSCTLFN_PROTO);
316
317 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc),
318 mvgbec_match, mvgbec_attach, NULL, NULL);
319 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc),
320 mvgbec_match, mvgbec_attach, NULL, NULL);
321
322 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc),
323 mvgbe_match, mvgbe_attach, NULL, NULL);
324
325 device_t mvgbec0 = NULL;
326 static int mvgbe_root_num;
327
328 struct mvgbe_port {
329 int model;
330 int unit;
331 int ports;
332 int irqs[3];
333 int flags;
334 #define FLAGS_FIX_TQTB (1 << 0)
335 #define FLAGS_FIX_MTU (1 << 1)
336 #define FLAGS_IPG1 (1 << 2)
337 #define FLAGS_IPG2 (1 << 3)
338 #define FLAGS_HAS_PV (1 << 4) /* Has Port Version Register */
339 } mvgbe_ports[] = {
340 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 },
341 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 },
342 #if 0
343 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 },
344 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 },
345 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 },
346 #endif
347 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, FLAGS_FIX_MTU },
348 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, FLAGS_FIX_MTU },
349 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 },
350 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 },
351 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 },
352 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, FLAGS_FIX_MTU },
353 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, FLAGS_FIX_MTU },
354
355 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
356 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
357 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
358 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
359 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
360 { MARVELL_KIRKWOOD_88F6282, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
361 { MARVELL_KIRKWOOD_88F6282, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
362
363 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
364 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
365 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
366 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
367 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
368 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
369
370 { MARVELL_DOVE_88AP510, 0, 1, { 29 }, FLAGS_FIX_TQTB | FLAGS_IPG2 },
371
372 { MARVELL_ARMADAXP_MV78130, 0, 1, { 66 }, FLAGS_HAS_PV },
373 { MARVELL_ARMADAXP_MV78130, 1, 1, { 70 }, FLAGS_HAS_PV },
374 { MARVELL_ARMADAXP_MV78130, 2, 1, { 74 }, FLAGS_HAS_PV },
375 { MARVELL_ARMADAXP_MV78160, 0, 1, { 66 }, FLAGS_HAS_PV },
376 { MARVELL_ARMADAXP_MV78160, 1, 1, { 70 }, FLAGS_HAS_PV },
377 { MARVELL_ARMADAXP_MV78160, 2, 1, { 74 }, FLAGS_HAS_PV },
378 { MARVELL_ARMADAXP_MV78160, 3, 1, { 78 }, FLAGS_HAS_PV },
379 { MARVELL_ARMADAXP_MV78230, 0, 1, { 66 }, FLAGS_HAS_PV },
380 { MARVELL_ARMADAXP_MV78230, 1, 1, { 70 }, FLAGS_HAS_PV },
381 { MARVELL_ARMADAXP_MV78230, 2, 1, { 74 }, FLAGS_HAS_PV },
382 { MARVELL_ARMADAXP_MV78260, 0, 1, { 66 }, FLAGS_HAS_PV },
383 { MARVELL_ARMADAXP_MV78260, 1, 1, { 70 }, FLAGS_HAS_PV },
384 { MARVELL_ARMADAXP_MV78260, 2, 1, { 74 }, FLAGS_HAS_PV },
385 { MARVELL_ARMADAXP_MV78260, 3, 1, { 78 }, FLAGS_HAS_PV },
386 { MARVELL_ARMADAXP_MV78460, 0, 1, { 66 }, FLAGS_HAS_PV },
387 { MARVELL_ARMADAXP_MV78460, 1, 1, { 70 }, FLAGS_HAS_PV },
388 { MARVELL_ARMADAXP_MV78460, 2, 1, { 74 }, FLAGS_HAS_PV },
389 { MARVELL_ARMADAXP_MV78460, 3, 1, { 78 }, FLAGS_HAS_PV },
390
391 { MARVELL_ARMADA370_MV6707, 0, 1, { 66 }, FLAGS_HAS_PV },
392 { MARVELL_ARMADA370_MV6707, 1, 1, { 70 }, FLAGS_HAS_PV },
393 { MARVELL_ARMADA370_MV6710, 0, 1, { 66 }, FLAGS_HAS_PV },
394 { MARVELL_ARMADA370_MV6710, 1, 1, { 70 }, FLAGS_HAS_PV },
395 { MARVELL_ARMADA370_MV6W11, 0, 1, { 66 }, FLAGS_HAS_PV },
396 { MARVELL_ARMADA370_MV6W11, 1, 1, { 70 }, FLAGS_HAS_PV },
397 };
398
399
400 /* ARGSUSED */
401 static int
mvgbec_match(device_t parent,cfdata_t match,void * aux)402 mvgbec_match(device_t parent, cfdata_t match, void *aux)
403 {
404 struct marvell_attach_args *mva = aux;
405 int i;
406
407 if (strcmp(mva->mva_name, match->cf_name) != 0)
408 return 0;
409 if (mva->mva_offset == MVA_OFFSET_DEFAULT)
410 return 0;
411
412 for (i = 0; i < __arraycount(mvgbe_ports); i++)
413 if (mva->mva_model == mvgbe_ports[i].model) {
414 mva->mva_size = MVGBE_SIZE;
415 return 1;
416 }
417 return 0;
418 }
419
420 /* ARGSUSED */
421 static void
mvgbec_attach(device_t parent,device_t self,void * aux)422 mvgbec_attach(device_t parent, device_t self, void *aux)
423 {
424 struct mvgbec_softc *csc = device_private(self);
425 struct marvell_attach_args *mva = aux, gbea;
426 struct mvgbe_softc *port;
427 struct mii_softc *mii;
428 device_t child;
429 uint32_t phyaddr;
430 int i, j;
431
432 aprint_naive("\n");
433 aprint_normal(": Marvell Gigabit Ethernet Controller\n");
434
435 csc->sc_dev = self;
436 csc->sc_iot = mva->mva_iot;
437 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset,
438 mva->mva_size, &csc->sc_ioh)) {
439 aprint_error_dev(self, "Cannot map registers\n");
440 return;
441 }
442
443 if (mvgbec0 == NULL)
444 mvgbec0 = self;
445
446 phyaddr = 0;
447 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr);
448
449 mutex_init(&csc->sc_mtx, MUTEX_DEFAULT, IPL_NET);
450
451 /* Disable and clear Gigabit Ethernet Unit interrupts */
452 MVGBE_WRITE(csc, MVGBE_EUIM, 0);
453 MVGBE_WRITE(csc, MVGBE_EUIC, 0);
454
455 mvgbec_wininit(csc, mva->mva_tags);
456
457 memset(&gbea, 0, sizeof(gbea));
458 for (i = 0; i < __arraycount(mvgbe_ports); i++) {
459 if (mvgbe_ports[i].model != mva->mva_model ||
460 mvgbe_ports[i].unit != mva->mva_unit)
461 continue;
462
463 csc->sc_flags = mvgbe_ports[i].flags;
464
465 for (j = 0; j < mvgbe_ports[i].ports; j++) {
466 gbea.mva_name = "mvgbe";
467 gbea.mva_model = mva->mva_model;
468 gbea.mva_iot = csc->sc_iot;
469 gbea.mva_ioh = csc->sc_ioh;
470 gbea.mva_unit = j;
471 gbea.mva_dmat = mva->mva_dmat;
472 gbea.mva_irq = mvgbe_ports[i].irqs[j];
473 child = config_found(csc->sc_dev, &gbea, mvgbec_print,
474 CFARGS(.submatch = mvgbec_search));
475 if (child) {
476 port = device_private(child);
477 mii = LIST_FIRST(&port->sc_mii.mii_phys);
478 if (mii != NULL)
479 phyaddr |= MVGBE_PHYADDR_PHYAD(j,
480 mii->mii_phy);
481 }
482 }
483 break;
484 }
485 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr);
486 }
487
488 static int
mvgbec_print(void * aux,const char * pnp)489 mvgbec_print(void *aux, const char *pnp)
490 {
491 struct marvell_attach_args *gbea = aux;
492
493 if (pnp)
494 aprint_normal("%s at %s port %d",
495 gbea->mva_name, pnp, gbea->mva_unit);
496 else {
497 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT)
498 aprint_normal(" port %d", gbea->mva_unit);
499 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT)
500 aprint_normal(" irq %d", gbea->mva_irq);
501 }
502 return UNCONF;
503 }
504
505 /* ARGSUSED */
506 static int
mvgbec_search(device_t parent,cfdata_t cf,const int * ldesc,void * aux)507 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
508 {
509 struct marvell_attach_args *gbea = aux;
510
511 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit &&
512 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT)
513 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ];
514
515 return config_match(parent, cf, aux);
516 }
517
518 static int
mvgbec_miibus_readreg(device_t dev,int phy,int reg,uint16_t * val)519 mvgbec_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
520 {
521 struct mvgbe_softc *sc = device_private(dev);
522 struct mvgbec_softc *csc;
523 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
524 uint32_t smi;
525 int i, rv = 0;
526
527 if (mvgbec0 == NULL) {
528 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n");
529 return -1;
530 }
531 csc = device_private(mvgbec0);
532
533 mutex_enter(&csc->sc_mtx);
534
535 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) {
536 DELAY(1);
537 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY))
538 break;
539 }
540 if (i == MVGBE_PHY_TIMEOUT) {
541 aprint_error_ifnet(ifp, "SMI busy timeout\n");
542 rv = ETIMEDOUT;
543 goto out;
544 }
545
546 smi =
547 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ;
548 MVGBE_WRITE(csc, MVGBE_SMI, smi);
549
550 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) {
551 DELAY(1);
552 smi = MVGBE_READ(csc, MVGBE_SMI);
553 if (smi & MVGBE_SMI_READVALID) {
554 *val = smi & MVGBE_SMI_DATA_MASK;
555 break;
556 }
557 }
558 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n",
559 i, MVGBE_PHY_TIMEOUT));
560 if (i >= MVGBE_PHY_TIMEOUT)
561 rv = ETIMEDOUT;
562
563 out:
564 mutex_exit(&csc->sc_mtx);
565
566 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#hx\n",
567 phy, reg, *val));
568
569 return rv;
570 }
571
572 static int
mvgbec_miibus_writereg(device_t dev,int phy,int reg,uint16_t val)573 mvgbec_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
574 {
575 struct mvgbe_softc *sc = device_private(dev);
576 struct mvgbec_softc *csc;
577 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
578 uint32_t smi;
579 int i, rv = 0;
580
581 if (mvgbec0 == NULL) {
582 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n");
583 return -1;
584 }
585 csc = device_private(mvgbec0);
586
587 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n",
588 phy, reg, val));
589
590 mutex_enter(&csc->sc_mtx);
591
592 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) {
593 DELAY(1);
594 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY))
595 break;
596 }
597 if (i == MVGBE_PHY_TIMEOUT) {
598 aprint_error_ifnet(ifp, "SMI busy timeout\n");
599 rv = ETIMEDOUT;
600 goto out;
601 }
602
603 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) |
604 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK);
605 MVGBE_WRITE(csc, MVGBE_SMI, smi);
606
607 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) {
608 DELAY(1);
609 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY))
610 break;
611 }
612
613 out:
614 mutex_exit(&csc->sc_mtx);
615
616 if (i == MVGBE_PHY_TIMEOUT) {
617 aprint_error_ifnet(ifp, "phy write timed out\n");
618 rv = ETIMEDOUT;
619 }
620
621 return rv;
622 }
623
624 static void
mvgbec_miibus_statchg(struct ifnet * ifp)625 mvgbec_miibus_statchg(struct ifnet *ifp)
626 {
627
628 /* nothing to do */
629 }
630
631
632 static void
mvgbec_wininit(struct mvgbec_softc * sc,enum marvell_tags * tags)633 mvgbec_wininit(struct mvgbec_softc *sc, enum marvell_tags *tags)
634 {
635 device_t pdev = device_parent(sc->sc_dev);
636 uint64_t base;
637 uint32_t en, ac, size;
638 int window, target, attr, rv, i;
639
640 /* First disable all address decode windows */
641 en = MVGBE_BARE_EN_MASK;
642 MVGBE_WRITE(sc, MVGBE_BARE, en);
643
644 ac = 0;
645 for (window = 0, i = 0;
646 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) {
647 rv = marvell_winparams_by_tag(pdev, tags[i],
648 &target, &attr, &base, &size);
649 if (rv != 0 || size == 0)
650 continue;
651
652 if (base > 0xffffffffULL) {
653 if (window >= MVGBE_NREMAP) {
654 aprint_error_dev(sc->sc_dev,
655 "can't remap window %d\n", window);
656 continue;
657 }
658 MVGBE_WRITE(sc, MVGBE_HA(window),
659 (base >> 32) & 0xffffffff);
660 }
661
662 MVGBE_WRITE(sc, MVGBE_BASEADDR(window),
663 MVGBE_BASEADDR_TARGET(target) |
664 MVGBE_BASEADDR_ATTR(attr) |
665 MVGBE_BASEADDR_BASE(base));
666 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size));
667
668 en &= ~(1 << window);
669 /* set full access (r/w) */
670 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA);
671 window++;
672 }
673 /* allow to access decode window */
674 MVGBE_WRITE(sc, MVGBE_EPAP, ac);
675
676 MVGBE_WRITE(sc, MVGBE_BARE, en);
677 }
678
679
680 /* ARGSUSED */
681 static int
mvgbe_match(device_t parent,cfdata_t match,void * aux)682 mvgbe_match(device_t parent, cfdata_t match, void *aux)
683 {
684 struct marvell_attach_args *mva = aux;
685 uint32_t pbase, maddrh, maddrl;
686 prop_dictionary_t dict;
687
688 dict = device_properties(parent);
689 if (dict) {
690 if (prop_dictionary_get(dict, "mac-address"))
691 return 1;
692 }
693
694 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE;
695 maddrh =
696 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH);
697 maddrl =
698 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL);
699 if ((maddrh | maddrl) == 0)
700 return 0;
701
702 return 1;
703 }
704
705 /* ARGSUSED */
706 static void
mvgbe_attach(device_t parent,device_t self,void * aux)707 mvgbe_attach(device_t parent, device_t self, void *aux)
708 {
709 struct mvgbec_softc *csc = device_private(parent);
710 struct mvgbe_softc *sc = device_private(self);
711 struct marvell_attach_args *mva = aux;
712 struct mvgbe_txmap_entry *entry;
713 prop_dictionary_t dict;
714 prop_data_t enaddrp;
715 struct ifnet *ifp;
716 struct mii_data * const mii = &sc->sc_mii;
717 bus_dma_segment_t seg;
718 bus_dmamap_t dmamap;
719 int rseg, i;
720 uint32_t maddrh, maddrl;
721 uint8_t enaddr[ETHER_ADDR_LEN];
722 void *kva;
723
724 aprint_naive("\n");
725 aprint_normal("\n");
726
727 dict = device_properties(parent);
728 if (dict)
729 enaddrp = prop_dictionary_get(dict, "mac-address");
730 else
731 enaddrp = NULL;
732
733 sc->sc_dev = self;
734 sc->sc_port = mva->mva_unit;
735 sc->sc_iot = mva->mva_iot;
736 callout_init(&sc->sc_tick_ch, 0);
737 callout_setfunc(&sc->sc_tick_ch, mvgbe_tick, sc);
738 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
739 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE,
740 MVGBE_PORTR_SIZE, &sc->sc_ioh)) {
741 aprint_error_dev(self, "Cannot map registers\n");
742 return;
743 }
744 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
745 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE,
746 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) {
747 aprint_error_dev(self,
748 "Cannot map destination address filter registers\n");
749 return;
750 }
751 sc->sc_dmat = mva->mva_dmat;
752
753 if (csc->sc_flags & FLAGS_HAS_PV) {
754 /* GbE port has Port Version register. */
755 sc->sc_version = MVGBE_READ(sc, MVGBE_PV);
756 aprint_normal_dev(self, "Port Version 0x%x\n", sc->sc_version);
757 }
758
759 if (sc->sc_version >= 0x10) {
760 /*
761 * Armada XP
762 */
763
764 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
765 MVGBE_PS0, sizeof(uint32_t), &sc->sc_linkup.ioh)) {
766 aprint_error_dev(self, "Cannot map linkup register\n");
767 return;
768 }
769 sc->sc_linkup.bit = MVGBE_PS0_LINKUP;
770 csc->sc_flags |= FLAGS_IPG2;
771 } else {
772 if (bus_space_subregion(mva->mva_iot, sc->sc_ioh,
773 MVGBE_PS, sizeof(uint32_t), &sc->sc_linkup.ioh)) {
774 aprint_error_dev(self, "Cannot map linkup register\n");
775 return;
776 }
777 sc->sc_linkup.bit = MVGBE_PS_LINKUP;
778 }
779
780 if (enaddrp) {
781 memcpy(enaddr, prop_data_data_nocopy(enaddrp), ETHER_ADDR_LEN);
782 maddrh = enaddr[0] << 24;
783 maddrh |= enaddr[1] << 16;
784 maddrh |= enaddr[2] << 8;
785 maddrh |= enaddr[3];
786 maddrl = enaddr[4] << 8;
787 maddrl |= enaddr[5];
788 MVGBE_WRITE(sc, MVGBE_MACAH, maddrh);
789 MVGBE_WRITE(sc, MVGBE_MACAL, maddrl);
790 }
791
792 maddrh = MVGBE_READ(sc, MVGBE_MACAH);
793 maddrl = MVGBE_READ(sc, MVGBE_MACAL);
794 sc->sc_enaddr[0] = maddrh >> 24;
795 sc->sc_enaddr[1] = maddrh >> 16;
796 sc->sc_enaddr[2] = maddrh >> 8;
797 sc->sc_enaddr[3] = maddrh >> 0;
798 sc->sc_enaddr[4] = maddrl >> 8;
799 sc->sc_enaddr[5] = maddrl >> 0;
800 aprint_normal_dev(self, "Ethernet address %s\n",
801 ether_sprintf(sc->sc_enaddr));
802
803 /* clear all ethernet port interrupts */
804 MVGBE_WRITE(sc, MVGBE_IC, 0);
805 MVGBE_WRITE(sc, MVGBE_ICE, 0);
806
807 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc);
808
809 /* Allocate the descriptor queues. */
810 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data),
811 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
812 aprint_error_dev(self, "can't alloc rx buffers\n");
813 return;
814 }
815 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg,
816 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) {
817 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n",
818 (u_long)sizeof(struct mvgbe_ring_data));
819 goto fail1;
820 }
821 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1,
822 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT,
823 &sc->sc_ring_map)) {
824 aprint_error_dev(self, "can't create dma map\n");
825 goto fail2;
826 }
827 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva,
828 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) {
829 aprint_error_dev(self, "can't load dma map\n");
830 goto fail3;
831 }
832 for (i = 0; i < MVGBE_RX_RING_CNT; i++)
833 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL;
834
835 SIMPLEQ_INIT(&sc->sc_txmap_head);
836 for (i = 0; i < MVGBE_TX_RING_CNT; i++) {
837 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL;
838
839 if (bus_dmamap_create(sc->sc_dmat,
840 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0,
841 BUS_DMA_NOWAIT, &dmamap)) {
842 aprint_error_dev(self, "Can't create TX dmamap\n");
843 goto fail4;
844 }
845
846 entry = kmem_alloc(sizeof(*entry), KM_SLEEP);
847 entry->dmamap = dmamap;
848 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link);
849 }
850
851 sc->sc_rdata = (struct mvgbe_ring_data *)kva;
852 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data));
853
854 /*
855 * We can support 802.1Q VLAN-sized frames and jumbo
856 * Ethernet frames.
857 */
858 sc->sc_ethercom.ec_capabilities |=
859 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU;
860
861 /* Try to allocate memory for jumbo buffers. */
862 if (mvgbe_alloc_jumbo_mem(sc)) {
863 aprint_error_dev(self, "jumbo buffer allocation failed\n");
864 goto fail4;
865 }
866
867 ifp = &sc->sc_ethercom.ec_if;
868 ifp->if_softc = sc;
869 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
870 ifp->if_start = mvgbe_start;
871 ifp->if_ioctl = mvgbe_ioctl;
872 ifp->if_init = mvgbe_init;
873 ifp->if_stop = mvgbe_stop;
874 ifp->if_watchdog = mvgbe_watchdog;
875 /*
876 * We can do IPv4/TCPv4/UDPv4 checksums in hardware.
877 */
878 sc->sc_ethercom.ec_if.if_capabilities |=
879 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
880 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
881 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
882 /*
883 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums.
884 */
885 sc->sc_ethercom.ec_if.if_capabilities &= ~IFCAP_CSUM_TCPv4_Tx;
886 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN));
887 IFQ_SET_READY(&ifp->if_snd);
888 strcpy(ifp->if_xname, device_xname(sc->sc_dev));
889
890 mvgbe_stop(ifp, 0);
891
892 /*
893 * Do MII setup.
894 */
895 mii->mii_ifp = ifp;
896 mii->mii_readreg = mvgbec_miibus_readreg;
897 mii->mii_writereg = mvgbec_miibus_writereg;
898 mii->mii_statchg = mvgbec_miibus_statchg;
899
900 sc->sc_ethercom.ec_mii = mii;
901 ifmedia_init(&mii->mii_media, 0, mvgbe_mediachange, mvgbe_mediastatus);
902 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY,
903 parent == mvgbec0 ? 0 : 1, 0);
904 if (LIST_FIRST(&mii->mii_phys) == NULL) {
905 aprint_error_dev(self, "no PHY found!\n");
906 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL);
907 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL);
908 } else
909 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
910
911 /*
912 * Call MI attach routines.
913 */
914 if_attach(ifp);
915 if_deferred_start_init(ifp, NULL);
916
917 ether_ifattach(ifp, sc->sc_enaddr);
918 ether_set_ifflags_cb(&sc->sc_ethercom, mvgbe_ifflags_cb);
919
920 sysctl_mvgbe_init(sc);
921 #ifdef MVGBE_EVENT_COUNTERS
922 /* Attach event counters. */
923 evcnt_attach_dynamic(&sc->sc_ev_rxoverrun, EVCNT_TYPE_MISC,
924 NULL, device_xname(sc->sc_dev), "rxoverrrun");
925 evcnt_attach_dynamic(&sc->sc_ev_wdogsoft, EVCNT_TYPE_MISC,
926 NULL, device_xname(sc->sc_dev), "wdogsoft");
927 #endif
928 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev),
929 RND_TYPE_NET, RND_FLAG_DEFAULT);
930
931 return;
932
933 fail4:
934 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) {
935 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link);
936 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap);
937 }
938 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map);
939 fail3:
940 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map);
941 fail2:
942 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data));
943 fail1:
944 bus_dmamem_free(sc->sc_dmat, &seg, rseg);
945 return;
946 }
947
948 static int
mvgbe_ipginttx(struct mvgbec_softc * csc,struct mvgbe_softc * sc,unsigned int ipginttx)949 mvgbe_ipginttx(struct mvgbec_softc *csc, struct mvgbe_softc *sc,
950 unsigned int ipginttx)
951 {
952 uint32_t reg;
953 reg = MVGBE_READ(sc, MVGBE_PTFUT);
954
955 if (csc->sc_flags & FLAGS_IPG2) {
956 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V2_MAX)
957 return -1;
958 reg &= ~MVGBE_PTFUT_IPGINTTX_V2_MASK;
959 reg |= MVGBE_PTFUT_IPGINTTX_V2(ipginttx);
960 } else if (csc->sc_flags & FLAGS_IPG1) {
961 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V1_MAX)
962 return -1;
963 reg &= ~MVGBE_PTFUT_IPGINTTX_V1_MASK;
964 reg |= MVGBE_PTFUT_IPGINTTX_V1(ipginttx);
965 }
966 MVGBE_WRITE(sc, MVGBE_PTFUT, reg);
967
968 return 0;
969 }
970
971 static int
mvgbe_ipgintrx(struct mvgbec_softc * csc,struct mvgbe_softc * sc,unsigned int ipgintrx)972 mvgbe_ipgintrx(struct mvgbec_softc *csc, struct mvgbe_softc *sc,
973 unsigned int ipgintrx)
974 {
975 uint32_t reg;
976 reg = MVGBE_READ(sc, MVGBE_SDC);
977
978 if (csc->sc_flags & FLAGS_IPG2) {
979 if (ipgintrx > MVGBE_SDC_IPGINTRX_V2_MAX)
980 return -1;
981 reg &= ~MVGBE_SDC_IPGINTRX_V2_MASK;
982 reg |= MVGBE_SDC_IPGINTRX_V2(ipgintrx);
983 } else if (csc->sc_flags & FLAGS_IPG1) {
984 if (ipgintrx > MVGBE_SDC_IPGINTRX_V1_MAX)
985 return -1;
986 reg &= ~MVGBE_SDC_IPGINTRX_V1_MASK;
987 reg |= MVGBE_SDC_IPGINTRX_V1(ipgintrx);
988 }
989 MVGBE_WRITE(sc, MVGBE_SDC, reg);
990
991 return 0;
992 }
993
994 static void
mvgbe_tick(void * arg)995 mvgbe_tick(void *arg)
996 {
997 struct mvgbe_softc *sc = arg;
998 struct mii_data *mii = &sc->sc_mii;
999 int s;
1000
1001 s = splnet();
1002 mii_tick(mii);
1003 /* Need more work */
1004 MVGBE_EVCNT_ADD(&sc->sc_ev_rxoverrun, MVGBE_READ(sc, MVGBE_POFC));
1005 splx(s);
1006
1007 callout_schedule(&sc->sc_tick_ch, hz);
1008 }
1009
1010 static int
mvgbe_intr(void * arg)1011 mvgbe_intr(void *arg)
1012 {
1013 struct mvgbe_softc *sc = arg;
1014 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1015 uint32_t ic, ice, datum = 0;
1016 int claimed = 0;
1017
1018 for (;;) {
1019 ice = MVGBE_READ(sc, MVGBE_ICE);
1020 ic = MVGBE_READ(sc, MVGBE_IC);
1021
1022 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice));
1023 if (ic == 0 && ice == 0)
1024 break;
1025
1026 datum = datum ^ ic ^ ice;
1027
1028 MVGBE_WRITE(sc, MVGBE_IC, ~ic);
1029 MVGBE_WRITE(sc, MVGBE_ICE, ~ice);
1030
1031 claimed = 1;
1032
1033 if (!(ifp->if_flags & IFF_RUNNING))
1034 break;
1035
1036 if (ice & MVGBE_ICE_LINKCHG) {
1037 if (MVGBE_IS_LINKUP(sc)) {
1038 /* Enable port RX and TX. */
1039 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0));
1040 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0));
1041 } else {
1042 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0));
1043 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0));
1044 }
1045
1046 /* Notify link change event to mii layer */
1047 mii_pollstat(&sc->sc_mii);
1048 }
1049
1050 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR))
1051 mvgbe_rxeof(sc);
1052
1053 if (ice & (MVGBE_ICE_TXBUF_MASK | MVGBE_ICE_TXERR_MASK))
1054 mvgbe_txeof(sc);
1055 }
1056
1057 if_schedule_deferred_start(ifp);
1058
1059 rnd_add_uint32(&sc->sc_rnd_source, datum);
1060
1061 return claimed;
1062 }
1063
1064 static void
mvgbe_start(struct ifnet * ifp)1065 mvgbe_start(struct ifnet *ifp)
1066 {
1067 struct mvgbe_softc *sc = ifp->if_softc;
1068 struct mbuf *m_head = NULL;
1069 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod;
1070 int pkts = 0;
1071
1072 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx,
1073 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf));
1074
1075 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1076 return;
1077 /* If Link is DOWN, can't start TX */
1078 if (!MVGBE_IS_LINKUP(sc))
1079 return;
1080
1081 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) {
1082 IFQ_POLL(&ifp->if_snd, m_head);
1083 if (m_head == NULL)
1084 break;
1085
1086 /*
1087 * Pack the data into the transmit ring. If we
1088 * don't have room, set the OACTIVE flag and wait
1089 * for the NIC to drain the ring.
1090 */
1091 if (mvgbe_encap(sc, m_head, &idx)) {
1092 if (sc->sc_cdata.mvgbe_tx_cnt > 0)
1093 ifp->if_flags |= IFF_OACTIVE;
1094 break;
1095 }
1096
1097 /* now we are committed to transmit the packet */
1098 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1099 pkts++;
1100
1101 /*
1102 * If there's a BPF listener, bounce a copy of this frame
1103 * to him.
1104 */
1105 bpf_mtap(ifp, m_head, BPF_D_OUT);
1106 }
1107 if (pkts == 0)
1108 return;
1109
1110 /* Transmit at Queue 0 */
1111 if (idx != sc->sc_cdata.mvgbe_tx_prod) {
1112 sc->sc_cdata.mvgbe_tx_prod = idx;
1113 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0));
1114
1115 /*
1116 * Set a timeout in case the chip goes out to lunch.
1117 */
1118 ifp->if_timer = 1;
1119 sc->sc_wdogsoft = 1;
1120 }
1121 }
1122
1123 static int
mvgbe_ioctl(struct ifnet * ifp,u_long cmd,void * data)1124 mvgbe_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1125 {
1126 struct mvgbe_softc *sc = ifp->if_softc;
1127 int s, error = 0;
1128
1129 s = splnet();
1130
1131 switch (cmd) {
1132 default:
1133 DPRINTFN(2, ("mvgbe_ioctl ETHER\n"));
1134 error = ether_ioctl(ifp, cmd, data);
1135 if (error == ENETRESET) {
1136 if (ifp->if_flags & IFF_RUNNING) {
1137 mvgbe_filter_setup(sc);
1138 }
1139 error = 0;
1140 }
1141 break;
1142 }
1143
1144 splx(s);
1145
1146 return error;
1147 }
1148
1149 static int
mvgbe_init(struct ifnet * ifp)1150 mvgbe_init(struct ifnet *ifp)
1151 {
1152 struct mvgbe_softc *sc = ifp->if_softc;
1153 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev));
1154 struct mii_data *mii = &sc->sc_mii;
1155 uint32_t reg;
1156 int i;
1157
1158 DPRINTFN(2, ("mvgbe_init\n"));
1159
1160 /* Cancel pending I/O and free all RX/TX buffers. */
1161 mvgbe_stop(ifp, 0);
1162
1163 /* clear all ethernet port interrupts */
1164 MVGBE_WRITE(sc, MVGBE_IC, 0);
1165 MVGBE_WRITE(sc, MVGBE_ICE, 0);
1166
1167 /* Init TX/RX descriptors */
1168 if (mvgbe_init_tx_ring(sc) == ENOBUFS) {
1169 aprint_error_ifnet(ifp,
1170 "initialization failed: no memory for tx buffers\n");
1171 return ENOBUFS;
1172 }
1173 if (mvgbe_init_rx_ring(sc) == ENOBUFS) {
1174 aprint_error_ifnet(ifp,
1175 "initialization failed: no memory for rx buffers\n");
1176 return ENOBUFS;
1177 }
1178
1179 if ((csc->sc_flags & FLAGS_IPG1) || (csc->sc_flags & FLAGS_IPG2)) {
1180 sc->sc_ipginttx = MVGBE_IPGINTTX_DEFAULT;
1181 sc->sc_ipgintrx = MVGBE_IPGINTRX_DEFAULT;
1182 }
1183 if (csc->sc_flags & FLAGS_FIX_MTU)
1184 MVGBE_WRITE(sc, MVGBE_MTU, 0); /* hw reset value is wrong */
1185 if (sc->sc_version >= 0x10) {
1186 MVGBE_WRITE(csc, MVGBE_PANC,
1187 MVGBE_PANC_FORCELINKPASS |
1188 MVGBE_PANC_INBANDANBYPASSEN |
1189 MVGBE_PANC_SETMIISPEED |
1190 MVGBE_PANC_SETGMIISPEED |
1191 MVGBE_PANC_ANSPEEDEN |
1192 MVGBE_PANC_SETFCEN |
1193 MVGBE_PANC_PAUSEADV |
1194 MVGBE_PANC_SETFULLDX |
1195 MVGBE_PANC_ANDUPLEXEN |
1196 MVGBE_PANC_RESERVED);
1197 MVGBE_WRITE(csc, MVGBE_PMACC0,
1198 MVGBE_PMACC0_RESERVED |
1199 MVGBE_PMACC0_FRAMESIZELIMIT(1600));
1200 reg = MVGBE_READ(csc, MVGBE_PMACC2);
1201 reg &= MVGBE_PMACC2_PCSEN; /* keep PCSEN bit */
1202 MVGBE_WRITE(csc, MVGBE_PMACC2,
1203 reg | MVGBE_PMACC2_RESERVED | MVGBE_PMACC2_RGMIIEN);
1204
1205 MVGBE_WRITE(sc, MVGBE_PXCX,
1206 MVGBE_READ(sc, MVGBE_PXCX) & ~MVGBE_PXCX_TXCRCDIS);
1207
1208 #ifndef MULTIPROCESSOR
1209 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_BM);
1210 #else
1211 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_EDM);
1212 #endif
1213 } else {
1214 MVGBE_WRITE(sc, MVGBE_PSC,
1215 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */
1216 MVGBE_PSC_RESERVED | /* Must be set to 1 */
1217 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */
1218 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */
1219 MVGBE_PSC_SETFULLDX); /* Set_FullDx */
1220 /* XXXX: mvgbe(4) always use RGMII. */
1221 MVGBE_WRITE(sc, MVGBE_PSC1,
1222 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN);
1223 /* XXXX: Also always Weighted Round-Robin Priority Mode */
1224 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0));
1225
1226 sc->sc_cmdsts_opts = MVGBE_TX_GENERATE_CRC;
1227 }
1228
1229 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0));
1230 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0));
1231
1232 if (csc->sc_flags & FLAGS_FIX_TQTB) {
1233 /*
1234 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff.
1235 * And offset 0x72704 must be programmed to 0x03ffffff.
1236 * Queue 1 through 7 must be programmed to 0x0.
1237 */
1238 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff);
1239 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff);
1240 for (i = 1; i < 8; i++) {
1241 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0);
1242 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0);
1243 }
1244 } else if (sc->sc_version < 0x10)
1245 for (i = 1; i < 8; i++) {
1246 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff);
1247 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff);
1248 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff);
1249 }
1250
1251 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS);
1252 MVGBE_WRITE(sc, MVGBE_PXCX, 0);
1253
1254 /* Set SDC register except IPGINT bits */
1255 MVGBE_WRITE(sc, MVGBE_SDC,
1256 MVGBE_SDC_RXBSZ_16_64BITWORDS |
1257 #ifndef MVGBE_BIG_ENDIAN
1258 MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */
1259 MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */
1260 #endif
1261 MVGBE_SDC_TXBSZ_16_64BITWORDS);
1262 /* And then set IPGINT bits */
1263 mvgbe_ipgintrx(csc, sc, sc->sc_ipgintrx);
1264
1265 /* Tx side */
1266 MVGBE_WRITE(sc, MVGBE_PTFUT, 0);
1267 mvgbe_ipginttx(csc, sc, sc->sc_ipginttx);
1268
1269 mvgbe_filter_setup(sc);
1270
1271 mii_mediachg(mii);
1272
1273 /* Enable port */
1274 if (sc->sc_version >= 0x10) {
1275 reg = MVGBE_READ(csc, MVGBE_PMACC0);
1276 MVGBE_WRITE(csc, MVGBE_PMACC0, reg | MVGBE_PMACC0_PORTEN);
1277 } else {
1278 reg = MVGBE_READ(sc, MVGBE_PSC);
1279 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN);
1280 }
1281
1282 /* If Link is UP, Start RX and TX traffic */
1283 if (MVGBE_IS_LINKUP(sc)) {
1284 /* Enable port RX/TX. */
1285 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0));
1286 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0));
1287 }
1288
1289 /* Enable interrupt masks */
1290 MVGBE_WRITE(sc, MVGBE_PIM,
1291 MVGBE_IC_RXBUF |
1292 MVGBE_IC_EXTEND |
1293 MVGBE_IC_RXBUFQ_MASK |
1294 MVGBE_IC_RXERROR |
1295 MVGBE_IC_RXERRQ_MASK);
1296 MVGBE_WRITE(sc, MVGBE_PEIM,
1297 MVGBE_ICE_TXBUF_MASK |
1298 MVGBE_ICE_TXERR_MASK |
1299 MVGBE_ICE_LINKCHG);
1300
1301 callout_schedule(&sc->sc_tick_ch, hz);
1302
1303 ifp->if_flags |= IFF_RUNNING;
1304 ifp->if_flags &= ~IFF_OACTIVE;
1305
1306 return 0;
1307 }
1308
1309 /* ARGSUSED */
1310 static void
mvgbe_stop(struct ifnet * ifp,int disable)1311 mvgbe_stop(struct ifnet *ifp, int disable)
1312 {
1313 struct mvgbe_softc *sc = ifp->if_softc;
1314 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev));
1315 struct mvgbe_chain_data *cdata = &sc->sc_cdata;
1316 uint32_t reg, txinprog, txfifoemp;
1317 int i, cnt;
1318
1319 DPRINTFN(2, ("mvgbe_stop\n"));
1320
1321 callout_stop(&sc->sc_tick_ch);
1322
1323 /* Stop Rx port activity. Check port Rx activity. */
1324 reg = MVGBE_READ(sc, MVGBE_RQC);
1325 if (reg & MVGBE_RQC_ENQ_MASK)
1326 /* Issue stop command for active channels only */
1327 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg));
1328
1329 /* Stop Tx port activity. Check port Tx activity. */
1330 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ(0))
1331 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0));
1332
1333 /* Force link down */
1334 if (sc->sc_version >= 0x10) {
1335 reg = MVGBE_READ(csc, MVGBE_PANC);
1336 MVGBE_WRITE(csc, MVGBE_PANC, reg | MVGBE_PANC_FORCELINKFAIL);
1337
1338 txinprog = MVGBE_PS_TXINPROG_(0);
1339 txfifoemp = MVGBE_PS_TXFIFOEMP_(0);
1340 } else {
1341 reg = MVGBE_READ(sc, MVGBE_PSC);
1342 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL);
1343
1344 txinprog = MVGBE_PS_TXINPROG;
1345 txfifoemp = MVGBE_PS_TXFIFOEMP;
1346 }
1347
1348 #define RX_DISABLE_TIMEOUT 0x1000000
1349 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000
1350 /* Wait for all Rx activity to terminate. */
1351 cnt = 0;
1352 do {
1353 if (cnt >= RX_DISABLE_TIMEOUT) {
1354 aprint_error_ifnet(ifp,
1355 "timeout for RX stopped. rqc 0x%x\n", reg);
1356 break;
1357 }
1358 cnt++;
1359
1360 /*
1361 * Check Receive Queue Command register that all Rx queues
1362 * are stopped
1363 */
1364 reg = MVGBE_READ(sc, MVGBE_RQC);
1365 } while (reg & 0xff);
1366
1367 /* Double check to verify that TX FIFO is empty */
1368 cnt = 0;
1369 while (1) {
1370 do {
1371 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) {
1372 aprint_error_ifnet(ifp,
1373 "timeout for TX FIFO empty. status 0x%x\n",
1374 reg);
1375 break;
1376 }
1377 cnt++;
1378
1379 reg = MVGBE_READ(sc, MVGBE_PS);
1380 } while (!(reg & txfifoemp) || reg & txinprog);
1381
1382 if (cnt >= TX_FIFO_EMPTY_TIMEOUT)
1383 break;
1384
1385 /* Double check */
1386 reg = MVGBE_READ(sc, MVGBE_PS);
1387 if (reg & txfifoemp && !(reg & txinprog))
1388 break;
1389 else
1390 aprint_error_ifnet(ifp,
1391 "TX FIFO empty double check failed."
1392 " %d loops, status 0x%x\n", cnt, reg);
1393 }
1394
1395 /* Reset the Enable bit */
1396 if (sc->sc_version >= 0x10) {
1397 reg = MVGBE_READ(csc, MVGBE_PMACC0);
1398 MVGBE_WRITE(csc, MVGBE_PMACC0, reg & ~MVGBE_PMACC0_PORTEN);
1399 } else {
1400 reg = MVGBE_READ(sc, MVGBE_PSC);
1401 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN);
1402 }
1403
1404 /*
1405 * Disable and clear interrupts
1406 * 0) controller interrupt
1407 * 1) port interrupt cause
1408 * 2) port interrupt mask
1409 */
1410 MVGBE_WRITE(csc, MVGBE_EUIM, 0);
1411 MVGBE_WRITE(csc, MVGBE_EUIC, 0);
1412 MVGBE_WRITE(sc, MVGBE_IC, 0);
1413 MVGBE_WRITE(sc, MVGBE_ICE, 0);
1414 MVGBE_WRITE(sc, MVGBE_PIM, 0);
1415 MVGBE_WRITE(sc, MVGBE_PEIM, 0);
1416
1417 /* Free RX and TX mbufs still in the queues. */
1418 for (i = 0; i < MVGBE_RX_RING_CNT; i++) {
1419 if (cdata->mvgbe_rx_chain[i].mvgbe_mbuf != NULL) {
1420 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf);
1421 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL;
1422 }
1423 }
1424 for (i = 0; i < MVGBE_TX_RING_CNT; i++) {
1425 if (cdata->mvgbe_tx_chain[i].mvgbe_mbuf != NULL) {
1426 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf);
1427 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL;
1428 }
1429 }
1430
1431 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1432 }
1433
1434 static void
mvgbe_watchdog(struct ifnet * ifp)1435 mvgbe_watchdog(struct ifnet *ifp)
1436 {
1437 struct mvgbe_softc *sc = ifp->if_softc;
1438
1439 /*
1440 * Reclaim first as there is a possibility of losing Tx completion
1441 * interrupts.
1442 */
1443 mvgbe_txeof(sc);
1444 if (sc->sc_cdata.mvgbe_tx_cnt != 0) {
1445 if (sc->sc_wdogsoft) {
1446 /*
1447 * There is race condition between CPU and DMA
1448 * engine. When DMA engine encounters queue end,
1449 * it clears MVGBE_TQC_ENQ bit.
1450 */
1451 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0));
1452 ifp->if_timer = 5;
1453 sc->sc_wdogsoft = 0;
1454 MVGBE_EVCNT_INCR(&sc->sc_ev_wdogsoft);
1455 } else {
1456 aprint_error_ifnet(ifp, "watchdog timeout\n");
1457
1458 if_statinc(ifp, if_oerrors);
1459
1460 mvgbe_init(ifp);
1461 }
1462 }
1463 }
1464
1465 static int
mvgbe_ifflags_cb(struct ethercom * ec)1466 mvgbe_ifflags_cb(struct ethercom *ec)
1467 {
1468 struct ifnet *ifp = &ec->ec_if;
1469 struct mvgbe_softc *sc = ifp->if_softc;
1470 u_short change = ifp->if_flags ^ sc->sc_if_flags;
1471
1472 if (change != 0)
1473 sc->sc_if_flags = ifp->if_flags;
1474
1475 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0)
1476 return ENETRESET;
1477
1478 if ((change & IFF_PROMISC) != 0)
1479 mvgbe_filter_setup(sc);
1480
1481 return 0;
1482 }
1483
1484 /*
1485 * Set media options.
1486 */
1487 static int
mvgbe_mediachange(struct ifnet * ifp)1488 mvgbe_mediachange(struct ifnet *ifp)
1489 {
1490 return ether_mediachange(ifp);
1491 }
1492
1493 /*
1494 * Report current media status.
1495 */
1496 static void
mvgbe_mediastatus(struct ifnet * ifp,struct ifmediareq * ifmr)1497 mvgbe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
1498 {
1499 ether_mediastatus(ifp, ifmr);
1500 }
1501
1502
1503 static int
mvgbe_init_rx_ring(struct mvgbe_softc * sc)1504 mvgbe_init_rx_ring(struct mvgbe_softc *sc)
1505 {
1506 struct mvgbe_chain_data *cd = &sc->sc_cdata;
1507 struct mvgbe_ring_data *rd = sc->sc_rdata;
1508 int i;
1509
1510 memset(rd->mvgbe_rx_ring, 0,
1511 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT);
1512
1513 for (i = 0; i < MVGBE_RX_RING_CNT; i++) {
1514 cd->mvgbe_rx_chain[i].mvgbe_desc =
1515 &rd->mvgbe_rx_ring[i];
1516 if (i == MVGBE_RX_RING_CNT - 1) {
1517 cd->mvgbe_rx_chain[i].mvgbe_next =
1518 &cd->mvgbe_rx_chain[0];
1519 rd->mvgbe_rx_ring[i].nextdescptr =
1520 H2MVGBE32(MVGBE_RX_RING_ADDR(sc, 0));
1521 } else {
1522 cd->mvgbe_rx_chain[i].mvgbe_next =
1523 &cd->mvgbe_rx_chain[i + 1];
1524 rd->mvgbe_rx_ring[i].nextdescptr =
1525 H2MVGBE32(MVGBE_RX_RING_ADDR(sc, i + 1));
1526 }
1527 }
1528
1529 for (i = 0; i < MVGBE_RX_RING_CNT; i++) {
1530 if (mvgbe_newbuf(sc, i, NULL,
1531 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) {
1532 aprint_error_ifnet(&sc->sc_ethercom.ec_if,
1533 "failed alloc of %dth mbuf\n", i);
1534 return ENOBUFS;
1535 }
1536 }
1537 sc->sc_cdata.mvgbe_rx_prod = 0;
1538 sc->sc_cdata.mvgbe_rx_cons = 0;
1539
1540 return 0;
1541 }
1542
1543 static int
mvgbe_init_tx_ring(struct mvgbe_softc * sc)1544 mvgbe_init_tx_ring(struct mvgbe_softc *sc)
1545 {
1546 struct mvgbe_chain_data *cd = &sc->sc_cdata;
1547 struct mvgbe_ring_data *rd = sc->sc_rdata;
1548 int i;
1549
1550 memset(sc->sc_rdata->mvgbe_tx_ring, 0,
1551 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT);
1552
1553 for (i = 0; i < MVGBE_TX_RING_CNT; i++) {
1554 cd->mvgbe_tx_chain[i].mvgbe_desc =
1555 &rd->mvgbe_tx_ring[i];
1556 if (i == MVGBE_TX_RING_CNT - 1) {
1557 cd->mvgbe_tx_chain[i].mvgbe_next =
1558 &cd->mvgbe_tx_chain[0];
1559 rd->mvgbe_tx_ring[i].nextdescptr =
1560 H2MVGBE32(MVGBE_TX_RING_ADDR(sc, 0));
1561 } else {
1562 cd->mvgbe_tx_chain[i].mvgbe_next =
1563 &cd->mvgbe_tx_chain[i + 1];
1564 rd->mvgbe_tx_ring[i].nextdescptr =
1565 H2MVGBE32(MVGBE_TX_RING_ADDR(sc, i + 1));
1566 }
1567 rd->mvgbe_tx_ring[i].cmdsts =
1568 H2MVGBE32(MVGBE_BUFFER_OWNED_BY_HOST);
1569 }
1570
1571 sc->sc_cdata.mvgbe_tx_prod = 0;
1572 sc->sc_cdata.mvgbe_tx_cons = 0;
1573 sc->sc_cdata.mvgbe_tx_cnt = 0;
1574
1575 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT,
1576 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1577
1578 return 0;
1579 }
1580
1581 static int
mvgbe_newbuf(struct mvgbe_softc * sc,int i,struct mbuf * m,bus_dmamap_t dmamap)1582 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m,
1583 bus_dmamap_t dmamap)
1584 {
1585 struct mbuf *m_new = NULL;
1586 struct mvgbe_chain *c;
1587 struct mvgbe_rx_desc *r;
1588 int align;
1589 vaddr_t offset;
1590 uint16_t bufsize;
1591
1592 if (m == NULL) {
1593 void *buf = NULL;
1594
1595 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1596 if (m_new == NULL) {
1597 aprint_error_ifnet(&sc->sc_ethercom.ec_if,
1598 "no memory for rx list -- packet dropped!\n");
1599 return ENOBUFS;
1600 }
1601
1602 /* Allocate the jumbo buffer */
1603 buf = mvgbe_jalloc(sc);
1604 if (buf == NULL) {
1605 m_freem(m_new);
1606 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
1607 "dropped!\n", sc->sc_ethercom.ec_if.if_xname));
1608 return ENOBUFS;
1609 }
1610
1611 /* Attach the buffer to the mbuf */
1612 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN;
1613 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc);
1614 } else {
1615 /*
1616 * We're re-using a previously allocated mbuf;
1617 * be sure to re-init pointers and lengths to
1618 * default values.
1619 */
1620 m_new = m;
1621 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN;
1622 m_new->m_data = m_new->m_ext.ext_buf;
1623 }
1624 align = (u_long)m_new->m_data & MVGBE_RXBUF_MASK;
1625 if (align != 0) {
1626 DPRINTFN(1,("align = %d\n", align));
1627 m_adj(m_new, MVGBE_RXBUF_ALIGN - align);
1628 }
1629
1630 c = &sc->sc_cdata.mvgbe_rx_chain[i];
1631 r = c->mvgbe_desc;
1632 c->mvgbe_mbuf = m_new;
1633 offset = (vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf;
1634 r->bufptr = H2MVGBE32(dmamap->dm_segs[0].ds_addr + offset);
1635 bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK;
1636 r->bufsize = H2MVGBE16(bufsize);
1637 r->cmdsts =
1638 H2MVGBE32(MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT);
1639
1640 /* Invalidate RX buffer */
1641 bus_dmamap_sync(sc->sc_dmat, dmamap, offset, bufsize,
1642 BUS_DMASYNC_PREREAD);
1643
1644 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1645
1646 return 0;
1647 }
1648
1649 /*
1650 * Memory management for jumbo frames.
1651 */
1652
1653 static int
mvgbe_alloc_jumbo_mem(struct mvgbe_softc * sc)1654 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc)
1655 {
1656 char *ptr, *kva;
1657 bus_dma_segment_t seg;
1658 int i, rseg, state, error;
1659 struct mvgbe_jpool_entry *entry;
1660
1661 state = error = 0;
1662
1663 /* Grab a big chunk o' storage. */
1664 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0,
1665 &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
1666 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n");
1667 return ENOBUFS;
1668 }
1669
1670 state = 1;
1671 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM,
1672 (void **)&kva, BUS_DMA_NOWAIT)) {
1673 aprint_error_dev(sc->sc_dev,
1674 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM);
1675 error = ENOBUFS;
1676 goto out;
1677 }
1678
1679 state = 2;
1680 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0,
1681 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) {
1682 aprint_error_dev(sc->sc_dev, "can't create dma map\n");
1683 error = ENOBUFS;
1684 goto out;
1685 }
1686
1687 state = 3;
1688 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map,
1689 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) {
1690 aprint_error_dev(sc->sc_dev, "can't load dma map\n");
1691 error = ENOBUFS;
1692 goto out;
1693 }
1694
1695 state = 4;
1696 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva;
1697 DPRINTFN(1,("mvgbe_jumbo_buf = %p\n", sc->sc_cdata.mvgbe_jumbo_buf));
1698
1699 LIST_INIT(&sc->sc_jfree_listhead);
1700 LIST_INIT(&sc->sc_jinuse_listhead);
1701
1702 /*
1703 * Now divide it up into 9K pieces and save the addresses
1704 * in an array.
1705 */
1706 ptr = sc->sc_cdata.mvgbe_jumbo_buf;
1707 for (i = 0; i < MVGBE_JSLOTS; i++) {
1708 sc->sc_cdata.mvgbe_jslots[i] = ptr;
1709 ptr += MVGBE_JLEN;
1710 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP);
1711 entry->slot = i;
1712 if (i)
1713 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry,
1714 jpool_entries);
1715 else
1716 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry,
1717 jpool_entries);
1718 }
1719 out:
1720 if (error != 0) {
1721 switch (state) {
1722 case 4:
1723 bus_dmamap_unload(sc->sc_dmat,
1724 sc->sc_cdata.mvgbe_rx_jumbo_map);
1725 case 3:
1726 bus_dmamap_destroy(sc->sc_dmat,
1727 sc->sc_cdata.mvgbe_rx_jumbo_map);
1728 case 2:
1729 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM);
1730 case 1:
1731 bus_dmamem_free(sc->sc_dmat, &seg, rseg);
1732 break;
1733 default:
1734 break;
1735 }
1736 }
1737
1738 return error;
1739 }
1740
1741 /*
1742 * Allocate a jumbo buffer.
1743 */
1744 static void *
mvgbe_jalloc(struct mvgbe_softc * sc)1745 mvgbe_jalloc(struct mvgbe_softc *sc)
1746 {
1747 struct mvgbe_jpool_entry *entry;
1748
1749 entry = LIST_FIRST(&sc->sc_jfree_listhead);
1750
1751 if (entry == NULL)
1752 return NULL;
1753
1754 LIST_REMOVE(entry, jpool_entries);
1755 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries);
1756 return sc->sc_cdata.mvgbe_jslots[entry->slot];
1757 }
1758
1759 /*
1760 * Release a jumbo buffer.
1761 */
1762 static void
mvgbe_jfree(struct mbuf * m,void * buf,size_t size,void * arg)1763 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg)
1764 {
1765 struct mvgbe_jpool_entry *entry;
1766 struct mvgbe_softc *sc;
1767 int i, s;
1768
1769 /* Extract the softc struct pointer. */
1770 sc = (struct mvgbe_softc *)arg;
1771
1772 if (sc == NULL)
1773 panic("%s: can't find softc pointer!", __func__);
1774
1775 /* calculate the slot this buffer belongs to */
1776
1777 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN;
1778
1779 if ((i < 0) || (i >= MVGBE_JSLOTS))
1780 panic("%s: asked to free buffer that we don't manage!",
1781 __func__);
1782
1783 s = splvm();
1784 entry = LIST_FIRST(&sc->sc_jinuse_listhead);
1785 if (entry == NULL)
1786 panic("%s: buffer not in use!", __func__);
1787 entry->slot = i;
1788 LIST_REMOVE(entry, jpool_entries);
1789 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries);
1790
1791 if (__predict_true(m != NULL))
1792 pool_cache_put(mb_cache, m);
1793 splx(s);
1794 }
1795
1796 static int
mvgbe_encap(struct mvgbe_softc * sc,struct mbuf * m_head,uint32_t * txidx)1797 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head,
1798 uint32_t *txidx)
1799 {
1800 struct mvgbe_tx_desc *f = NULL;
1801 struct mvgbe_txmap_entry *entry;
1802 bus_dma_segment_t *txseg;
1803 bus_dmamap_t txmap;
1804 uint32_t first, current, last, cmdsts;
1805 int m_csumflags, i;
1806 bool needs_defrag = false;
1807
1808 DPRINTFN(3, ("mvgbe_encap\n"));
1809
1810 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head);
1811 if (entry == NULL) {
1812 DPRINTFN(2, ("mvgbe_encap: no txmap available\n"));
1813 return ENOBUFS;
1814 }
1815 txmap = entry->dmamap;
1816
1817 first = current = last = *txidx;
1818
1819 /*
1820 * Preserve m_pkthdr.csum_flags here since m_head might be
1821 * updated by m_defrag()
1822 */
1823 m_csumflags = m_head->m_pkthdr.csum_flags;
1824
1825 do_defrag:
1826 if (__predict_false(needs_defrag == true)) {
1827 /* A small unaligned segment was detected. */
1828 struct mbuf *m_new;
1829 m_new = m_defrag(m_head, M_DONTWAIT);
1830 if (m_new == NULL) {
1831 DPRINTFN(2, ("mvgbe_encap: defrag failed\n"));
1832 return EFBIG;
1833 }
1834 m_head = m_new;
1835 }
1836
1837 /*
1838 * Start packing the mbufs in this chain into
1839 * the fragment pointers. Stop when we run out
1840 * of fragments or hit the end of the mbuf chain.
1841 */
1842 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) {
1843 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n"));
1844 return ENOBUFS;
1845 }
1846
1847 txseg = txmap->dm_segs;
1848
1849 if (__predict_true(needs_defrag == false)) {
1850 /*
1851 * Detect rarely encountered DMA limitation.
1852 */
1853 for (i = 0; i < txmap->dm_nsegs; i++) {
1854 if (((txseg[i].ds_addr & 7) != 0) &&
1855 (txseg[i].ds_len <= 8) &&
1856 (txseg[i].ds_len >= 1)
1857 ) {
1858 txseg = NULL;
1859 bus_dmamap_unload(sc->sc_dmat, txmap);
1860 needs_defrag = true;
1861 goto do_defrag;
1862 }
1863 }
1864 }
1865
1866 /* Sync the DMA map. */
1867 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize,
1868 BUS_DMASYNC_PREWRITE);
1869
1870 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >=
1871 MVGBE_TX_RING_CNT) {
1872 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n"));
1873 bus_dmamap_unload(sc->sc_dmat, txmap);
1874 return ENOBUFS;
1875 }
1876
1877
1878 DPRINTFN(3, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs));
1879
1880 for (i = 0; i < txmap->dm_nsegs; i++) {
1881 f = &sc->sc_rdata->mvgbe_tx_ring[current];
1882 f->bufptr = H2MVGBE32(txseg[i].ds_addr);
1883 f->bytecnt = H2MVGBE16(txseg[i].ds_len);
1884 if (i != 0)
1885 f->cmdsts = H2MVGBE32(MVGBE_BUFFER_OWNED_BY_DMA);
1886 last = current;
1887 current = MVGBE_TX_RING_NEXT(current);
1888 }
1889
1890 cmdsts = sc->sc_cmdsts_opts;
1891 if (m_csumflags & M_CSUM_IPv4)
1892 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM;
1893 if (m_csumflags & M_CSUM_TCPv4)
1894 cmdsts |=
1895 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP;
1896 if (m_csumflags & M_CSUM_UDPv4)
1897 cmdsts |=
1898 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP;
1899 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) {
1900 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t);
1901
1902 cmdsts |= MVGBE_TX_IP_NO_FRAG |
1903 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */
1904 }
1905 if (txmap->dm_nsegs == 1)
1906 f->cmdsts = H2MVGBE32(cmdsts |
1907 MVGBE_TX_ENABLE_INTERRUPT |
1908 MVGBE_TX_ZERO_PADDING |
1909 MVGBE_TX_FIRST_DESC |
1910 MVGBE_TX_LAST_DESC);
1911 else {
1912 f = &sc->sc_rdata->mvgbe_tx_ring[first];
1913 f->cmdsts = H2MVGBE32(cmdsts | MVGBE_TX_FIRST_DESC);
1914
1915 f = &sc->sc_rdata->mvgbe_tx_ring[last];
1916 f->cmdsts = H2MVGBE32(
1917 MVGBE_BUFFER_OWNED_BY_DMA |
1918 MVGBE_TX_ENABLE_INTERRUPT |
1919 MVGBE_TX_ZERO_PADDING |
1920 MVGBE_TX_LAST_DESC);
1921
1922 /* Sync descriptors except first */
1923 MVGBE_CDTXSYNC(sc,
1924 (MVGBE_TX_RING_CNT - 1 == *txidx) ? 0 : (*txidx) + 1,
1925 txmap->dm_nsegs - 1,
1926 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1927 }
1928
1929 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head;
1930 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link);
1931 sc->sc_cdata.mvgbe_tx_map[last] = entry;
1932
1933 /* Finally, sync first descriptor */
1934 sc->sc_rdata->mvgbe_tx_ring[first].cmdsts |=
1935 H2MVGBE32(MVGBE_BUFFER_OWNED_BY_DMA);
1936 MVGBE_CDTXSYNC(sc, *txidx, 1,
1937 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1938
1939 sc->sc_cdata.mvgbe_tx_cnt += i;
1940 *txidx = current;
1941
1942 DPRINTFN(3, ("mvgbe_encap: completed successfully\n"));
1943
1944 return 0;
1945 }
1946
1947 static void
mvgbe_rxeof(struct mvgbe_softc * sc)1948 mvgbe_rxeof(struct mvgbe_softc *sc)
1949 {
1950 struct mvgbe_chain_data *cdata = &sc->sc_cdata;
1951 struct mvgbe_rx_desc *cur_rx;
1952 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1953 struct mbuf *m;
1954 bus_dmamap_t dmamap;
1955 uint32_t rxstat;
1956 uint16_t bufsize;
1957 int idx, cur, total_len;
1958
1959 idx = sc->sc_cdata.mvgbe_rx_prod;
1960
1961 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx));
1962
1963 for (;;) {
1964 cur = idx;
1965
1966 /* Sync the descriptor */
1967 MVGBE_CDRXSYNC(sc, idx,
1968 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1969
1970 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx];
1971
1972 rxstat = MVGBE2H32(cur_rx->cmdsts);
1973 if ((rxstat & MVGBE_BUFFER_OWNED_MASK) ==
1974 MVGBE_BUFFER_OWNED_BY_DMA) {
1975 /* Invalidate the descriptor -- it's not ready yet */
1976 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1977 sc->sc_cdata.mvgbe_rx_prod = idx;
1978 break;
1979 }
1980 #ifdef DIAGNOSTIC
1981 if ((rxstat &
1982 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) !=
1983 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC))
1984 panic(
1985 "mvgbe_rxeof: buffer size is smaller than packet");
1986 #endif
1987
1988 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map;
1989
1990 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
1991 BUS_DMASYNC_POSTREAD);
1992
1993 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf;
1994 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL;
1995 total_len = MVGBE2H16(cur_rx->bytecnt) - ETHER_CRC_LEN;
1996 bufsize = MVGBE2H16(cur_rx->bufsize);
1997
1998 cdata->mvgbe_rx_map[idx] = NULL;
1999
2000 idx = MVGBE_RX_RING_NEXT(idx);
2001
2002 if (rxstat & MVGBE_ERROR_SUMMARY) {
2003 #if 0
2004 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK;
2005
2006 if (err == MVGBE_RX_CRC_ERROR)
2007 if_statinc(ifp, if_ierrors);
2008 if (err == MVGBE_RX_OVERRUN_ERROR)
2009 if_statinc(ifp, if_ierrors);
2010 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR)
2011 if_statinc(ifp, if_ierrors);
2012 if (err == MVGBE_RX_RESOURCE_ERROR)
2013 if_statinc(ifp, if_ierrors);
2014 #else
2015 if_statinc(ifp, if_ierrors);
2016 #endif
2017 mvgbe_newbuf(sc, cur, m, dmamap);
2018 continue;
2019 }
2020
2021 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) {
2022 int flgs = 0;
2023
2024 /* Check IPv4 header checksum */
2025 flgs |= M_CSUM_IPv4;
2026 if (!(rxstat & MVGBE_RX_IP_HEADER_OK))
2027 flgs |= M_CSUM_IPv4_BAD;
2028 else if ((bufsize & MVGBE_RX_IP_FRAGMENT) == 0) {
2029 /*
2030 * Check TCPv4/UDPv4 checksum for
2031 * non-fragmented packet only.
2032 *
2033 * It seemd that sometimes
2034 * MVGBE_RX_L4_CHECKSUM_OK bit was set to 0
2035 * even if the checksum is correct and the
2036 * packet was not fragmented. So we don't set
2037 * M_CSUM_TCP_UDP_BAD even if csum bit is 0.
2038 */
2039
2040 if (((rxstat & MVGBE_RX_L4_TYPE_MASK) ==
2041 MVGBE_RX_L4_TYPE_TCP) &&
2042 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0))
2043 flgs |= M_CSUM_TCPv4;
2044 else if (((rxstat & MVGBE_RX_L4_TYPE_MASK) ==
2045 MVGBE_RX_L4_TYPE_UDP) &&
2046 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0))
2047 flgs |= M_CSUM_UDPv4;
2048 }
2049 m->m_pkthdr.csum_flags = flgs;
2050 }
2051
2052 /*
2053 * Try to allocate a new jumbo buffer. If that
2054 * fails, copy the packet to mbufs and put the
2055 * jumbo buffer back in the ring so it can be
2056 * re-used. If allocating mbufs fails, then we
2057 * have to drop the packet.
2058 */
2059 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) {
2060 struct mbuf *m0;
2061
2062 m0 = m_devget(mtod(m, char *), total_len, 0, ifp);
2063 mvgbe_newbuf(sc, cur, m, dmamap);
2064 if (m0 == NULL) {
2065 aprint_error_ifnet(ifp,
2066 "no receive buffers available --"
2067 " packet dropped!\n");
2068 if_statinc(ifp, if_ierrors);
2069 continue;
2070 }
2071 m = m0;
2072 } else {
2073 m_set_rcvif(m, ifp);
2074 m->m_pkthdr.len = m->m_len = total_len;
2075 }
2076
2077 /* Skip on first 2byte (HW header) */
2078 m_adj(m, MVGBE_HWHEADER_SIZE);
2079
2080 /* pass it on. */
2081 if_percpuq_enqueue(ifp->if_percpuq, m);
2082 }
2083 }
2084
2085 static void
mvgbe_txeof(struct mvgbe_softc * sc)2086 mvgbe_txeof(struct mvgbe_softc *sc)
2087 {
2088 struct mvgbe_chain_data *cdata = &sc->sc_cdata;
2089 struct mvgbe_tx_desc *cur_tx;
2090 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2091 struct mvgbe_txmap_entry *entry;
2092 uint32_t txstat;
2093 int idx;
2094
2095 DPRINTFN(3, ("mvgbe_txeof\n"));
2096
2097 /*
2098 * Go through our tx ring and free mbufs for those
2099 * frames that have been sent.
2100 */
2101 idx = cdata->mvgbe_tx_cons;
2102 while (idx != cdata->mvgbe_tx_prod) {
2103 MVGBE_CDTXSYNC(sc, idx, 1,
2104 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2105
2106 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx];
2107 #ifdef MVGBE_DEBUG
2108 if (mvgbe_debug >= 3)
2109 mvgbe_dump_txdesc(cur_tx, idx);
2110 #endif
2111 txstat = MVGBE2H32(cur_tx->cmdsts);
2112 if ((txstat & MVGBE_BUFFER_OWNED_MASK) ==
2113 MVGBE_BUFFER_OWNED_BY_DMA) {
2114 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD);
2115 break;
2116 }
2117 if (txstat & MVGBE_TX_LAST_DESC)
2118 if_statinc(ifp, if_opackets);
2119 if (txstat & MVGBE_ERROR_SUMMARY) {
2120 int err = txstat & MVGBE_TX_ERROR_CODE_MASK;
2121
2122 if (err == MVGBE_TX_LATE_COLLISION_ERROR)
2123 if_statinc(ifp, if_collisions);
2124 if (err == MVGBE_TX_UNDERRUN_ERROR)
2125 if_statinc(ifp, if_oerrors);
2126 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO)
2127 if_statinc(ifp, if_collisions);
2128 }
2129 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) {
2130 entry = cdata->mvgbe_tx_map[idx];
2131
2132 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0,
2133 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2134
2135 bus_dmamap_unload(sc->sc_dmat, entry->dmamap);
2136
2137 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf);
2138 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL;
2139
2140 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link);
2141 cdata->mvgbe_tx_map[idx] = NULL;
2142 }
2143 cdata->mvgbe_tx_cnt--;
2144 idx = MVGBE_TX_RING_NEXT(idx);
2145 }
2146 if (cdata->mvgbe_tx_cnt == 0)
2147 ifp->if_timer = 0;
2148
2149 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2)
2150 ifp->if_flags &= ~IFF_OACTIVE;
2151
2152 cdata->mvgbe_tx_cons = idx;
2153 }
2154
2155 static uint8_t
mvgbe_crc8(const uint8_t * data,size_t size)2156 mvgbe_crc8(const uint8_t *data, size_t size)
2157 {
2158 int bit;
2159 uint8_t byte;
2160 uint8_t crc = 0;
2161 const uint8_t poly = 0x07;
2162
2163 while (size--)
2164 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--)
2165 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0);
2166
2167 return crc;
2168 }
2169
2170 CTASSERT(MVGBE_NDFSMT == MVGBE_NDFOMT);
2171
2172 static void
mvgbe_filter_setup(struct mvgbe_softc * sc)2173 mvgbe_filter_setup(struct mvgbe_softc *sc)
2174 {
2175 struct ethercom *ec = &sc->sc_ethercom;
2176 struct ifnet *ifp= &sc->sc_ethercom.ec_if;
2177 struct ether_multi *enm;
2178 struct ether_multistep step;
2179 uint32_t dfut[MVGBE_NDFUT], dfsmt[MVGBE_NDFSMT], dfomt[MVGBE_NDFOMT];
2180 uint32_t pxc;
2181 int i;
2182 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00};
2183
2184 memset(dfut, 0, sizeof(dfut));
2185 memset(dfsmt, 0, sizeof(dfsmt));
2186 memset(dfomt, 0, sizeof(dfomt));
2187
2188 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
2189 goto allmulti;
2190 }
2191
2192 ETHER_LOCK(ec);
2193 ETHER_FIRST_MULTI(step, ec, enm);
2194 while (enm != NULL) {
2195 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
2196 /* ranges are complex and somewhat rare */
2197 ETHER_UNLOCK(ec);
2198 goto allmulti;
2199 }
2200 /* chip handles some IPv4 multicast specially */
2201 if (memcmp(enm->enm_addrlo, special, 5) == 0) {
2202 i = enm->enm_addrlo[5];
2203 dfsmt[i>>2] |=
2204 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS);
2205 } else {
2206 i = mvgbe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN);
2207 dfomt[i>>2] |=
2208 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS);
2209 }
2210
2211 ETHER_NEXT_MULTI(step, enm);
2212 }
2213 ETHER_UNLOCK(ec);
2214 goto set;
2215
2216 allmulti:
2217 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
2218 for (i = 0; i < MVGBE_NDFSMT; i++) {
2219 dfsmt[i] = dfomt[i] =
2220 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) |
2221 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) |
2222 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) |
2223 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS);
2224 }
2225 }
2226
2227 set:
2228 pxc = MVGBE_READ(sc, MVGBE_PXC);
2229 pxc &= ~MVGBE_PXC_UPM;
2230 pxc |= MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP;
2231 if (ifp->if_flags & IFF_BROADCAST) {
2232 pxc &= ~(MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP);
2233 }
2234 if (ifp->if_flags & IFF_PROMISC) {
2235 pxc |= MVGBE_PXC_UPM;
2236 }
2237 MVGBE_WRITE(sc, MVGBE_PXC, pxc);
2238
2239 /* Set Destination Address Filter Unicast Table */
2240 if (ifp->if_flags & IFF_PROMISC) {
2241 /* pass all unicast addresses */
2242 for (i = 0; i < MVGBE_NDFUT; i++) {
2243 dfut[i] =
2244 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) |
2245 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) |
2246 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) |
2247 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS);
2248 }
2249 } else {
2250 i = sc->sc_enaddr[5] & 0xf; /* last nibble */
2251 dfut[i>>2] = MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS);
2252 }
2253 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, dfut, MVGBE_NDFUT);
2254
2255 /* Set Destination Address Filter Multicast Tables */
2256 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, dfsmt, MVGBE_NDFSMT);
2257 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, dfomt, MVGBE_NDFOMT);
2258 }
2259
2260 #ifdef MVGBE_DEBUG
2261 static void
mvgbe_dump_txdesc(struct mvgbe_tx_desc * desc,int idx)2262 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx)
2263 {
2264 #define DESC_PRINT(X) \
2265 if (X) \
2266 printf("txdesc[%d]." #X "=%#x\n", idx, X);
2267
2268 #ifdef MVGBE_BIG_ENDIAN
2269 DESC_PRINT(desc->bytecnt);
2270 DESC_PRINT(desc->l4ichk);
2271 DESC_PRINT(desc->cmdsts);
2272 DESC_PRINT(desc->nextdescptr);
2273 DESC_PRINT(desc->bufptr);
2274 #else
2275 DESC_PRINT(MVGBE2H32(desc->cmdsts));
2276 DESC_PRINT(MVGBE2H16(desc->l4ichk));
2277 DESC_PRINT(MVGBE2H16(desc->bytecnt));
2278 DESC_PRINT(MVGBE2H32(desc->bufptr));
2279 DESC_PRINT(MVGBE2H32(desc->nextdescptr));
2280 #endif
2281 #undef DESC_PRINT
2282 }
2283 #endif
2284
2285 SYSCTL_SETUP(sysctl_mvgbe, "sysctl mvgbe subtree setup")
2286 {
2287 int rc;
2288 const struct sysctlnode *node;
2289
2290 if ((rc = sysctl_createv(clog, 0, NULL, &node,
2291 0, CTLTYPE_NODE, "mvgbe",
2292 SYSCTL_DESCR("mvgbe interface controls"),
2293 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
2294 goto err;
2295 }
2296
2297 mvgbe_root_num = node->sysctl_num;
2298 return;
2299
2300 err:
2301 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc);
2302 }
2303
2304 static void
sysctl_mvgbe_init(struct mvgbe_softc * sc)2305 sysctl_mvgbe_init(struct mvgbe_softc *sc)
2306 {
2307 const struct sysctlnode *node;
2308 int mvgbe_nodenum;
2309
2310 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node,
2311 0, CTLTYPE_NODE, device_xname(sc->sc_dev),
2312 SYSCTL_DESCR("mvgbe per-controller controls"),
2313 NULL, 0, NULL, 0, CTL_HW, mvgbe_root_num, CTL_CREATE,
2314 CTL_EOL) != 0) {
2315 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n");
2316 return;
2317 }
2318 mvgbe_nodenum = node->sysctl_num;
2319
2320 /* interrupt moderation sysctls */
2321 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node,
2322 CTLFLAG_READWRITE, CTLTYPE_INT, "ipginttx",
2323 SYSCTL_DESCR("mvgbe TX interrupt moderation timer"),
2324 mvgbe_sysctl_ipginttx, 0, (void *)sc,
2325 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE,
2326 CTL_EOL) != 0) {
2327 aprint_normal_dev(sc->sc_dev,
2328 "couldn't create ipginttx sysctl node\n");
2329 }
2330 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node,
2331 CTLFLAG_READWRITE, CTLTYPE_INT, "ipgintrx",
2332 SYSCTL_DESCR("mvgbe RX interrupt moderation timer"),
2333 mvgbe_sysctl_ipgintrx, 0, (void *)sc,
2334 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE,
2335 CTL_EOL) != 0) {
2336 aprint_normal_dev(sc->sc_dev,
2337 "couldn't create ipginttx sysctl node\n");
2338 }
2339 }
2340
2341 static int
mvgbe_sysctl_ipginttx(SYSCTLFN_ARGS)2342 mvgbe_sysctl_ipginttx(SYSCTLFN_ARGS)
2343 {
2344 int error;
2345 unsigned int t;
2346 struct sysctlnode node;
2347 struct mvgbec_softc *csc;
2348 struct mvgbe_softc *sc;
2349
2350 node = *rnode;
2351 sc = node.sysctl_data;
2352 csc = device_private(device_parent(sc->sc_dev));
2353 t = sc->sc_ipginttx;
2354 node.sysctl_data = &t;
2355 error = sysctl_lookup(SYSCTLFN_CALL(&node));
2356 if (error || newp == NULL)
2357 return error;
2358
2359 if (mvgbe_ipginttx(csc, sc, t) < 0)
2360 return EINVAL;
2361 /*
2362 * update the softc with sysctl-changed value, and mark
2363 * for hardware update
2364 */
2365 sc->sc_ipginttx = t;
2366
2367 return 0;
2368 }
2369
2370 static int
mvgbe_sysctl_ipgintrx(SYSCTLFN_ARGS)2371 mvgbe_sysctl_ipgintrx(SYSCTLFN_ARGS)
2372 {
2373 int error;
2374 unsigned int t;
2375 struct sysctlnode node;
2376 struct mvgbec_softc *csc;
2377 struct mvgbe_softc *sc;
2378
2379 node = *rnode;
2380 sc = node.sysctl_data;
2381 csc = device_private(device_parent(sc->sc_dev));
2382 t = sc->sc_ipgintrx;
2383 node.sysctl_data = &t;
2384 error = sysctl_lookup(SYSCTLFN_CALL(&node));
2385 if (error || newp == NULL)
2386 return error;
2387
2388 if (mvgbe_ipgintrx(csc, sc, t) < 0)
2389 return EINVAL;
2390 /*
2391 * update the softc with sysctl-changed value, and mark
2392 * for hardware update
2393 */
2394 sc->sc_ipgintrx = t;
2395
2396 return 0;
2397 }
2398