1 /* $NetBSD: nouveau_nvkm_subdev_bios_perf.c,v 1.3 2021/12/18 23:45:38 riastradh Exp $ */
2
3 /*
4 * Copyright 2012 Nouveau Community
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Martin Peres
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_bios_perf.c,v 1.3 2021/12/18 23:45:38 riastradh Exp $");
28
29 #include <subdev/bios.h>
30 #include <subdev/bios/bit.h>
31 #include <subdev/bios/perf.h>
32 #include <subdev/pci.h>
33
34 u32
nvbios_perf_table(struct nvkm_bios * bios,u8 * ver,u8 * hdr,u8 * cnt,u8 * len,u8 * snr,u8 * ssz)35 nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr,
36 u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
37 {
38 struct bit_entry bit_P;
39 u32 perf = 0;
40
41 if (!bit_entry(bios, 'P', &bit_P)) {
42 if (bit_P.version <= 2) {
43 perf = nvbios_rd32(bios, bit_P.offset + 0);
44 if (perf) {
45 *ver = nvbios_rd08(bios, perf + 0);
46 *hdr = nvbios_rd08(bios, perf + 1);
47 if (*ver >= 0x40 && *ver < 0x41) {
48 *cnt = nvbios_rd08(bios, perf + 5);
49 *len = nvbios_rd08(bios, perf + 2);
50 *snr = nvbios_rd08(bios, perf + 4);
51 *ssz = nvbios_rd08(bios, perf + 3);
52 return perf;
53 } else
54 if (*ver >= 0x20 && *ver < 0x40) {
55 *cnt = nvbios_rd08(bios, perf + 2);
56 *len = nvbios_rd08(bios, perf + 3);
57 *snr = nvbios_rd08(bios, perf + 4);
58 *ssz = nvbios_rd08(bios, perf + 5);
59 return perf;
60 }
61 }
62 }
63 }
64
65 if (bios->bmp_offset) {
66 if (nvbios_rd08(bios, bios->bmp_offset + 6) >= 0x25) {
67 perf = nvbios_rd16(bios, bios->bmp_offset + 0x94);
68 if (perf) {
69 *hdr = nvbios_rd08(bios, perf + 0);
70 *ver = nvbios_rd08(bios, perf + 1);
71 *cnt = nvbios_rd08(bios, perf + 2);
72 *len = nvbios_rd08(bios, perf + 3);
73 *snr = 0;
74 *ssz = 0;
75 return perf;
76 }
77 }
78 }
79
80 return 0;
81 }
82
83 u32
nvbios_perf_entry(struct nvkm_bios * bios,int idx,u8 * ver,u8 * hdr,u8 * cnt,u8 * len)84 nvbios_perf_entry(struct nvkm_bios *bios, int idx,
85 u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
86 {
87 u8 snr, ssz;
88 u32 perf = nvbios_perf_table(bios, ver, hdr, cnt, len, &snr, &ssz);
89 if (perf && idx < *cnt) {
90 perf = perf + *hdr + (idx * (*len + (snr * ssz)));
91 *hdr = *len;
92 *cnt = snr;
93 *len = ssz;
94 return perf;
95 }
96 return 0;
97 }
98
99 u32
nvbios_perfEp(struct nvkm_bios * bios,int idx,u8 * ver,u8 * hdr,u8 * cnt,u8 * len,struct nvbios_perfE * info)100 nvbios_perfEp(struct nvkm_bios *bios, int idx,
101 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *info)
102 {
103 u32 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len);
104 memset(info, 0x00, sizeof(*info));
105 info->pstate = nvbios_rd08(bios, perf + 0x00);
106 switch (!!perf * *ver) {
107 case 0x12:
108 case 0x13:
109 case 0x14:
110 info->core = nvbios_rd32(bios, perf + 0x01) * 10;
111 info->memory = nvbios_rd32(bios, perf + 0x05) * 20;
112 info->fanspeed = nvbios_rd08(bios, perf + 0x37);
113 if (*hdr > 0x38)
114 info->voltage = nvbios_rd08(bios, perf + 0x38);
115 break;
116 case 0x21:
117 case 0x23:
118 case 0x24:
119 info->fanspeed = nvbios_rd08(bios, perf + 0x04);
120 info->voltage = nvbios_rd08(bios, perf + 0x05);
121 info->shader = nvbios_rd16(bios, perf + 0x06) * 1000;
122 info->core = info->shader + (signed char)
123 nvbios_rd08(bios, perf + 0x08) * 1000;
124 switch (bios->subdev.device->chipset) {
125 case 0x49:
126 case 0x4b:
127 info->memory = nvbios_rd16(bios, perf + 0x0b) * 1000;
128 break;
129 default:
130 info->memory = nvbios_rd16(bios, perf + 0x0b) * 2000;
131 break;
132 }
133 break;
134 case 0x25:
135 info->fanspeed = nvbios_rd08(bios, perf + 0x04);
136 info->voltage = nvbios_rd08(bios, perf + 0x05);
137 info->core = nvbios_rd16(bios, perf + 0x06) * 1000;
138 info->shader = nvbios_rd16(bios, perf + 0x0a) * 1000;
139 info->memory = nvbios_rd16(bios, perf + 0x0c) * 1000;
140 break;
141 case 0x30:
142 info->script = nvbios_rd16(bios, perf + 0x02);
143 /* fall through */
144 case 0x35:
145 info->fanspeed = nvbios_rd08(bios, perf + 0x06);
146 info->voltage = nvbios_rd08(bios, perf + 0x07);
147 info->core = nvbios_rd16(bios, perf + 0x08) * 1000;
148 info->shader = nvbios_rd16(bios, perf + 0x0a) * 1000;
149 info->memory = nvbios_rd16(bios, perf + 0x0c) * 1000;
150 info->vdec = nvbios_rd16(bios, perf + 0x10) * 1000;
151 info->disp = nvbios_rd16(bios, perf + 0x14) * 1000;
152 break;
153 case 0x40:
154 info->voltage = nvbios_rd08(bios, perf + 0x02);
155 switch (nvbios_rd08(bios, perf + 0xb) & 0x3) {
156 case 0:
157 info->pcie_speed = NVKM_PCIE_SPEED_5_0;
158 break;
159 case 3:
160 case 1:
161 info->pcie_speed = NVKM_PCIE_SPEED_2_5;
162 break;
163 case 2:
164 info->pcie_speed = NVKM_PCIE_SPEED_8_0;
165 break;
166 default:
167 break;
168 }
169 info->pcie_width = 0xff;
170 break;
171 default:
172 return 0;
173 }
174 return perf;
175 }
176
177 u32
nvbios_perfSe(struct nvkm_bios * bios,u32 perfE,int idx,u8 * ver,u8 * hdr,u8 cnt,u8 len)178 nvbios_perfSe(struct nvkm_bios *bios, u32 perfE, int idx,
179 u8 *ver, u8 *hdr, u8 cnt, u8 len)
180 {
181 u32 data = 0x00000000;
182 if (idx < cnt) {
183 data = perfE + *hdr + (idx * len);
184 *hdr = len;
185 }
186 return data;
187 }
188
189 u32
nvbios_perfSp(struct nvkm_bios * bios,u32 perfE,int idx,u8 * ver,u8 * hdr,u8 cnt,u8 len,struct nvbios_perfS * info)190 nvbios_perfSp(struct nvkm_bios *bios, u32 perfE, int idx,
191 u8 *ver, u8 *hdr, u8 cnt, u8 len,
192 struct nvbios_perfS *info)
193 {
194 u32 data = nvbios_perfSe(bios, perfE, idx, ver, hdr, cnt, len);
195 memset(info, 0x00, sizeof(*info));
196 switch (!!data * *ver) {
197 case 0x40:
198 info->v40.freq = (nvbios_rd16(bios, data + 0x00) & 0x3fff) * 1000;
199 break;
200 default:
201 break;
202 }
203 return data;
204 }
205
206 int
nvbios_perf_fan_parse(struct nvkm_bios * bios,struct nvbios_perf_fan * fan)207 nvbios_perf_fan_parse(struct nvkm_bios *bios,
208 struct nvbios_perf_fan *fan)
209 {
210 u8 ver, hdr, cnt, len, snr, ssz;
211 u32 perf = nvbios_perf_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
212 if (!perf)
213 return -ENODEV;
214
215 if (ver >= 0x20 && ver < 0x40 && hdr > 6)
216 fan->pwm_divisor = nvbios_rd16(bios, perf + 6);
217 else
218 fan->pwm_divisor = 0;
219
220 return 0;
221 }
222