1/*
2 * Spreadtrum SC9860 SoC
3 *
4 * Copyright (C) 2016, Spreadtrum Communications Inc.
5 *
6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/gpio/gpio.h>
12#include "whale2.dtsi"
13
14/ {
15	cpus {
16		#address-cells = <2>;
17		#size-cells = <0>;
18
19		cpu-map {
20			cluster0 {
21				core0 {
22					cpu = <&CPU0>;
23				};
24				core1 {
25					cpu = <&CPU1>;
26				};
27				core2 {
28					cpu = <&CPU2>;
29				};
30				core3 {
31					cpu = <&CPU3>;
32				};
33			};
34
35			cluster1 {
36				core0 {
37					cpu = <&CPU4>;
38				};
39				core1 {
40					cpu = <&CPU5>;
41				};
42				core2 {
43					cpu = <&CPU6>;
44				};
45				core3 {
46					cpu = <&CPU7>;
47				};
48			};
49		};
50
51		CPU0: cpu@530000 {
52			device_type = "cpu";
53			compatible = "arm,cortex-a53";
54			reg = <0x0 0x530000>;
55			enable-method = "psci";
56			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
57		};
58
59		CPU1: cpu@530001 {
60			device_type = "cpu";
61			compatible = "arm,cortex-a53";
62			reg = <0x0 0x530001>;
63			enable-method = "psci";
64			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
65		};
66
67		CPU2: cpu@530002 {
68			device_type = "cpu";
69			compatible = "arm,cortex-a53";
70			reg = <0x0 0x530002>;
71			enable-method = "psci";
72			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
73		};
74
75		CPU3: cpu@530003 {
76			device_type = "cpu";
77			compatible = "arm,cortex-a53";
78			reg = <0x0 0x530003>;
79			enable-method = "psci";
80			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
81		};
82
83		CPU4: cpu@530100 {
84			device_type = "cpu";
85			compatible = "arm,cortex-a53";
86			reg = <0x0 0x530100>;
87			enable-method = "psci";
88			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
89		};
90
91		CPU5: cpu@530101 {
92			device_type = "cpu";
93			compatible = "arm,cortex-a53";
94			reg = <0x0 0x530101>;
95			enable-method = "psci";
96			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
97		};
98
99		CPU6: cpu@530102 {
100			device_type = "cpu";
101			compatible = "arm,cortex-a53";
102			reg = <0x0 0x530102>;
103			enable-method = "psci";
104			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
105		};
106
107		CPU7: cpu@530103 {
108			device_type = "cpu";
109			compatible = "arm,cortex-a53";
110			reg = <0x0 0x530103>;
111			enable-method = "psci";
112			cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
113		};
114	};
115
116	idle-states{
117		entry-method = "psci";
118
119		CORE_PD: core_pd {
120			compatible = "arm,idle-state";
121			entry-latency-us = <1000>;
122			exit-latency-us = <700>;
123			min-residency-us = <2500>;
124			local-timer-stop;
125			arm,psci-suspend-param = <0x00010002>;
126		};
127
128		CLUSTER_PD: cluster_pd {
129			compatible = "arm,idle-state";
130			entry-latency-us = <1000>;
131			exit-latency-us = <1000>;
132			min-residency-us = <3000>;
133			local-timer-stop;
134			arm,psci-suspend-param = <0x01010003>;
135		};
136	};
137
138	gic: interrupt-controller@12001000 {
139		compatible = "arm,gic-400";
140		reg = <0 0x12001000 0 0x1000>,
141		      <0 0x12002000 0 0x2000>,
142		      <0 0x12004000 0 0x2000>,
143		      <0 0x12006000 0 0x2000>;
144		#interrupt-cells = <3>;
145		interrupt-controller;
146		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
147					| IRQ_TYPE_LEVEL_HIGH)>;
148	};
149
150	psci {
151		compatible = "arm,psci-0.2";
152		method = "smc";
153	};
154
155	timer {
156		compatible = "arm,armv8-timer";
157		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
158					 | IRQ_TYPE_LEVEL_LOW)>,
159			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
160					 | IRQ_TYPE_LEVEL_LOW)>,
161			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
162					 | IRQ_TYPE_LEVEL_LOW)>,
163			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
164					 | IRQ_TYPE_LEVEL_LOW)>;
165	};
166
167	pmu {
168		compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
169		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
170			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
171			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
172			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
173			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
174			     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
175			     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
176			     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
177		interrupt-affinity = <&CPU0>,
178				     <&CPU1>,
179				     <&CPU2>,
180				     <&CPU3>,
181				     <&CPU4>,
182				     <&CPU5>,
183				     <&CPU6>,
184				     <&CPU7>;
185	};
186
187	soc {
188		pmu_gate: pmu-gate {
189			compatible = "sprd,sc9860-pmu-gate";
190			sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
191			clocks = <&ext_26m>;
192			#clock-cells = <1>;
193		};
194
195		pll: pll {
196			compatible = "sprd,sc9860-pll";
197			sprd,syscon = <&ana_regs>; /* 0x40400000 */
198			clocks = <&pmu_gate 0>;
199			#clock-cells = <1>;
200		};
201
202		ap_clk: clock-controller@20000000 {
203			compatible = "sprd,sc9860-ap-clk";
204			reg = <0 0x20000000 0 0x400>;
205			clocks = <&ext_26m>, <&pll 0>,
206				 <&pmu_gate 0>;
207			#clock-cells = <1>;
208		};
209
210		aon_prediv: aon-prediv {
211			compatible = "sprd,sc9860-aon-prediv";
212			reg = <0 0x402d0000 0 0x400>;
213			clocks = <&ext_26m>, <&pll 0>,
214				 <&pmu_gate 0>;
215			#clock-cells = <1>;
216		};
217
218		apahb_gate: apahb-gate {
219			compatible = "sprd,sc9860-apahb-gate";
220			sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */
221			clocks = <&aon_prediv 0>;
222			#clock-cells = <1>;
223		};
224
225		aon_gate: aon-gate {
226			compatible = "sprd,sc9860-aon-gate";
227			sprd,syscon = <&aon_regs>; /* 0x402e0000 */
228			clocks = <&aon_prediv 0>;
229			#clock-cells = <1>;
230		};
231
232		aonsecure_clk: clock-controller@40880000 {
233			compatible = "sprd,sc9860-aonsecure-clk";
234			reg = <0 0x40880000 0 0x400>;
235			clocks = <&ext_26m>, <&pll 0>;
236			#clock-cells = <1>;
237		};
238
239		agcp_gate: agcp-gate {
240			compatible = "sprd,sc9860-agcp-gate";
241			sprd,syscon = <&agcp_regs>; /* 0x415e0000 */
242			clocks = <&aon_prediv 0>;
243			#clock-cells = <1>;
244		};
245
246		gpu_clk: clock-controller@60200000 {
247			compatible = "sprd,sc9860-gpu-clk";
248			reg = <0 0x60200000 0 0x400>;
249			clocks = <&pll 0>;
250			#clock-cells = <1>;
251		};
252
253		vsp_clk: clock-controller@61000000 {
254			compatible = "sprd,sc9860-vsp-clk";
255			reg = <0 0x61000000 0 0x400>;
256			clocks = <&ext_26m>, <&pll 0>;
257			#clock-cells = <1>;
258		};
259
260		vsp_gate: vsp-gate {
261			compatible = "sprd,sc9860-vsp-gate";
262			sprd,syscon = <&vsp_regs>; /* 0x61100000 */
263			clocks = <&vsp_clk 0>;
264			#clock-cells = <1>;
265		};
266
267		cam_clk: clock-controller@62000000 {
268			compatible = "sprd,sc9860-cam-clk";
269			reg = <0 0x62000000 0 0x4000>;
270			clocks = <&ext_26m>, <&pll 0>;
271			#clock-cells = <1>;
272		};
273
274		cam_gate: cam-gate {
275			compatible = "sprd,sc9860-cam-gate";
276			sprd,syscon = <&cam_regs>; /* 0x62100000 */
277			clocks = <&cam_clk 0>;
278			#clock-cells = <1>;
279		};
280
281		disp_clk: clock-controller@63000000 {
282			compatible = "sprd,sc9860-disp-clk";
283			reg = <0 0x63000000 0 0x400>;
284			clocks = <&ext_26m>, <&pll 0>;
285			#clock-cells = <1>;
286		};
287
288		disp_gate: disp-gate {
289			compatible = "sprd,sc9860-disp-gate";
290			sprd,syscon = <&disp_regs>; /* 0x63100000 */
291			clocks = <&disp_clk 0>;
292			#clock-cells = <1>;
293		};
294
295		apapb_gate: apapb-gate {
296			compatible = "sprd,sc9860-apapb-gate";
297			sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */
298			clocks = <&ap_clk 0>;
299			#clock-cells = <1>;
300		};
301
302		funnel@10001000 { /* SoC Funnel */
303			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
304			reg = <0 0x10001000 0 0x1000>;
305			clocks = <&ext_26m>;
306			clock-names = "apb_pclk";
307			out-ports {
308				port {
309					soc_funnel_out_port: endpoint {
310						remote-endpoint = <&etb_in>;
311					};
312				};
313			};
314
315			in-ports {
316				#address-cells = <1>;
317				#size-cells = <0>;
318
319				port@0 {
320					reg = <0>;
321					soc_funnel_in_port0: endpoint {
322						remote-endpoint =
323						<&main_funnel_out_port>;
324					};
325				};
326
327				port@4 {
328					reg = <4>;
329					soc_funnel_in_port1: endpoint {
330						remote-endpoint =
331							<&stm_out_port>;
332					};
333				};
334			};
335		};
336
337		etb@10003000 {
338			compatible = "arm,coresight-tmc", "arm,primecell";
339			reg = <0 0x10003000 0 0x1000>;
340			clocks = <&ext_26m>;
341			clock-names = "apb_pclk";
342			out-ports {
343				port {
344					etb_in: endpoint {
345						remote-endpoint =
346							<&soc_funnel_out_port>;
347					};
348				};
349			};
350		};
351
352		stm@10006000 {
353			compatible = "arm,coresight-stm", "arm,primecell";
354			reg = <0 0x10006000 0 0x1000>,
355			      <0 0x01000000 0 0x180000>;
356			reg-names = "stm-base", "stm-stimulus-base";
357			clocks = <&ext_26m>;
358			clock-names = "apb_pclk";
359			out-ports {
360				port {
361					stm_out_port: endpoint {
362						remote-endpoint =
363							<&soc_funnel_in_port1>;
364					};
365				};
366			};
367		};
368
369		funnel@11001000 { /* Cluster0 Funnel */
370			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
371			reg = <0 0x11001000 0 0x1000>;
372			clocks = <&ext_26m>;
373			clock-names = "apb_pclk";
374			out-ports {
375				port {
376					cluster0_funnel_out_port: endpoint {
377						remote-endpoint =
378							<&cluster0_etf_in>;
379					};
380				};
381			};
382
383			in-ports {
384				#address-cells = <1>;
385				#size-cells = <0>;
386
387				port@0 {
388					reg = <0>;
389					cluster0_funnel_in_port0: endpoint {
390						remote-endpoint = <&etm0_out>;
391					};
392				};
393
394				port@1 {
395					reg = <1>;
396					cluster0_funnel_in_port1: endpoint {
397						remote-endpoint = <&etm1_out>;
398					};
399				};
400
401				port@2 {
402					reg = <2>;
403					cluster0_funnel_in_port2: endpoint {
404						remote-endpoint = <&etm2_out>;
405					};
406				};
407
408				port@4 {
409					reg = <4>;
410					cluster0_funnel_in_port3: endpoint {
411						remote-endpoint = <&etm3_out>;
412					};
413				};
414			};
415		};
416
417		funnel@11002000 { /* Cluster1 Funnel */
418			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
419			reg = <0 0x11002000 0 0x1000>;
420			clocks = <&ext_26m>;
421			clock-names = "apb_pclk";
422			out-ports {
423				port {
424					cluster1_funnel_out_port: endpoint {
425						remote-endpoint =
426							<&cluster1_etf_in>;
427					};
428				};
429			};
430
431			in-ports {
432				#address-cells = <1>;
433				#size-cells = <0>;
434
435				port@0 {
436					reg = <0>;
437					cluster1_funnel_in_port0: endpoint {
438						remote-endpoint = <&etm4_out>;
439					};
440				};
441
442				port@1 {
443					reg = <1>;
444					cluster1_funnel_in_port1: endpoint {
445						remote-endpoint = <&etm5_out>;
446					};
447				};
448
449				port@2 {
450					reg = <2>;
451					cluster1_funnel_in_port2: endpoint {
452						remote-endpoint = <&etm6_out>;
453					};
454				};
455
456				port@3 {
457					reg = <3>;
458					cluster1_funnel_in_port3: endpoint {
459						remote-endpoint = <&etm7_out>;
460					};
461				};
462			};
463		};
464
465		etf@11003000 { /*  ETF on Cluster0 */
466			compatible = "arm,coresight-tmc", "arm,primecell";
467			reg = <0 0x11003000 0 0x1000>;
468			clocks = <&ext_26m>;
469			clock-names = "apb_pclk";
470
471			out-ports {
472				port {
473					cluster0_etf_out: endpoint {
474						remote-endpoint =
475						<&main_funnel_in_port0>;
476					};
477				};
478			};
479
480			in-ports {
481				port {
482					cluster0_etf_in: endpoint {
483						remote-endpoint =
484						<&cluster0_funnel_out_port>;
485					};
486				};
487			};
488		};
489
490		etf@11004000 { /* ETF on Cluster1 */
491			compatible = "arm,coresight-tmc", "arm,primecell";
492			reg = <0 0x11004000 0 0x1000>;
493			clocks = <&ext_26m>;
494			clock-names = "apb_pclk";
495
496			out-ports {
497				port {
498					cluster1_etf_out: endpoint {
499						remote-endpoint =
500						<&main_funnel_in_port1>;
501					};
502				};
503			};
504
505			in-ports {
506				port {
507					cluster1_etf_in: endpoint {
508						remote-endpoint =
509						<&cluster1_funnel_out_port>;
510					};
511				};
512			};
513		};
514
515		funnel@11005000 { /* Main Funnel */
516			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
517			reg = <0 0x11005000 0 0x1000>;
518			clocks = <&ext_26m>;
519			clock-names = "apb_pclk";
520
521			out-ports {
522				port {
523					main_funnel_out_port: endpoint {
524						remote-endpoint =
525							<&soc_funnel_in_port0>;
526					};
527				};
528			};
529
530			in-ports {
531				#address-cells = <1>;
532				#size-cells = <0>;
533
534				port@0 {
535					reg = <0>;
536					main_funnel_in_port0: endpoint {
537						remote-endpoint =
538							<&cluster0_etf_out>;
539					};
540				};
541
542				port@1 {
543					reg = <1>;
544					main_funnel_in_port1: endpoint {
545						remote-endpoint =
546							<&cluster1_etf_out>;
547					};
548				};
549			};
550		};
551
552		etm@11440000 {
553			compatible = "arm,coresight-etm4x", "arm,primecell";
554			reg = <0 0x11440000 0 0x1000>;
555			cpu = <&CPU0>;
556			clocks = <&ext_26m>;
557			clock-names = "apb_pclk";
558
559			out-ports {
560				port {
561					etm0_out: endpoint {
562						remote-endpoint =
563							<&cluster0_funnel_in_port0>;
564					};
565				};
566			};
567		};
568
569		etm@11540000 {
570			compatible = "arm,coresight-etm4x", "arm,primecell";
571			reg = <0 0x11540000 0 0x1000>;
572			cpu = <&CPU1>;
573			clocks = <&ext_26m>;
574			clock-names = "apb_pclk";
575
576			out-ports {
577				port {
578					etm1_out: endpoint {
579						remote-endpoint =
580							<&cluster0_funnel_in_port1>;
581					};
582				};
583			};
584		};
585
586		etm@11640000 {
587			compatible = "arm,coresight-etm4x", "arm,primecell";
588			reg = <0 0x11640000 0 0x1000>;
589			cpu = <&CPU2>;
590			clocks = <&ext_26m>;
591			clock-names = "apb_pclk";
592
593			out-ports {
594				port {
595					etm2_out: endpoint {
596						remote-endpoint =
597							<&cluster0_funnel_in_port2>;
598					};
599				};
600			};
601		};
602
603		etm@11740000 {
604			compatible = "arm,coresight-etm4x", "arm,primecell";
605			reg = <0 0x11740000 0 0x1000>;
606			cpu = <&CPU3>;
607			clocks = <&ext_26m>;
608			clock-names = "apb_pclk";
609
610			out-ports {
611				port {
612					etm3_out: endpoint {
613						remote-endpoint =
614							<&cluster0_funnel_in_port3>;
615					};
616				};
617			};
618		};
619
620		etm@11840000 {
621			compatible = "arm,coresight-etm4x", "arm,primecell";
622			reg = <0 0x11840000 0 0x1000>;
623			cpu = <&CPU4>;
624			clocks = <&ext_26m>;
625			clock-names = "apb_pclk";
626
627			out-ports {
628				port {
629					etm4_out: endpoint {
630						remote-endpoint =
631							<&cluster1_funnel_in_port0>;
632					};
633				};
634			};
635		};
636
637		etm@11940000 {
638			compatible = "arm,coresight-etm4x", "arm,primecell";
639			reg = <0 0x11940000 0 0x1000>;
640			cpu = <&CPU5>;
641			clocks = <&ext_26m>;
642			clock-names = "apb_pclk";
643
644			out-ports {
645				port {
646					etm5_out: endpoint {
647						remote-endpoint =
648							<&cluster1_funnel_in_port1>;
649					};
650				};
651			};
652		};
653
654		etm@11a40000 {
655			compatible = "arm,coresight-etm4x", "arm,primecell";
656			reg = <0 0x11a40000 0 0x1000>;
657			cpu = <&CPU6>;
658			clocks = <&ext_26m>;
659			clock-names = "apb_pclk";
660
661			out-ports {
662				port {
663					etm6_out: endpoint {
664						remote-endpoint =
665							<&cluster1_funnel_in_port2>;
666					};
667				};
668			};
669		};
670
671		etm@11b40000 {
672			compatible = "arm,coresight-etm4x", "arm,primecell";
673			reg = <0 0x11b40000 0 0x1000>;
674			cpu = <&CPU7>;
675			clocks = <&ext_26m>;
676			clock-names = "apb_pclk";
677
678			out-ports {
679				port {
680					etm7_out: endpoint {
681						remote-endpoint =
682							<&cluster1_funnel_in_port3>;
683					};
684				};
685			};
686		};
687
688		gpio-keys {
689			compatible = "gpio-keys";
690
691			key-volumedown {
692				label = "Volume Down Key";
693				linux,code = <KEY_VOLUMEDOWN>;
694				gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>;
695				debounce-interval = <2>;
696				wakeup-source;
697			};
698
699			key-volumeup {
700				label = "Volume Up Key";
701				linux,code = <KEY_VOLUMEUP>;
702				gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>;
703				debounce-interval = <2>;
704				wakeup-source;
705			};
706
707			key-power {
708				label = "Power Key";
709				linux,code = <KEY_POWER>;
710				gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>;
711				debounce-interval = <2>;
712				wakeup-source;
713			};
714		};
715	};
716};
717