xref: /openbsd/gnu/gcc/gcc/config/frv/predicates.md (revision 404b540a) 
1;; Predicate definitions for Frv.
2;; Copyright (C) 2005 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 2, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING.  If not, write to
18;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19;; Boston, MA 02110-1301, USA.
20
21;; Return true if operand is a GPR register.
22
23(define_predicate "integer_register_operand"
24  (match_code "reg,subreg")
25{
26  if (GET_MODE (op) != mode && mode != VOIDmode)
27    return FALSE;
28
29  if (GET_CODE (op) == SUBREG)
30    {
31      if (GET_CODE (SUBREG_REG (op)) != REG)
32	return register_operand (op, mode);
33
34      op = SUBREG_REG (op);
35    }
36
37  if (GET_CODE (op) != REG)
38    return FALSE;
39
40  return GPR_AP_OR_PSEUDO_P (REGNO (op));
41})
42
43;; Return 1 is OP is a memory operand, or will be turned into one by
44;; reload.
45
46(define_predicate "frv_load_operand"
47  (match_code "reg,subreg,mem")
48{
49  if (GET_MODE (op) != mode && mode != VOIDmode)
50    return FALSE;
51
52  if (reload_in_progress)
53    {
54      rtx tmp = op;
55      if (GET_CODE (tmp) == SUBREG)
56	tmp = SUBREG_REG (tmp);
57      if (GET_CODE (tmp) == REG
58	  && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
59	op = reg_equiv_memory_loc[REGNO (tmp)];
60    }
61
62  return op && memory_operand (op, mode);
63})
64
65;; Return true if operand is a GPR register.  Do not allow SUBREG's
66;; here, in order to prevent a combine bug.
67
68(define_predicate "gpr_no_subreg_operand"
69  (match_code "reg")
70{
71  if (GET_MODE (op) != mode && mode != VOIDmode)
72    return FALSE;
73
74  if (GET_CODE (op) != REG)
75    return FALSE;
76
77  return GPR_OR_PSEUDO_P (REGNO (op));
78})
79
80;; Return 1 if operand is a GPR register or a FPR register.
81
82(define_predicate "gpr_or_fpr_operand"
83  (match_code "reg,subreg")
84{
85  int regno;
86
87  if (GET_MODE (op) != mode && mode != VOIDmode)
88    return FALSE;
89
90  if (GET_CODE (op) == SUBREG)
91    {
92      if (GET_CODE (SUBREG_REG (op)) != REG)
93	return register_operand (op, mode);
94
95      op = SUBREG_REG (op);
96    }
97
98  if (GET_CODE (op) != REG)
99    return FALSE;
100
101  regno = REGNO (op);
102  if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
103    return TRUE;
104
105  return FALSE;
106})
107
108;; Return 1 if operand is a GPR register or 12 bit signed immediate.
109
110(define_predicate "gpr_or_int12_operand"
111  (match_code "reg,subreg,const_int,const")
112{
113  if (GET_CODE (op) == CONST_INT)
114    return IN_RANGE_P (INTVAL (op), -2048, 2047);
115
116  if (got12_operand (op, mode))
117    return true;
118
119  if (GET_MODE (op) != mode && mode != VOIDmode)
120    return FALSE;
121
122  if (GET_CODE (op) == SUBREG)
123    {
124      if (GET_CODE (SUBREG_REG (op)) != REG)
125	return register_operand (op, mode);
126
127      op = SUBREG_REG (op);
128    }
129
130  if (GET_CODE (op) != REG)
131    return FALSE;
132
133  return GPR_OR_PSEUDO_P (REGNO (op));
134})
135
136;; Return 1 if operand is a GPR register, or a FPR register, or a 12
137;; bit signed immediate.
138
139(define_predicate "gpr_fpr_or_int12_operand"
140  (match_code "reg,subreg,const_int")
141{
142  int regno;
143
144  if (GET_CODE (op) == CONST_INT)
145    return IN_RANGE_P (INTVAL (op), -2048, 2047);
146
147  if (GET_MODE (op) != mode && mode != VOIDmode)
148    return FALSE;
149
150  if (GET_CODE (op) == SUBREG)
151    {
152      if (GET_CODE (SUBREG_REG (op)) != REG)
153	return register_operand (op, mode);
154
155      op = SUBREG_REG (op);
156    }
157
158  if (GET_CODE (op) != REG)
159    return FALSE;
160
161  regno = REGNO (op);
162  if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
163    return TRUE;
164
165  return FALSE;
166})
167
168;; Return 1 if operand is a register or 10 bit signed immediate.
169
170(define_predicate "gpr_or_int10_operand"
171  (match_code "reg,subreg,const_int")
172{
173  if (GET_CODE (op) == CONST_INT)
174    return IN_RANGE_P (INTVAL (op), -512, 511);
175
176  if (GET_MODE (op) != mode && mode != VOIDmode)
177    return FALSE;
178
179  if (GET_CODE (op) == SUBREG)
180    {
181      if (GET_CODE (SUBREG_REG (op)) != REG)
182	return register_operand (op, mode);
183
184      op = SUBREG_REG (op);
185    }
186
187  if (GET_CODE (op) != REG)
188    return FALSE;
189
190  return GPR_OR_PSEUDO_P (REGNO (op));
191})
192
193;; Return 1 if operand is a register or an integer immediate.
194
195(define_predicate "gpr_or_int_operand"
196  (match_code "reg,subreg,const_int")
197{
198  if (GET_CODE (op) == CONST_INT)
199    return TRUE;
200
201  if (GET_MODE (op) != mode && mode != VOIDmode)
202    return FALSE;
203
204  if (GET_CODE (op) == SUBREG)
205    {
206      if (GET_CODE (SUBREG_REG (op)) != REG)
207	return register_operand (op, mode);
208
209      op = SUBREG_REG (op);
210    }
211
212  if (GET_CODE (op) != REG)
213    return FALSE;
214
215  return GPR_OR_PSEUDO_P (REGNO (op));
216})
217
218;; Return true if operand is something that can be an input for a move
219;; operation.
220
221(define_predicate "move_source_operand"
222  (match_code "reg,subreg,const_int,mem,const_double,const,symbol_ref,label_ref")
223{
224  rtx subreg;
225  enum rtx_code code;
226
227  switch (GET_CODE (op))
228    {
229    default:
230      break;
231
232    case CONST_INT:
233    case CONST_DOUBLE:
234      return immediate_operand (op, mode);
235
236    case SUBREG:
237      if (GET_MODE (op) != mode && mode != VOIDmode)
238        return FALSE;
239
240      subreg = SUBREG_REG (op);
241      code = GET_CODE (subreg);
242      if (code == MEM)
243	return frv_legitimate_address_p (mode, XEXP (subreg, 0),
244					 reload_completed, FALSE, FALSE);
245
246      return (code == REG);
247
248    case REG:
249      if (GET_MODE (op) != mode && mode != VOIDmode)
250        return FALSE;
251
252      return TRUE;
253
254    case MEM:
255      return frv_legitimate_memory_operand (op, mode, FALSE);
256    }
257
258  return FALSE;
259})
260
261;; Return true if operand is something that can be an output for a
262;; move operation.
263
264(define_predicate "move_destination_operand"
265  (match_code "reg,subreg,mem")
266{
267  rtx subreg;
268  enum rtx_code code;
269
270  switch (GET_CODE (op))
271    {
272    default:
273      break;
274
275    case SUBREG:
276      if (GET_MODE (op) != mode && mode != VOIDmode)
277        return FALSE;
278
279      subreg = SUBREG_REG (op);
280      code = GET_CODE (subreg);
281      if (code == MEM)
282	return frv_legitimate_address_p (mode, XEXP (subreg, 0),
283					 reload_completed, FALSE, FALSE);
284
285      return (code == REG);
286
287    case REG:
288      if (GET_MODE (op) != mode && mode != VOIDmode)
289        return FALSE;
290
291      return TRUE;
292
293    case MEM:
294      return frv_legitimate_memory_operand (op, mode, FALSE);
295    }
296
297  return FALSE;
298})
299
300;; Return true if we the operand is a valid destination for a movcc_fp
301;; instruction.  This means rejecting fcc_operands, since we need
302;; scratch registers to write to them.
303
304(define_predicate "movcc_fp_destination_operand"
305  (match_code "reg,subreg,mem")
306{
307  if (fcc_operand (op, mode))
308    return FALSE;
309
310  return move_destination_operand (op, mode);
311})
312
313;; Return true if operand is something that can be an input for a
314;; conditional move operation.
315
316(define_predicate "condexec_source_operand"
317  (match_code "reg,subreg,const_int,mem,const_double")
318{
319  rtx subreg;
320  enum rtx_code code;
321
322  switch (GET_CODE (op))
323    {
324    default:
325      break;
326
327    case CONST_INT:
328    case CONST_DOUBLE:
329      return ZERO_P (op);
330
331    case SUBREG:
332      if (GET_MODE (op) != mode && mode != VOIDmode)
333        return FALSE;
334
335      subreg = SUBREG_REG (op);
336      code = GET_CODE (subreg);
337      if (code == MEM)
338	return frv_legitimate_address_p (mode, XEXP (subreg, 0),
339					 reload_completed, TRUE, FALSE);
340
341      return (code == REG);
342
343    case REG:
344      if (GET_MODE (op) != mode && mode != VOIDmode)
345        return FALSE;
346
347      return TRUE;
348
349    case MEM:
350      return frv_legitimate_memory_operand (op, mode, TRUE);
351    }
352
353  return FALSE;
354})
355
356;; Return true if operand is something that can be an output for a
357;; conditional move operation.
358
359(define_predicate "condexec_dest_operand"
360  (match_code "reg,subreg,mem")
361{
362  rtx subreg;
363  enum rtx_code code;
364
365  switch (GET_CODE (op))
366    {
367    default:
368      break;
369
370    case SUBREG:
371      if (GET_MODE (op) != mode && mode != VOIDmode)
372        return FALSE;
373
374      subreg = SUBREG_REG (op);
375      code = GET_CODE (subreg);
376      if (code == MEM)
377	return frv_legitimate_address_p (mode, XEXP (subreg, 0),
378					 reload_completed, TRUE, FALSE);
379
380      return (code == REG);
381
382    case REG:
383      if (GET_MODE (op) != mode && mode != VOIDmode)
384        return FALSE;
385
386      return TRUE;
387
388    case MEM:
389      return frv_legitimate_memory_operand (op, mode, TRUE);
390    }
391
392  return FALSE;
393})
394
395;; Return true if operand is a register of any flavor or a 0 of the
396;; appropriate type.
397
398(define_predicate "reg_or_0_operand"
399  (match_code "reg,subreg,const_int,const_double")
400{
401  switch (GET_CODE (op))
402    {
403    default:
404      break;
405
406    case REG:
407    case SUBREG:
408      if (GET_MODE (op) != mode && mode != VOIDmode)
409	return FALSE;
410
411      return register_operand (op, mode);
412
413    case CONST_INT:
414    case CONST_DOUBLE:
415      return ZERO_P (op);
416    }
417
418  return FALSE;
419})
420
421;; Return true if operand is the link register.
422
423(define_predicate "lr_operand"
424  (match_code "reg")
425{
426  if (GET_CODE (op) != REG)
427    return FALSE;
428
429  if (GET_MODE (op) != mode && mode != VOIDmode)
430    return FALSE;
431
432  if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
433    return FALSE;
434
435  return TRUE;
436})
437
438;; Return true if operand is a gpr register or a valid memory operand.
439
440(define_predicate "gpr_or_memory_operand"
441  (match_code "reg,subreg,mem")
442{
443  return (integer_register_operand (op, mode)
444	  || frv_legitimate_memory_operand (op, mode, FALSE));
445})
446
447;; Return true if operand is a gpr register, a valid memory operand,
448;; or a memory operand that can be made valid using an additional gpr
449;; register.
450
451(define_predicate "gpr_or_memory_operand_with_scratch"
452  (match_code "reg,subreg,mem")
453{
454  rtx addr;
455
456  if (gpr_or_memory_operand (op, mode))
457    return TRUE;
458
459  if (GET_CODE (op) != MEM)
460    return FALSE;
461
462  if (GET_MODE (op) != mode)
463    return FALSE;
464
465  addr = XEXP (op, 0);
466
467  if (GET_CODE (addr) != PLUS)
468    return FALSE;
469
470  if (!integer_register_operand (XEXP (addr, 0), Pmode))
471    return FALSE;
472
473  if (GET_CODE (XEXP (addr, 1)) != CONST_INT)
474    return FALSE;
475
476  return TRUE;
477})
478
479;; Return true if operand is a fpr register or a valid memory
480;; operation.
481
482(define_predicate "fpr_or_memory_operand"
483  (match_code "reg,subreg,mem")
484{
485  return (fpr_operand (op, mode)
486	  || frv_legitimate_memory_operand (op, mode, FALSE));
487})
488
489;; Return 1 if operand is a 12 bit signed immediate.
490
491(define_predicate "int12_operand"
492  (match_code "const_int")
493{
494  if (GET_CODE (op) != CONST_INT)
495    return FALSE;
496
497  return IN_RANGE_P (INTVAL (op), -2048, 2047);
498})
499
500;; Return 1 if operand is an integer constant that takes 2
501;; instructions to load up and can be split into sethi/setlo
502;; instructions..
503
504(define_predicate "int_2word_operand"
505  (match_code "const_int,const_double,symbol_ref,label_ref,const")
506{
507  HOST_WIDE_INT value;
508  REAL_VALUE_TYPE rv;
509  long l;
510
511  switch (GET_CODE (op))
512    {
513    default:
514      break;
515
516    case LABEL_REF:
517      if (TARGET_FDPIC)
518	return FALSE;
519
520      return (flag_pic == 0);
521
522    case CONST:
523      if (flag_pic || TARGET_FDPIC)
524	return FALSE;
525
526      op = XEXP (op, 0);
527      if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
528	op = XEXP (op, 0);
529      return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
530
531    case SYMBOL_REF:
532      if (TARGET_FDPIC)
533	return FALSE;
534
535      /* small data references are already 1 word */
536      return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
537
538    case CONST_INT:
539      return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
540
541    case CONST_DOUBLE:
542      if (GET_MODE (op) == SFmode)
543	{
544	  REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
545	  REAL_VALUE_TO_TARGET_SINGLE (rv, l);
546	  value = l;
547	  return ! IN_RANGE_P (value, -32768, 32767);
548	}
549      else if (GET_MODE (op) == VOIDmode)
550	{
551	  value = CONST_DOUBLE_LOW (op);
552	  return ! IN_RANGE_P (value, -32768, 32767);
553	}
554      break;
555    }
556
557  return FALSE;
558})
559
560;; Return true if operand is the uClinux PIC register.
561
562(define_predicate "fdpic_operand"
563  (match_code "reg")
564{
565  if (!TARGET_FDPIC)
566    return FALSE;
567
568  if (GET_CODE (op) != REG)
569    return FALSE;
570
571  if (GET_MODE (op) != mode && mode != VOIDmode)
572    return FALSE;
573
574  if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
575    return FALSE;
576
577  return TRUE;
578})
579
580;; TODO: Add a comment here.
581
582(define_predicate "fdpic_fptr_operand"
583  (match_code "reg")
584{
585  if (GET_MODE (op) != mode && mode != VOIDmode)
586    return FALSE;
587  if (GET_CODE (op) != REG)
588    return FALSE;
589  if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
590    return FALSE;
591  return TRUE;
592})
593
594;; An address operand that may use a pair of registers, an addressing
595;; mode that we reject in general.
596
597(define_predicate "ldd_address_operand"
598  (match_code "reg,subreg,plus")
599{
600  if (GET_MODE (op) != mode && GET_MODE (op) != VOIDmode)
601    return FALSE;
602
603  return frv_legitimate_address_p (DImode, op, reload_completed, FALSE, TRUE);
604})
605
606;; TODO: Add a comment here.
607
608(define_predicate "got12_operand"
609  (match_code "const")
610{
611  struct frv_unspec unspec;
612
613  if (frv_const_unspec_p (op, &unspec))
614    switch (unspec.reloc)
615      {
616      case R_FRV_GOT12:
617      case R_FRV_GOTOFF12:
618      case R_FRV_FUNCDESC_GOT12:
619      case R_FRV_FUNCDESC_GOTOFF12:
620      case R_FRV_GPREL12:
621      case R_FRV_TLSMOFF12:
622	return true;
623      }
624  return false;
625})
626
627;; Return true if OP is a valid const-unspec expression.
628
629(define_predicate "const_unspec_operand"
630  (match_code "const")
631{
632  struct frv_unspec unspec;
633
634  return frv_const_unspec_p (op, &unspec);
635})
636
637;; Return true if operand is an icc register.
638
639(define_predicate "icc_operand"
640  (match_code "reg")
641{
642  int regno;
643
644  if (GET_MODE (op) != mode && mode != VOIDmode)
645    return FALSE;
646
647  if (GET_CODE (op) != REG)
648    return FALSE;
649
650  regno = REGNO (op);
651  return ICC_OR_PSEUDO_P (regno);
652})
653
654;; Return true if operand is an fcc register.
655
656(define_predicate "fcc_operand"
657  (match_code "reg")
658{
659  int regno;
660
661  if (GET_MODE (op) != mode && mode != VOIDmode)
662    return FALSE;
663
664  if (GET_CODE (op) != REG)
665    return FALSE;
666
667  regno = REGNO (op);
668  return FCC_OR_PSEUDO_P (regno);
669})
670
671;; Return true if operand is either an fcc or icc register.
672
673(define_predicate "cc_operand"
674  (match_code "reg")
675{
676  int regno;
677
678  if (GET_MODE (op) != mode && mode != VOIDmode)
679    return FALSE;
680
681  if (GET_CODE (op) != REG)
682    return FALSE;
683
684  regno = REGNO (op);
685  if (CC_OR_PSEUDO_P (regno))
686    return TRUE;
687
688  return FALSE;
689})
690
691;; Return true if operand is an integer CCR register.
692
693(define_predicate "icr_operand"
694  (match_code "reg")
695{
696  int regno;
697
698  if (GET_MODE (op) != mode && mode != VOIDmode)
699    return FALSE;
700
701  if (GET_CODE (op) != REG)
702    return FALSE;
703
704  regno = REGNO (op);
705  return ICR_OR_PSEUDO_P (regno);
706})
707
708;; Return true if operand is an fcc register.
709
710(define_predicate "fcr_operand"
711  (match_code "reg")
712{
713  int regno;
714
715  if (GET_MODE (op) != mode && mode != VOIDmode)
716    return FALSE;
717
718  if (GET_CODE (op) != REG)
719    return FALSE;
720
721  regno = REGNO (op);
722  return FCR_OR_PSEUDO_P (regno);
723})
724
725;; Return true if operand is either an fcc or icc register.
726
727(define_predicate "cr_operand"
728  (match_code "reg")
729{
730  int regno;
731
732  if (GET_MODE (op) != mode && mode != VOIDmode)
733    return FALSE;
734
735  if (GET_CODE (op) != REG)
736    return FALSE;
737
738  regno = REGNO (op);
739  if (CR_OR_PSEUDO_P (regno))
740    return TRUE;
741
742  return FALSE;
743})
744
745;; Return true if operand is a FPR register.
746
747(define_predicate "fpr_operand"
748  (match_code "reg,subreg")
749{
750  if (GET_MODE (op) != mode && mode != VOIDmode)
751    return FALSE;
752
753  if (GET_CODE (op) == SUBREG)
754    {
755      if (GET_CODE (SUBREG_REG (op)) != REG)
756        return register_operand (op, mode);
757
758      op = SUBREG_REG (op);
759    }
760
761  if (GET_CODE (op) != REG)
762    return FALSE;
763
764  return FPR_OR_PSEUDO_P (REGNO (op));
765})
766
767;; Return true if operand is an even GPR or FPR register.
768
769(define_predicate "even_reg_operand"
770  (match_code "reg,subreg")
771{
772  int regno;
773
774  if (GET_MODE (op) != mode && mode != VOIDmode)
775    return FALSE;
776
777  if (GET_CODE (op) == SUBREG)
778    {
779      if (GET_CODE (SUBREG_REG (op)) != REG)
780        return register_operand (op, mode);
781
782      op = SUBREG_REG (op);
783    }
784
785  if (GET_CODE (op) != REG)
786    return FALSE;
787
788  regno = REGNO (op);
789  if (regno >= FIRST_PSEUDO_REGISTER)
790    return TRUE;
791
792  if (GPR_P (regno))
793    return (((regno - GPR_FIRST) & 1) == 0);
794
795  if (FPR_P (regno))
796    return (((regno - FPR_FIRST) & 1) == 0);
797
798  return FALSE;
799})
800
801;; Return true if operand is an odd GPR register.
802
803(define_predicate "odd_reg_operand"
804  (match_code "reg,subreg")
805{
806  int regno;
807
808  if (GET_MODE (op) != mode && mode != VOIDmode)
809    return FALSE;
810
811  if (GET_CODE (op) == SUBREG)
812    {
813      if (GET_CODE (SUBREG_REG (op)) != REG)
814        return register_operand (op, mode);
815
816      op = SUBREG_REG (op);
817    }
818
819  if (GET_CODE (op) != REG)
820    return FALSE;
821
822  regno = REGNO (op);
823  /* Assume that reload will give us an even register.  */
824  if (regno >= FIRST_PSEUDO_REGISTER)
825    return FALSE;
826
827  if (GPR_P (regno))
828    return (((regno - GPR_FIRST) & 1) != 0);
829
830  if (FPR_P (regno))
831    return (((regno - FPR_FIRST) & 1) != 0);
832
833  return FALSE;
834})
835
836;; Return true if operand is an even GPR register.
837
838(define_predicate "even_gpr_operand"
839  (match_code "reg,subreg")
840{
841  int regno;
842
843  if (GET_MODE (op) != mode && mode != VOIDmode)
844    return FALSE;
845
846  if (GET_CODE (op) == SUBREG)
847    {
848      if (GET_CODE (SUBREG_REG (op)) != REG)
849        return register_operand (op, mode);
850
851      op = SUBREG_REG (op);
852    }
853
854  if (GET_CODE (op) != REG)
855    return FALSE;
856
857  regno = REGNO (op);
858  if (regno >= FIRST_PSEUDO_REGISTER)
859    return TRUE;
860
861  if (! GPR_P (regno))
862    return FALSE;
863
864  return (((regno - GPR_FIRST) & 1) == 0);
865})
866
867;; Return true if operand is an odd GPR register.
868
869(define_predicate "odd_gpr_operand"
870  (match_code "reg,subreg")
871{
872  int regno;
873
874  if (GET_MODE (op) != mode && mode != VOIDmode)
875    return FALSE;
876
877  if (GET_CODE (op) == SUBREG)
878    {
879      if (GET_CODE (SUBREG_REG (op)) != REG)
880        return register_operand (op, mode);
881
882      op = SUBREG_REG (op);
883    }
884
885  if (GET_CODE (op) != REG)
886    return FALSE;
887
888  regno = REGNO (op);
889  /* Assume that reload will give us an even register.  */
890  if (regno >= FIRST_PSEUDO_REGISTER)
891    return FALSE;
892
893  if (! GPR_P (regno))
894    return FALSE;
895
896  return (((regno - GPR_FIRST) & 1) != 0);
897})
898
899;; Return true if operand is a quad aligned FPR register.
900
901(define_predicate "quad_fpr_operand"
902  (match_code "reg,subreg")
903{
904  int regno;
905
906  if (GET_MODE (op) != mode && mode != VOIDmode)
907    return FALSE;
908
909  if (GET_CODE (op) == SUBREG)
910    {
911      if (GET_CODE (SUBREG_REG (op)) != REG)
912        return register_operand (op, mode);
913
914      op = SUBREG_REG (op);
915    }
916
917  if (GET_CODE (op) != REG)
918    return FALSE;
919
920  regno = REGNO (op);
921  if (regno >= FIRST_PSEUDO_REGISTER)
922    return TRUE;
923
924  if (! FPR_P (regno))
925    return FALSE;
926
927  return (((regno - FPR_FIRST) & 3) == 0);
928})
929
930;; Return true if operand is an even FPR register.
931
932(define_predicate "even_fpr_operand"
933  (match_code "reg,subreg")
934{
935  int regno;
936
937  if (GET_MODE (op) != mode && mode != VOIDmode)
938    return FALSE;
939
940  if (GET_CODE (op) == SUBREG)
941    {
942      if (GET_CODE (SUBREG_REG (op)) != REG)
943        return register_operand (op, mode);
944
945      op = SUBREG_REG (op);
946    }
947
948  if (GET_CODE (op) != REG)
949    return FALSE;
950
951  regno = REGNO (op);
952  if (regno >= FIRST_PSEUDO_REGISTER)
953    return TRUE;
954
955  if (! FPR_P (regno))
956    return FALSE;
957
958  return (((regno - FPR_FIRST) & 1) == 0);
959})
960
961;; Return true if operand is an odd FPR register.
962
963(define_predicate "odd_fpr_operand"
964  (match_code "reg,subreg")
965{
966  int regno;
967
968  if (GET_MODE (op) != mode && mode != VOIDmode)
969    return FALSE;
970
971  if (GET_CODE (op) == SUBREG)
972    {
973      if (GET_CODE (SUBREG_REG (op)) != REG)
974        return register_operand (op, mode);
975
976      op = SUBREG_REG (op);
977    }
978
979  if (GET_CODE (op) != REG)
980    return FALSE;
981
982  regno = REGNO (op);
983  /* Assume that reload will give us an even register.  */
984  if (regno >= FIRST_PSEUDO_REGISTER)
985    return FALSE;
986
987  if (! FPR_P (regno))
988    return FALSE;
989
990  return (((regno - FPR_FIRST) & 1) != 0);
991})
992
993;; Return true if operand is a 2 word memory address that can be
994;; loaded in one instruction to load or store.  We assume the stack
995;; and frame pointers are suitably aligned, and variables in the small
996;; data area.  FIXME -- at some we should recognize other globals and
997;; statics. We can't assume that any old pointer is aligned, given
998;; that arguments could be passed on an odd word on the stack and the
999;; address taken and passed through to another function.
1000
1001(define_predicate "dbl_memory_one_insn_operand"
1002  (match_code "mem")
1003{
1004  rtx addr;
1005  rtx addr_reg;
1006
1007  if (! TARGET_DWORD)
1008    return FALSE;
1009
1010  if (GET_CODE (op) != MEM)
1011    return FALSE;
1012
1013  if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
1014    return FALSE;
1015
1016  addr = XEXP (op, 0);
1017  if (GET_CODE (addr) == REG)
1018    addr_reg = addr;
1019
1020  else if (GET_CODE (addr) == PLUS)
1021    {
1022      rtx addr0 = XEXP (addr, 0);
1023      rtx addr1 = XEXP (addr, 1);
1024
1025      if (GET_CODE (addr0) != REG)
1026	return FALSE;
1027
1028      if (got12_operand (addr1, VOIDmode))
1029	return TRUE;
1030
1031      if (GET_CODE (addr1) != CONST_INT)
1032	return FALSE;
1033
1034      if ((INTVAL (addr1) & 7) != 0)
1035	return FALSE;
1036
1037      addr_reg = addr0;
1038    }
1039
1040  else
1041    return FALSE;
1042
1043  if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
1044    return TRUE;
1045
1046  return FALSE;
1047})
1048
1049;; Return true if operand is a 2 word memory address that needs to use
1050;; two instructions to load or store.
1051
1052(define_predicate "dbl_memory_two_insn_operand"
1053  (match_code "mem")
1054{
1055  if (GET_CODE (op) != MEM)
1056    return FALSE;
1057
1058  if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
1059    return FALSE;
1060
1061  if (! TARGET_DWORD)
1062    return TRUE;
1063
1064  return ! dbl_memory_one_insn_operand (op, mode);
1065})
1066
1067;; Return true if operand is a memory reference suitable for a call.
1068
1069(define_predicate "call_operand"
1070  (match_code "reg,subreg,const_int,const,symbol_ref")
1071{
1072  if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
1073    return FALSE;
1074
1075  if (GET_CODE (op) == SYMBOL_REF)
1076    return !TARGET_LONG_CALLS || SYMBOL_REF_LOCAL_P (op);
1077
1078  /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
1079     never occur anyway), but prevents reload from not handling the case
1080     properly of a call through a pointer on a function that calls
1081     vfork/setjmp, etc. due to the need to flush all of the registers to stack.  */
1082  return gpr_or_int12_operand (op, mode);
1083})
1084
1085;; Return true if operand is a memory reference suitable for a
1086;; sibcall.
1087
1088(define_predicate "sibcall_operand"
1089  (match_code "reg,subreg,const_int,const")
1090{
1091  if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
1092    return FALSE;
1093
1094  /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
1095     never occur anyway), but prevents reload from not handling the case
1096     properly of a call through a pointer on a function that calls
1097     vfork/setjmp, etc. due to the need to flush all of the registers to stack.  */
1098  return gpr_or_int12_operand (op, mode);
1099})
1100
1101;; Return 1 if operand is an integer constant with the bottom 16 bits
1102;; clear.
1103
1104(define_predicate "upper_int16_operand"
1105  (match_code "const_int")
1106{
1107  if (GET_CODE (op) != CONST_INT)
1108    return FALSE;
1109
1110  return ((INTVAL (op) & 0xffff) == 0);
1111})
1112
1113;; Return 1 if operand is a 16 bit unsigned immediate.
1114
1115(define_predicate "uint16_operand"
1116  (match_code "const_int")
1117{
1118  if (GET_CODE (op) != CONST_INT)
1119    return FALSE;
1120
1121  return IN_RANGE_P (INTVAL (op), 0, 0xffff);
1122})
1123
1124;; Returns 1 if OP is either a SYMBOL_REF or a constant.
1125
1126(define_predicate "symbolic_operand"
1127  (match_code "symbol_ref,const_int")
1128{
1129  enum rtx_code c = GET_CODE (op);
1130
1131  if (c == CONST)
1132    {
1133      /* Allow (const:SI (plus:SI (symbol_ref) (const_int))).  */
1134      return GET_MODE (op) == SImode
1135	&& GET_CODE (XEXP (op, 0)) == PLUS
1136	&& GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
1137	&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT;
1138    }
1139
1140  return c == SYMBOL_REF || c == CONST_INT;
1141})
1142
1143;; Return true if operator is a kind of relational operator.
1144
1145(define_predicate "relational_operator"
1146  (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu")
1147{
1148  return (integer_relational_operator (op, mode)
1149	  || float_relational_operator (op, mode));
1150})
1151
1152;; Return true if OP is a relational operator suitable for CCmode,
1153;; CC_UNSmode or CC_NZmode.
1154
1155(define_predicate "integer_relational_operator"
1156  (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu")
1157{
1158  if (mode != VOIDmode && mode != GET_MODE (op))
1159    return FALSE;
1160
1161  /* The allowable relations depend on the mode of the ICC register.  */
1162  switch (GET_CODE (op))
1163    {
1164    default:
1165      return FALSE;
1166
1167    case EQ:
1168    case NE:
1169    case LT:
1170    case GE:
1171      return (GET_MODE (XEXP (op, 0)) == CC_NZmode
1172	      || GET_MODE (XEXP (op, 0)) == CCmode);
1173
1174    case LE:
1175    case GT:
1176      return GET_MODE (XEXP (op, 0)) == CCmode;
1177
1178    case GTU:
1179    case GEU:
1180    case LTU:
1181    case LEU:
1182      return (GET_MODE (XEXP (op, 0)) == CC_NZmode
1183	      || GET_MODE (XEXP (op, 0)) == CC_UNSmode);
1184    }
1185})
1186
1187;; Return true if operator is a floating point relational operator.
1188
1189(define_predicate "float_relational_operator"
1190  (match_code "eq,ne,le,lt,ge,gt")
1191{
1192  if (mode != VOIDmode && mode != GET_MODE (op))
1193    return FALSE;
1194
1195  switch (GET_CODE (op))
1196    {
1197    default:
1198      return FALSE;
1199
1200    case EQ: case NE:
1201    case LE: case LT:
1202    case GE: case GT:
1203#if 0
1204    case UEQ: case UNE:
1205    case ULE: case ULT:
1206    case UGE: case UGT:
1207    case ORDERED:
1208    case UNORDERED:
1209#endif
1210      return GET_MODE (XEXP (op, 0)) == CC_FPmode;
1211    }
1212})
1213
1214;; Return true if operator is EQ/NE of a conditional execution
1215;; register.
1216
1217(define_predicate "ccr_eqne_operator"
1218  (match_code "eq,ne")
1219{
1220  enum machine_mode op_mode = GET_MODE (op);
1221  rtx op0;
1222  rtx op1;
1223  int regno;
1224
1225  if (mode != VOIDmode && op_mode != mode)
1226    return FALSE;
1227
1228  switch (GET_CODE (op))
1229    {
1230    default:
1231      return FALSE;
1232
1233    case EQ:
1234    case NE:
1235      break;
1236    }
1237
1238  op1 = XEXP (op, 1);
1239  if (op1 != const0_rtx)
1240    return FALSE;
1241
1242  op0 = XEXP (op, 0);
1243  if (GET_CODE (op0) != REG)
1244    return FALSE;
1245
1246  regno = REGNO (op0);
1247  if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
1248    return TRUE;
1249
1250  return FALSE;
1251})
1252
1253;; Return true if operator is a minimum or maximum operator (both
1254;; signed and unsigned).
1255
1256(define_predicate "minmax_operator"
1257  (match_code "smin,smax,umin,umax")
1258{
1259  if (mode != VOIDmode && mode != GET_MODE (op))
1260    return FALSE;
1261
1262  switch (GET_CODE (op))
1263    {
1264    default:
1265      return FALSE;
1266
1267    case SMIN:
1268    case SMAX:
1269    case UMIN:
1270    case UMAX:
1271      break;
1272    }
1273
1274  if (! integer_register_operand (XEXP (op, 0), mode))
1275    return FALSE;
1276
1277  if (! gpr_or_int10_operand (XEXP (op, 1), mode))
1278    return FALSE;
1279
1280  return TRUE;
1281})
1282
1283;; Return true if operator is an integer binary operator that can
1284;; executed conditionally and takes 1 cycle.
1285
1286(define_predicate "condexec_si_binary_operator"
1287  (match_code "plus,minus,and,ior,xor,ashift,ashiftrt,lshiftrt")
1288{
1289  enum machine_mode op_mode = GET_MODE (op);
1290
1291  if (mode != VOIDmode && op_mode != mode)
1292    return FALSE;
1293
1294  switch (GET_CODE (op))
1295    {
1296    default:
1297      return FALSE;
1298
1299    case PLUS:
1300    case MINUS:
1301    case AND:
1302    case IOR:
1303    case XOR:
1304    case ASHIFT:
1305    case ASHIFTRT:
1306    case LSHIFTRT:
1307      return TRUE;
1308    }
1309})
1310
1311;; Return true if operator is an integer binary operator that can be
1312;; executed conditionally by a media instruction.
1313
1314(define_predicate "condexec_si_media_operator"
1315  (match_code "and,ior,xor")
1316{
1317  enum machine_mode op_mode = GET_MODE (op);
1318
1319  if (mode != VOIDmode && op_mode != mode)
1320    return FALSE;
1321
1322  switch (GET_CODE (op))
1323    {
1324    default:
1325      return FALSE;
1326
1327    case AND:
1328    case IOR:
1329    case XOR:
1330      return TRUE;
1331    }
1332})
1333
1334;; Return true if operator is an integer division operator that can
1335;; executed conditionally.
1336
1337(define_predicate "condexec_si_divide_operator"
1338  (match_code "div,udiv")
1339{
1340  enum machine_mode op_mode = GET_MODE (op);
1341
1342  if (mode != VOIDmode && op_mode != mode)
1343    return FALSE;
1344
1345  switch (GET_CODE (op))
1346    {
1347    default:
1348      return FALSE;
1349
1350    case DIV:
1351    case UDIV:
1352      return TRUE;
1353    }
1354})
1355
1356;; Return true if operator is an integer unary operator that can
1357;; executed conditionally.
1358
1359(define_predicate "condexec_si_unary_operator"
1360  (match_code "not,neg")
1361{
1362  enum machine_mode op_mode = GET_MODE (op);
1363
1364  if (mode != VOIDmode && op_mode != mode)
1365    return FALSE;
1366
1367  switch (GET_CODE (op))
1368    {
1369    default:
1370      return FALSE;
1371
1372    case NEG:
1373    case NOT:
1374      return TRUE;
1375    }
1376})
1377
1378;; Return true if operator is an addition or subtraction
1379;; expression. Such expressions can be evaluated conditionally by
1380;; floating-point instructions.
1381
1382(define_predicate "condexec_sf_add_operator"
1383  (match_code "plus,minus")
1384{
1385  enum machine_mode op_mode = GET_MODE (op);
1386
1387  if (mode != VOIDmode && op_mode != mode)
1388    return FALSE;
1389
1390  switch (GET_CODE (op))
1391    {
1392    default:
1393      return FALSE;
1394
1395    case PLUS:
1396    case MINUS:
1397      return TRUE;
1398    }
1399})
1400
1401;; Return true if operator is a conversion-type expression that can be
1402;; evaluated conditionally by floating-point instructions.
1403
1404(define_predicate "condexec_sf_conv_operator"
1405  (match_code "abs,neg")
1406{
1407  enum machine_mode op_mode = GET_MODE (op);
1408
1409  if (mode != VOIDmode && op_mode != mode)
1410    return FALSE;
1411
1412  switch (GET_CODE (op))
1413    {
1414    default:
1415      return FALSE;
1416
1417    case NEG:
1418    case ABS:
1419      return TRUE;
1420    }
1421})
1422
1423;; Return true if OP is an integer binary operator that can be
1424;; combined with a (set ... (compare:CC_NZ ...)) pattern.
1425
1426(define_predicate "intop_compare_operator"
1427  (match_code "plus,minus,and,ior,xor,ashift,ashiftrt,lshiftrt")
1428{
1429  if (mode != VOIDmode && GET_MODE (op) != mode)
1430    return FALSE;
1431
1432  switch (GET_CODE (op))
1433    {
1434    default:
1435      return FALSE;
1436
1437    case PLUS:
1438    case MINUS:
1439    case AND:
1440    case IOR:
1441    case XOR:
1442    case ASHIFTRT:
1443    case LSHIFTRT:
1444      return GET_MODE (op) == SImode;
1445    }
1446})
1447
1448;; Return 1 if operand is a register or 6 bit signed immediate.
1449
1450(define_predicate "fpr_or_int6_operand"
1451  (match_code "reg,subreg,const_int")
1452{
1453  if (GET_CODE (op) == CONST_INT)
1454    return IN_RANGE_P (INTVAL (op), -32, 31);
1455
1456  if (GET_MODE (op) != mode && mode != VOIDmode)
1457    return FALSE;
1458
1459  if (GET_CODE (op) == SUBREG)
1460    {
1461      if (GET_CODE (SUBREG_REG (op)) != REG)
1462	return register_operand (op, mode);
1463
1464      op = SUBREG_REG (op);
1465    }
1466
1467  if (GET_CODE (op) != REG)
1468    return FALSE;
1469
1470  return FPR_OR_PSEUDO_P (REGNO (op));
1471})
1472
1473;; Return 1 if operand is a 6 bit signed immediate.
1474
1475(define_predicate "int6_operand"
1476  (match_code "const_int")
1477{
1478  if (GET_CODE (op) != CONST_INT)
1479    return FALSE;
1480
1481  return IN_RANGE_P (INTVAL (op), -32, 31);
1482})
1483
1484;; Return 1 if operand is a 5 bit signed immediate.
1485
1486(define_predicate "int5_operand"
1487  (match_code "const_int")
1488{
1489  return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
1490})
1491
1492;; Return 1 if operand is a 5 bit unsigned immediate.
1493
1494(define_predicate "uint5_operand"
1495  (match_code "const_int")
1496{
1497  return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
1498})
1499
1500;; Return 1 if operand is a 4 bit unsigned immediate.
1501
1502(define_predicate "uint4_operand"
1503  (match_code "const_int")
1504{
1505  return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
1506})
1507
1508;; Return 1 if operand is a 1 bit unsigned immediate (0 or 1).
1509
1510(define_predicate "uint1_operand"
1511  (match_code "const_int")
1512{
1513  return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
1514})
1515
1516;; Return 1 if operand is a valid ACC register number.
1517
1518(define_predicate "acc_operand"
1519  (match_code "reg,subreg")
1520{
1521  return ((mode == VOIDmode || mode == GET_MODE (op))
1522	  && REG_P (op) && ACC_P (REGNO (op))
1523	  && ((REGNO (op) - ACC_FIRST) & ~ACC_MASK) == 0);
1524})
1525
1526;; Return 1 if operand is a valid even ACC register number.
1527
1528(define_predicate "even_acc_operand"
1529  (match_code "reg,subreg")
1530{
1531  return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 1) == 0;
1532})
1533
1534;; Return 1 if operand is zero or four.
1535
1536(define_predicate "quad_acc_operand"
1537  (match_code "reg,subreg")
1538{
1539  return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 3) == 0;
1540})
1541
1542;; Return 1 if operand is a valid ACCG register number.
1543
1544(define_predicate "accg_operand"
1545  (match_code "reg,subreg")
1546{
1547  return ((mode == VOIDmode || mode == GET_MODE (op))
1548	  && REG_P (op) && ACCG_P (REGNO (op))
1549	  && ((REGNO (op) - ACCG_FIRST) & ~ACC_MASK) == 0);
1550})
1551