1 /* mips.h. Mips opcode list for GDB, the GNU debugger. 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 3 Free Software Foundation, Inc. 4 Contributed by Ralph Campbell and OSF 5 Commented and modified by Ian Lance Taylor, Cygnus Support 6 7 This file is part of GDB, GAS, and the GNU binutils. 8 9 GDB, GAS, and the GNU binutils are free software; you can redistribute 10 them and/or modify them under the terms of the GNU General Public 11 License as published by the Free Software Foundation; either version 12 1, or (at your option) any later version. 13 14 GDB, GAS, and the GNU binutils are distributed in the hope that they 15 will be useful, but WITHOUT ANY WARRANTY; without even the implied 16 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 17 the GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this file; see the file COPYING. If not, write to the Free 21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 22 23 #ifndef _MIPS_H_ 24 #define _MIPS_H_ 25 26 /* These are bit masks and shift counts to use to access the various 27 fields of an instruction. To retrieve the X field of an 28 instruction, use the expression 29 (i >> OP_SH_X) & OP_MASK_X 30 To set the same field (to j), use 31 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 32 33 Make sure you use fields that are appropriate for the instruction, 34 of course. 35 36 The 'i' format uses OP, RS, RT and IMMEDIATE. 37 38 The 'j' format uses OP and TARGET. 39 40 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 41 42 The 'b' format uses OP, RS, RT and DELTA. 43 44 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 45 46 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 47 48 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 49 breakpoint instruction are not defined; Kane says the breakpoint 50 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 51 only use ten bits). An optional two-operand form of break/sdbbp 52 allows the lower ten bits to be set too, and MIPS32 and later 53 architectures allow 20 bits to be set with a signal operand 54 (using CODE20). 55 56 The syscall instruction uses CODE20. 57 58 The general coprocessor instructions use COPZ. */ 59 60 #define OP_MASK_OP 0x3f 61 #define OP_SH_OP 26 62 #define OP_MASK_RS 0x1f 63 #define OP_SH_RS 21 64 #define OP_MASK_FR 0x1f 65 #define OP_SH_FR 21 66 #define OP_MASK_FMT 0x1f 67 #define OP_SH_FMT 21 68 #define OP_MASK_BCC 0x7 69 #define OP_SH_BCC 18 70 #define OP_MASK_CODE 0x3ff 71 #define OP_SH_CODE 16 72 #define OP_MASK_CODE2 0x3ff 73 #define OP_SH_CODE2 6 74 #define OP_MASK_RT 0x1f 75 #define OP_SH_RT 16 76 #define OP_MASK_FT 0x1f 77 #define OP_SH_FT 16 78 #define OP_MASK_CACHE 0x1f 79 #define OP_SH_CACHE 16 80 #define OP_MASK_RD 0x1f 81 #define OP_SH_RD 11 82 #define OP_MASK_FS 0x1f 83 #define OP_SH_FS 11 84 #define OP_MASK_PREFX 0x1f 85 #define OP_SH_PREFX 11 86 #define OP_MASK_CCC 0x7 87 #define OP_SH_CCC 8 88 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 89 #define OP_SH_CODE20 6 90 #define OP_MASK_SHAMT 0x1f 91 #define OP_SH_SHAMT 6 92 #define OP_MASK_FD 0x1f 93 #define OP_SH_FD 6 94 #define OP_MASK_TARGET 0x3ffffff 95 #define OP_SH_TARGET 0 96 #define OP_MASK_COPZ 0x1ffffff 97 #define OP_SH_COPZ 0 98 #define OP_MASK_IMMEDIATE 0xffff 99 #define OP_SH_IMMEDIATE 0 100 #define OP_MASK_DELTA 0xffff 101 #define OP_SH_DELTA 0 102 #define OP_MASK_FUNCT 0x3f 103 #define OP_SH_FUNCT 0 104 #define OP_MASK_SPEC 0x3f 105 #define OP_SH_SPEC 0 106 #define OP_SH_LOCC 8 /* FP condition code. */ 107 #define OP_SH_HICC 18 /* FP condition code. */ 108 #define OP_MASK_CC 0x7 109 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 110 #define OP_MASK_COP1NORM 0x1 /* a single bit. */ 111 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 112 #define OP_MASK_COP1SPEC 0xf 113 #define OP_MASK_COP1SCLR 0x4 114 #define OP_MASK_COP1CMP 0x3 115 #define OP_SH_COP1CMP 4 116 #define OP_SH_FORMAT 21 /* FP short format field. */ 117 #define OP_MASK_FORMAT 0x7 118 #define OP_SH_TRUE 16 119 #define OP_MASK_TRUE 0x1 120 #define OP_SH_GE 17 121 #define OP_MASK_GE 0x01 122 #define OP_SH_UNSIGNED 16 123 #define OP_MASK_UNSIGNED 0x1 124 #define OP_SH_HINT 16 125 #define OP_MASK_HINT 0x1f 126 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 127 #define OP_MASK_MMI 0x3f 128 #define OP_SH_MMISUB 6 129 #define OP_MASK_MMISUB 0x1f 130 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 131 #define OP_SH_PERFREG 1 132 #define OP_SH_SEL 0 /* Coprocessor select field. */ 133 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 134 #define OP_SH_CODE19 6 /* 19 bit wait code. */ 135 #define OP_MASK_CODE19 0x7ffff 136 #define OP_SH_ALN 21 137 #define OP_MASK_ALN 0x7 138 #define OP_SH_VSEL 21 139 #define OP_MASK_VSEL 0x1f 140 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 141 but 0x8-0xf don't select bytes. */ 142 #define OP_SH_VECBYTE 22 143 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 144 #define OP_SH_VECALIGN 21 145 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 146 #define OP_SH_INSMSB 11 147 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 148 #define OP_SH_EXTMSBD 11 149 150 #define OP_OP_COP0 0x10 151 #define OP_OP_COP1 0x11 152 #define OP_OP_COP2 0x12 153 #define OP_OP_COP3 0x13 154 #define OP_OP_LWC1 0x31 155 #define OP_OP_LWC2 0x32 156 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 157 #define OP_OP_LDC1 0x35 158 #define OP_OP_LDC2 0x36 159 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 160 #define OP_OP_SWC1 0x39 161 #define OP_OP_SWC2 0x3a 162 #define OP_OP_SWC3 0x3b 163 #define OP_OP_SDC1 0x3d 164 #define OP_OP_SDC2 0x3e 165 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 166 167 /* Values in the 'VSEL' field. */ 168 #define MDMX_FMTSEL_IMM_QH 0x1d 169 #define MDMX_FMTSEL_IMM_OB 0x1e 170 #define MDMX_FMTSEL_VEC_QH 0x15 171 #define MDMX_FMTSEL_VEC_OB 0x16 172 173 /* This structure holds information for a particular instruction. */ 174 175 struct mips_opcode 176 { 177 /* The name of the instruction. */ 178 const char *name; 179 /* A string describing the arguments for this instruction. */ 180 const char *args; 181 /* The basic opcode for the instruction. When assembling, this 182 opcode is modified by the arguments to produce the actual opcode 183 that is used. If pinfo is INSN_MACRO, then this is 0. */ 184 unsigned long match; 185 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 186 relevant portions of the opcode when disassembling. If the 187 actual opcode anded with the match field equals the opcode field, 188 then we have found the correct instruction. If pinfo is 189 INSN_MACRO, then this field is the macro identifier. */ 190 unsigned long mask; 191 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 192 of bits describing the instruction, notably any relevant hazard 193 information. */ 194 unsigned long pinfo; 195 /* A collection of bits describing the instruction sets of which this 196 instruction or macro is a member. */ 197 unsigned long membership; 198 }; 199 200 /* These are the characters which may appear in the args field of an 201 instruction. They appear in the order in which the fields appear 202 when the instruction is used. Commas and parentheses in the args 203 string are ignored when assembling, and written into the output 204 when disassembling. 205 206 Each of these characters corresponds to a mask field defined above. 207 208 "<" 5 bit shift amount (OP_*_SHAMT) 209 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 210 "a" 26 bit target address (OP_*_TARGET) 211 "b" 5 bit base register (OP_*_RS) 212 "c" 10 bit breakpoint code (OP_*_CODE) 213 "d" 5 bit destination register specifier (OP_*_RD) 214 "h" 5 bit prefx hint (OP_*_PREFX) 215 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 216 "j" 16 bit signed immediate (OP_*_DELTA) 217 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 218 Also used for immediate operands in vr5400 vector insns. 219 "o" 16 bit signed offset (OP_*_DELTA) 220 "p" 16 bit PC relative branch target address (OP_*_DELTA) 221 "q" 10 bit extra breakpoint code (OP_*_CODE2) 222 "r" 5 bit same register used as both source and target (OP_*_RS) 223 "s" 5 bit source register specifier (OP_*_RS) 224 "t" 5 bit target register (OP_*_RT) 225 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 226 "v" 5 bit same register used as both source and destination (OP_*_RS) 227 "w" 5 bit same register used as both target and destination (OP_*_RT) 228 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 229 (used by clo and clz) 230 "C" 25 bit coprocessor function code (OP_*_COPZ) 231 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 232 "J" 19 bit wait function code (OP_*_CODE19) 233 "x" accept and ignore register name 234 "z" must be zero register 235 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 236 "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). 237 Enforces: 0 <= pos < 32. 238 "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). 239 Requires that "+A" or "+E" occur first to set position. 240 Enforces: 0 < (pos+size) <= 32. 241 "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). 242 Requires that "+A" or "+E" occur first to set position. 243 Enforces: 0 < (pos+size) <= 32. 244 (Also used by "dext" w/ different limits, but limits for 245 that are checked by the M_DEXT macro.) 246 "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). 247 Enforces: 32 <= pos < 64. 248 "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). 249 Requires that "+A" or "+E" occur first to set position. 250 Enforces: 32 < (pos+size) <= 64. 251 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 252 Requires that "+A" or "+E" occur first to set position. 253 Enforces: 32 < (pos+size) <= 64. 254 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 255 Requires that "+A" or "+E" occur first to set position. 256 Enforces: 32 < (pos+size) <= 64. 257 258 Floating point instructions: 259 "D" 5 bit destination register (OP_*_FD) 260 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 261 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 262 "S" 5 bit fs source 1 register (OP_*_FS) 263 "T" 5 bit ft source 2 register (OP_*_FT) 264 "R" 5 bit fr source 3 register (OP_*_FR) 265 "V" 5 bit same register used as floating source and destination (OP_*_FS) 266 "W" 5 bit same register used as floating target and destination (OP_*_FT) 267 268 Coprocessor instructions: 269 "E" 5 bit target register (OP_*_RT) 270 "G" 5 bit destination register (OP_*_RD) 271 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 272 "P" 5 bit performance-monitor register (OP_*_PERFREG) 273 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 274 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 275 see also "k" above 276 "+D" Combined destination register ("G") and sel ("H") for CP0 ops, 277 for pretty-printing in disassembly only. 278 279 Macro instructions: 280 "A" General 32 bit expression 281 "I" 32 bit immediate (value placed in imm_expr). 282 "+I" 32 bit immediate (value placed in imm2_expr). 283 "F" 64 bit floating point constant in .rdata 284 "L" 64 bit floating point constant in .lit8 285 "f" 32 bit floating point constant 286 "l" 32 bit floating point constant in .lit4 287 288 MDMX instruction operands (note that while these use the FP register 289 fields, they accept both $fN and $vN names for the registers): 290 "O" MDMX alignment offset (OP_*_ALN) 291 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 292 "X" MDMX destination register (OP_*_FD) 293 "Y" MDMX source register (OP_*_FS) 294 "Z" MDMX source register (OP_*_FT) 295 296 Other: 297 "()" parens surrounding optional value 298 "," separates operands 299 "[]" brackets around index for vector-op scalar operand specifier (vr5400) 300 "+" Start of extension sequence. 301 302 Characters used so far, for quick reference when adding more: 303 "%[]<>(),+" 304 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 305 "abcdefhijklopqrstuvwxz" 306 307 Extension character sequences used so far ("+" followed by the 308 following), for quick reference when adding more: 309 "ABCDEFGHI" 310 */ 311 312 /* These are the bits which may be set in the pinfo field of an 313 instructions, if it is not equal to INSN_MACRO. */ 314 315 /* Modifies the general purpose register in OP_*_RD. */ 316 #define INSN_WRITE_GPR_D 0x00000001 317 /* Modifies the general purpose register in OP_*_RT. */ 318 #define INSN_WRITE_GPR_T 0x00000002 319 /* Modifies general purpose register 31. */ 320 #define INSN_WRITE_GPR_31 0x00000004 321 /* Modifies the floating point register in OP_*_FD. */ 322 #define INSN_WRITE_FPR_D 0x00000008 323 /* Modifies the floating point register in OP_*_FS. */ 324 #define INSN_WRITE_FPR_S 0x00000010 325 /* Modifies the floating point register in OP_*_FT. */ 326 #define INSN_WRITE_FPR_T 0x00000020 327 /* Reads the general purpose register in OP_*_RS. */ 328 #define INSN_READ_GPR_S 0x00000040 329 /* Reads the general purpose register in OP_*_RT. */ 330 #define INSN_READ_GPR_T 0x00000080 331 /* Reads the floating point register in OP_*_FS. */ 332 #define INSN_READ_FPR_S 0x00000100 333 /* Reads the floating point register in OP_*_FT. */ 334 #define INSN_READ_FPR_T 0x00000200 335 /* Reads the floating point register in OP_*_FR. */ 336 #define INSN_READ_FPR_R 0x00000400 337 /* Modifies coprocessor condition code. */ 338 #define INSN_WRITE_COND_CODE 0x00000800 339 /* Reads coprocessor condition code. */ 340 #define INSN_READ_COND_CODE 0x00001000 341 /* TLB operation. */ 342 #define INSN_TLB 0x00002000 343 /* Reads coprocessor register other than floating point register. */ 344 #define INSN_COP 0x00004000 345 /* Instruction loads value from memory, requiring delay. */ 346 #define INSN_LOAD_MEMORY_DELAY 0x00008000 347 /* Instruction loads value from coprocessor, requiring delay. */ 348 #define INSN_LOAD_COPROC_DELAY 0x00010000 349 /* Instruction has unconditional branch delay slot. */ 350 #define INSN_UNCOND_BRANCH_DELAY 0x00020000 351 /* Instruction has conditional branch delay slot. */ 352 #define INSN_COND_BRANCH_DELAY 0x00040000 353 /* Conditional branch likely: if branch not taken, insn nullified. */ 354 #define INSN_COND_BRANCH_LIKELY 0x00080000 355 /* Moves to coprocessor register, requiring delay. */ 356 #define INSN_COPROC_MOVE_DELAY 0x00100000 357 /* Loads coprocessor register from memory, requiring delay. */ 358 #define INSN_COPROC_MEMORY_DELAY 0x00200000 359 /* Reads the HI register. */ 360 #define INSN_READ_HI 0x00400000 361 /* Reads the LO register. */ 362 #define INSN_READ_LO 0x00800000 363 /* Modifies the HI register. */ 364 #define INSN_WRITE_HI 0x01000000 365 /* Modifies the LO register. */ 366 #define INSN_WRITE_LO 0x02000000 367 /* Takes a trap (easier to keep out of delay slot). */ 368 #define INSN_TRAP 0x04000000 369 /* Instruction stores value into memory. */ 370 #define INSN_STORE_MEMORY 0x08000000 371 /* Instruction uses single precision floating point. */ 372 #define FP_S 0x10000000 373 /* Instruction uses double precision floating point. */ 374 #define FP_D 0x20000000 375 /* Instruction is part of the tx39's integer multiply family. */ 376 #define INSN_MULT 0x40000000 377 /* Instruction synchronize shared memory. */ 378 #define INSN_SYNC 0x80000000 379 /* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */ 380 #define INSN_READ_MDMX_ACC 0 381 /* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */ 382 #define INSN_WRITE_MDMX_ACC 0 383 384 /* Instruction is actually a macro. It should be ignored by the 385 disassembler, and requires special treatment by the assembler. */ 386 #define INSN_MACRO 0xffffffff 387 388 /* Masks used to mark instructions to indicate which MIPS ISA level 389 they were introduced in. ISAs, as defined below, are logical 390 ORs of these bits, indicating that they support the instructions 391 defined at the given level. */ 392 393 #define INSN_ISA_MASK 0x00000fff 394 #define INSN_ISA1 0x00000001 395 #define INSN_ISA2 0x00000002 396 #define INSN_ISA3 0x00000004 397 #define INSN_ISA4 0x00000008 398 #define INSN_ISA5 0x00000010 399 #define INSN_ISA32 0x00000020 400 #define INSN_ISA64 0x00000040 401 #define INSN_ISA32R2 0x00000080 402 #define INSN_ISA64R2 0x00000100 403 404 /* Masks used for MIPS-defined ASEs. */ 405 #define INSN_ASE_MASK 0x0000f000 406 407 /* MIPS 16 ASE */ 408 #define INSN_MIPS16 0x00002000 409 /* MIPS-3D ASE */ 410 #define INSN_MIPS3D 0x00004000 411 /* MDMX ASE */ 412 #define INSN_MDMX 0x00008000 413 414 /* Chip specific instructions. These are bitmasks. */ 415 416 /* MIPS R4650 instruction. */ 417 #define INSN_4650 0x00010000 418 /* LSI R4010 instruction. */ 419 #define INSN_4010 0x00020000 420 /* NEC VR4100 instruction. */ 421 #define INSN_4100 0x00040000 422 /* Toshiba R3900 instruction. */ 423 #define INSN_3900 0x00080000 424 /* MIPS R10000 instruction. */ 425 #define INSN_10000 0x00100000 426 /* Broadcom SB-1 instruction. */ 427 #define INSN_SB1 0x00200000 428 /* NEC VR4111/VR4181 instruction. */ 429 #define INSN_4111 0x00400000 430 /* NEC VR4120 instruction. */ 431 #define INSN_4120 0x00800000 432 /* NEC VR5400 instruction. */ 433 #define INSN_5400 0x01000000 434 /* NEC VR5500 instruction. */ 435 #define INSN_5500 0x02000000 436 437 /* MIPS ISA defines, use instead of hardcoding ISA level. */ 438 439 #define ISA_UNKNOWN 0 /* Gas internal use. */ 440 #define ISA_MIPS1 (INSN_ISA1) 441 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) 442 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) 443 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) 444 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) 445 446 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) 447 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) 448 449 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) 450 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) 451 452 453 /* CPU defines, use instead of hardcoding processor number. Keep this 454 in sync with bfd/archures.c in order for machine selection to work. */ 455 #define CPU_UNKNOWN 0 /* Gas internal use. */ 456 #define CPU_R3000 3000 457 #define CPU_R3900 3900 458 #define CPU_R4000 4000 459 #define CPU_R4010 4010 460 #define CPU_VR4100 4100 461 #define CPU_R4111 4111 462 #define CPU_VR4120 4120 463 #define CPU_R4300 4300 464 #define CPU_R4400 4400 465 #define CPU_R4600 4600 466 #define CPU_R4650 4650 467 #define CPU_R5000 5000 468 #define CPU_VR5400 5400 469 #define CPU_VR5500 5500 470 #define CPU_R6000 6000 471 #define CPU_RM7000 7000 472 #define CPU_R8000 8000 473 #define CPU_R10000 10000 474 #define CPU_R12000 12000 475 #define CPU_MIPS16 16 476 #define CPU_MIPS32 32 477 #define CPU_MIPS32R2 33 478 #define CPU_MIPS5 5 479 #define CPU_MIPS64 64 480 #define CPU_MIPS64R2 65 481 #define CPU_SB1 12310201 /* octal 'SB', 01. */ 482 483 /* Test for membership in an ISA including chip specific ISAs. INSN 484 is pointer to an element of the opcode table; ISA is the specified 485 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 486 test, or zero if no CPU specific ISA test is desired. */ 487 488 #define OPCODE_IS_MEMBER(insn, isa, cpu) \ 489 (((insn)->membership & isa) != 0 \ 490 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ 491 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ 492 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ 493 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ 494 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ 495 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ 496 && ((insn)->membership & INSN_10000) != 0) \ 497 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ 498 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ 499 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ 500 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ 501 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ 502 || 0) /* Please keep this term for easier source merging. */ 503 504 /* This is a list of macro expanded instructions. 505 506 _I appended means immediate 507 _A appended means address 508 _AB appended means address with base register 509 _D appended means 64 bit floating point constant 510 _S appended means 32 bit floating point constant. */ 511 512 enum 513 { 514 M_ABS, 515 M_ADD_I, 516 M_ADDU_I, 517 M_AND_I, 518 M_BEQ, 519 M_BEQ_I, 520 M_BEQL_I, 521 M_BGE, 522 M_BGEL, 523 M_BGE_I, 524 M_BGEL_I, 525 M_BGEU, 526 M_BGEUL, 527 M_BGEU_I, 528 M_BGEUL_I, 529 M_BGT, 530 M_BGTL, 531 M_BGT_I, 532 M_BGTL_I, 533 M_BGTU, 534 M_BGTUL, 535 M_BGTU_I, 536 M_BGTUL_I, 537 M_BLE, 538 M_BLEL, 539 M_BLE_I, 540 M_BLEL_I, 541 M_BLEU, 542 M_BLEUL, 543 M_BLEU_I, 544 M_BLEUL_I, 545 M_BLT, 546 M_BLTL, 547 M_BLT_I, 548 M_BLTL_I, 549 M_BLTU, 550 M_BLTUL, 551 M_BLTU_I, 552 M_BLTUL_I, 553 M_BNE, 554 M_BNE_I, 555 M_BNEL_I, 556 M_DABS, 557 M_DADD_I, 558 M_DADDU_I, 559 M_DDIV_3, 560 M_DDIV_3I, 561 M_DDIVU_3, 562 M_DDIVU_3I, 563 M_DEXT, 564 M_DINS, 565 M_DIV_3, 566 M_DIV_3I, 567 M_DIVU_3, 568 M_DIVU_3I, 569 M_DLA_AB, 570 M_DLCA_AB, 571 M_DLI, 572 M_DMUL, 573 M_DMUL_I, 574 M_DMULO, 575 M_DMULO_I, 576 M_DMULOU, 577 M_DMULOU_I, 578 M_DREM_3, 579 M_DREM_3I, 580 M_DREMU_3, 581 M_DREMU_3I, 582 M_DSUB_I, 583 M_DSUBU_I, 584 M_DSUBU_I_2, 585 M_JR_S, 586 M_J_S, 587 M_J_A, 588 M_JALR_S, 589 M_JALR_DS, 590 M_JAL_1, 591 M_JAL_2, 592 M_JAL_A, 593 M_L_DOB, 594 M_L_DAB, 595 M_LA_AB, 596 M_LB_A, 597 M_LB_AB, 598 M_LBU_A, 599 M_LBU_AB, 600 M_LCA_AB, 601 M_LD_A, 602 M_LD_OB, 603 M_LD_AB, 604 M_LDC1_AB, 605 M_LDC2_AB, 606 M_LDC3_AB, 607 M_LDL_AB, 608 M_LDR_AB, 609 M_LH_A, 610 M_LH_AB, 611 M_LHU_A, 612 M_LHU_AB, 613 M_LI, 614 M_LI_D, 615 M_LI_DD, 616 M_LI_S, 617 M_LI_SS, 618 M_LL_AB, 619 M_LLD_AB, 620 M_LS_A, 621 M_LW_A, 622 M_LW_AB, 623 M_LWC0_A, 624 M_LWC0_AB, 625 M_LWC1_A, 626 M_LWC1_AB, 627 M_LWC2_A, 628 M_LWC2_AB, 629 M_LWC3_A, 630 M_LWC3_AB, 631 M_LWL_A, 632 M_LWL_AB, 633 M_LWR_A, 634 M_LWR_AB, 635 M_LWU_AB, 636 M_MOVE, 637 M_MUL, 638 M_MUL_I, 639 M_MULO, 640 M_MULO_I, 641 M_MULOU, 642 M_MULOU_I, 643 M_NOR_I, 644 M_OR_I, 645 M_REM_3, 646 M_REM_3I, 647 M_REMU_3, 648 M_REMU_3I, 649 M_DROL, 650 M_ROL, 651 M_DROL_I, 652 M_ROL_I, 653 M_DROR, 654 M_ROR, 655 M_DROR_I, 656 M_ROR_I, 657 M_S_DA, 658 M_S_DOB, 659 M_S_DAB, 660 M_S_S, 661 M_SC_AB, 662 M_SCD_AB, 663 M_SD_A, 664 M_SD_OB, 665 M_SD_AB, 666 M_SDC1_AB, 667 M_SDC2_AB, 668 M_SDC3_AB, 669 M_SDL_AB, 670 M_SDR_AB, 671 M_SEQ, 672 M_SEQ_I, 673 M_SGE, 674 M_SGE_I, 675 M_SGEU, 676 M_SGEU_I, 677 M_SGT, 678 M_SGT_I, 679 M_SGTU, 680 M_SGTU_I, 681 M_SLE, 682 M_SLE_I, 683 M_SLEU, 684 M_SLEU_I, 685 M_SLT_I, 686 M_SLTU_I, 687 M_SNE, 688 M_SNE_I, 689 M_SB_A, 690 M_SB_AB, 691 M_SH_A, 692 M_SH_AB, 693 M_SW_A, 694 M_SW_AB, 695 M_SWC0_A, 696 M_SWC0_AB, 697 M_SWC1_A, 698 M_SWC1_AB, 699 M_SWC2_A, 700 M_SWC2_AB, 701 M_SWC3_A, 702 M_SWC3_AB, 703 M_SWL_A, 704 M_SWL_AB, 705 M_SWR_A, 706 M_SWR_AB, 707 M_SUB_I, 708 M_SUBU_I, 709 M_SUBU_I_2, 710 M_TEQ_I, 711 M_TGE_I, 712 M_TGEU_I, 713 M_TLT_I, 714 M_TLTU_I, 715 M_TNE_I, 716 M_TRUNCWD, 717 M_TRUNCWS, 718 M_ULD, 719 M_ULD_A, 720 M_ULH, 721 M_ULH_A, 722 M_ULHU, 723 M_ULHU_A, 724 M_ULW, 725 M_ULW_A, 726 M_USH, 727 M_USH_A, 728 M_USW, 729 M_USW_A, 730 M_USD, 731 M_USD_A, 732 M_XOR_I, 733 M_COP0, 734 M_COP1, 735 M_COP2, 736 M_COP3, 737 M_NUM_MACROS 738 }; 739 740 741 /* The order of overloaded instructions matters. Label arguments and 742 register arguments look the same. Instructions that can have either 743 for arguments must apear in the correct order in this table for the 744 assembler to pick the right one. In other words, entries with 745 immediate operands must apear after the same instruction with 746 registers. 747 748 Many instructions are short hand for other instructions (i.e., The 749 jal <register> instruction is short for jalr <register>). */ 750 751 extern const struct mips_opcode mips_builtin_opcodes[]; 752 extern const int bfd_mips_num_builtin_opcodes; 753 extern struct mips_opcode *mips_opcodes; 754 extern int bfd_mips_num_opcodes; 755 #define NUMOPCODES bfd_mips_num_opcodes 756 757 758 /* The rest of this file adds definitions for the mips16 TinyRISC 759 processor. */ 760 761 /* These are the bitmasks and shift counts used for the different 762 fields in the instruction formats. Other than OP, no masks are 763 provided for the fixed portions of an instruction, since they are 764 not needed. 765 766 The I format uses IMM11. 767 768 The RI format uses RX and IMM8. 769 770 The RR format uses RX, and RY. 771 772 The RRI format uses RX, RY, and IMM5. 773 774 The RRR format uses RX, RY, and RZ. 775 776 The RRI_A format uses RX, RY, and IMM4. 777 778 The SHIFT format uses RX, RY, and SHAMT. 779 780 The I8 format uses IMM8. 781 782 The I8_MOVR32 format uses RY and REGR32. 783 784 The IR_MOV32R format uses REG32R and MOV32Z. 785 786 The I64 format uses IMM8. 787 788 The RI64 format uses RY and IMM5. 789 */ 790 791 #define MIPS16OP_MASK_OP 0x1f 792 #define MIPS16OP_SH_OP 11 793 #define MIPS16OP_MASK_IMM11 0x7ff 794 #define MIPS16OP_SH_IMM11 0 795 #define MIPS16OP_MASK_RX 0x7 796 #define MIPS16OP_SH_RX 8 797 #define MIPS16OP_MASK_IMM8 0xff 798 #define MIPS16OP_SH_IMM8 0 799 #define MIPS16OP_MASK_RY 0x7 800 #define MIPS16OP_SH_RY 5 801 #define MIPS16OP_MASK_IMM5 0x1f 802 #define MIPS16OP_SH_IMM5 0 803 #define MIPS16OP_MASK_RZ 0x7 804 #define MIPS16OP_SH_RZ 2 805 #define MIPS16OP_MASK_IMM4 0xf 806 #define MIPS16OP_SH_IMM4 0 807 #define MIPS16OP_MASK_REGR32 0x1f 808 #define MIPS16OP_SH_REGR32 0 809 #define MIPS16OP_MASK_REG32R 0x1f 810 #define MIPS16OP_SH_REG32R 3 811 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 812 #define MIPS16OP_MASK_MOVE32Z 0x7 813 #define MIPS16OP_SH_MOVE32Z 0 814 #define MIPS16OP_MASK_IMM6 0x3f 815 #define MIPS16OP_SH_IMM6 5 816 817 /* These are the characters which may appears in the args field of an 818 instruction. They appear in the order in which the fields appear 819 when the instruction is used. Commas and parentheses in the args 820 string are ignored when assembling, and written into the output 821 when disassembling. 822 823 "y" 3 bit register (MIPS16OP_*_RY) 824 "x" 3 bit register (MIPS16OP_*_RX) 825 "z" 3 bit register (MIPS16OP_*_RZ) 826 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 827 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 828 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 829 "0" zero register ($0) 830 "S" stack pointer ($sp or $29) 831 "P" program counter 832 "R" return address register ($ra or $31) 833 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 834 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 835 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 836 "a" 26 bit jump address 837 "e" 11 bit extension value 838 "l" register list for entry instruction 839 "L" register list for exit instruction 840 841 The remaining codes may be extended. Except as otherwise noted, 842 the full extended operand is a 16 bit signed value. 843 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 844 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 845 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 846 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 847 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 848 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 849 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 850 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 851 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 852 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 853 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 854 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 855 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 856 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 857 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 858 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 859 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 860 "q" 11 bit branch address (MIPS16OP_*_IMM11) 861 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 862 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 863 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 864 */ 865 866 /* For the mips16, we use the same opcode table format and a few of 867 the same flags. However, most of the flags are different. */ 868 869 /* Modifies the register in MIPS16OP_*_RX. */ 870 #define MIPS16_INSN_WRITE_X 0x00000001 871 /* Modifies the register in MIPS16OP_*_RY. */ 872 #define MIPS16_INSN_WRITE_Y 0x00000002 873 /* Modifies the register in MIPS16OP_*_RZ. */ 874 #define MIPS16_INSN_WRITE_Z 0x00000004 875 /* Modifies the T ($24) register. */ 876 #define MIPS16_INSN_WRITE_T 0x00000008 877 /* Modifies the SP ($29) register. */ 878 #define MIPS16_INSN_WRITE_SP 0x00000010 879 /* Modifies the RA ($31) register. */ 880 #define MIPS16_INSN_WRITE_31 0x00000020 881 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ 882 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 883 /* Reads the register in MIPS16OP_*_RX. */ 884 #define MIPS16_INSN_READ_X 0x00000080 885 /* Reads the register in MIPS16OP_*_RY. */ 886 #define MIPS16_INSN_READ_Y 0x00000100 887 /* Reads the register in MIPS16OP_*_MOVE32Z. */ 888 #define MIPS16_INSN_READ_Z 0x00000200 889 /* Reads the T ($24) register. */ 890 #define MIPS16_INSN_READ_T 0x00000400 891 /* Reads the SP ($29) register. */ 892 #define MIPS16_INSN_READ_SP 0x00000800 893 /* Reads the RA ($31) register. */ 894 #define MIPS16_INSN_READ_31 0x00001000 895 /* Reads the program counter. */ 896 #define MIPS16_INSN_READ_PC 0x00002000 897 /* Reads the general purpose register in MIPS16OP_*_REGR32. */ 898 #define MIPS16_INSN_READ_GPR_X 0x00004000 899 /* Is a branch insn. */ 900 #define MIPS16_INSN_BRANCH 0x00010000 901 902 /* The following flags have the same value for the mips16 opcode 903 table: 904 INSN_UNCOND_BRANCH_DELAY 905 INSN_COND_BRANCH_DELAY 906 INSN_COND_BRANCH_LIKELY (never used) 907 INSN_READ_HI 908 INSN_READ_LO 909 INSN_WRITE_HI 910 INSN_WRITE_LO 911 INSN_TRAP 912 INSN_ISA3 913 */ 914 915 extern const struct mips_opcode mips16_opcodes[]; 916 extern const int bfd_mips16_num_opcodes; 917 918 #endif /* _MIPS_H_ */ 919