1 /* Definitions of target machine for GNU compiler. 2 Sun 68000/68020 version. 3 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 4 2000, 2001, 2002 Free Software Foundation, Inc. 5 6 This file is part of GNU CC. 7 8 GNU CC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GNU CC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GNU CC; see the file COPYING. If not, write to 20 the Free Software Foundation, 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. */ 22 23 24 /* Note that some other tm.h files include this one and then override 25 many of the definitions that relate to assembler syntax. */ 26 27 28 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI 29 quantities. */ 30 #define INT_OP_STANDARD 0 /* .byte, .short, .long */ 31 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */ 32 #define INT_OP_NO_DOT 2 /* byte, short, long */ 33 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */ 34 35 /* Set the default */ 36 #define INT_OP_GROUP INT_OP_DOT_WORD 37 38 /* Names to predefine in the preprocessor for this target machine. */ 39 40 /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */ 41 42 /* Print subsidiary information on the compiler version in use. */ 43 #ifdef MOTOROLA 44 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)"); 45 #else 46 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)"); 47 #endif 48 49 /* Define SUPPORT_SUN_FPA to include support for generating code for 50 the Sun Floating Point Accelerator, an optional product for Sun 3 51 machines. By default, it is not defined. Avoid defining it unless 52 you need to output code for the Sun3+FPA architecture, as it has the 53 effect of slowing down the register set operations in hard-reg-set.h 54 (total number of registers will exceed number of bits in a long, 55 if defined, causing the set operations to expand to loops). 56 SUPPORT_SUN_FPA is typically defined in sun3.h. */ 57 58 /* Run-time compilation parameters selecting different hardware subsets. */ 59 60 extern int target_flags; 61 62 /* Macros used in the machine description to test the flags. */ 63 64 /* Compile for a 68020 (not a 68000 or 68010). */ 65 #define MASK_68020 1 66 #define TARGET_68020 (target_flags & MASK_68020) 67 68 /* Compile 68881 insns for floating point (not library calls). */ 69 #define MASK_68881 2 70 #define TARGET_68881 (target_flags & MASK_68881) 71 72 /* Compile using 68020 bit-field insns. */ 73 #define MASK_BITFIELD 4 74 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD) 75 76 /* Compile using rtd insn calling sequence. 77 This will not work unless you use prototypes at least 78 for all functions that can take varying numbers of args. */ 79 #define MASK_RTD 8 80 #define TARGET_RTD (target_flags & MASK_RTD) 81 82 /* Compile passing first two args in regs 0 and 1. 83 This exists only to test compiler features that will 84 be needed for RISC chips. It is not usable 85 and is not intended to be usable on this cpu. */ 86 #define MASK_REGPARM 16 87 #define TARGET_REGPARM (target_flags & MASK_REGPARM) 88 89 /* Compile with 16-bit `int'. */ 90 #define MASK_SHORT 32 91 #define TARGET_SHORT (target_flags & MASK_SHORT) 92 93 /* Compile with special insns for Sun FPA. */ 94 #define MASK_FPA 64 95 #define TARGET_FPA (target_flags & MASK_FPA) 96 97 /* Compile (actually, link) for Sun SKY board. */ 98 #define MASK_SKY 128 99 #define TARGET_SKY (target_flags & MASK_SKY) 100 101 /* Optimize for 68040, but still allow execution on 68020 102 (-m68020-40 or -m68040). 103 The 68040 will execute all 68030 and 68881/2 instructions, but some 104 of them must be emulated in software by the OS. When TARGET_68040 is 105 turned on, these instructions won't be used. This code will still 106 run on a 68030 and 68881/2. */ 107 #define MASK_68040 256 108 #define TARGET_68040 (target_flags & MASK_68040) 109 110 /* Use the 68040-only fp instructions (-m68040 or -m68060). */ 111 #define MASK_68040_ONLY 512 112 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY) 113 114 /* Optimize for 68060, but still allow execution on 68020 115 (-m68020-60 or -m68060). 116 The 68060 will execute all 68030 and 68881/2 instructions, but some 117 of them must be emulated in software by the OS. When TARGET_68060 is 118 turned on, these instructions won't be used. This code will still 119 run on a 68030 and 68881/2. */ 120 #define MASK_68060 1024 121 #define TARGET_68060 (target_flags & MASK_68060) 122 123 /* Compile for mcf5200 */ 124 #define MASK_5200 2048 125 #define TARGET_5200 (target_flags & MASK_5200) 126 127 /* Align ints to a word boundary. This breaks compatibility with the 128 published ABI's for structures containing ints, but produces faster 129 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire). 130 It's required for coldfire cpus without a misalignment module. */ 131 #define MASK_ALIGN_INT 4096 132 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT) 133 134 /* Compile for a CPU32 */ 135 /* A 68020 without bitfields is a good heuristic for a CPU32 */ 136 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD) 137 138 /* Use PC-relative addressing modes (without using a global offset table). 139 The m68000 supports 16-bit PC-relative addressing. 140 The m68020 supports 32-bit PC-relative addressing 141 (using outer displacements). 142 143 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are 144 treated as all containing an implicit PC-relative component, and hence 145 cannot be used directly as addresses for memory writes. See the comments 146 in m68k.c for more information. */ 147 #define MASK_PCREL 8192 148 #define TARGET_PCREL (target_flags & MASK_PCREL) 149 150 /* Relax strict alignment. */ 151 #define MASK_NO_STRICT_ALIGNMENT 16384 152 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT) 153 154 /* Macro to define tables used to set the flags. 155 This is a list in braces of pairs in braces, 156 each pair being { "NAME", VALUE } 157 where VALUE is the bits to set or minus the bits to clear. 158 An empty string NAME is used to identify the default VALUE. */ 159 160 #define TARGET_SWITCHES \ 161 { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ 162 N_("Generate code for a 68020") }, \ 163 { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ 164 N_("Generate code for a 68020") }, \ 165 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \ 166 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \ 167 { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ 168 |MASK_68020|MASK_BITFIELD|MASK_68881), \ 169 N_("Generate code for a 68000") }, \ 170 { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ 171 |MASK_68020|MASK_BITFIELD|MASK_68881), \ 172 N_("Generate code for a 68000") }, \ 173 { "bitfield", MASK_BITFIELD, \ 174 N_("Use the bit-field instructions") }, \ 175 { "nobitfield", - MASK_BITFIELD, \ 176 N_("Do not use the bit-field instructions") }, \ 177 { "rtd", MASK_RTD, \ 178 N_("Use different calling convention using 'rtd'") }, \ 179 { "nortd", - MASK_RTD, \ 180 N_("Use normal calling convention") }, \ 181 { "short", MASK_SHORT, \ 182 N_("Consider type `int' to be 16 bits wide") }, \ 183 { "noshort", - MASK_SHORT, \ 184 N_("Consider type `int' to be 32 bits wide") }, \ 185 { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881), \ 186 N_("Generate code for a Sun FPA") }, \ 187 { "fpa", MASK_FPA, "" }, \ 188 { "nofpa", - MASK_FPA, \ 189 N_("Do not generate code for a Sun FPA") }, \ 190 { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881), \ 191 N_("Generate code for a Sun Sky board") }, \ 192 { "sky", MASK_SKY, \ 193 N_("Generate code for a Sun Sky board") }, \ 194 { "nosky", - MASK_SKY, \ 195 N_("Do not use Sky linkage convention") }, \ 196 { "68881", - (MASK_FPA|MASK_SKY), \ 197 N_("Generate code for a 68881") }, \ 198 { "68881", MASK_68881, "" }, \ 199 { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881), \ 200 N_("Generate code with library calls for floating point") }, \ 201 { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY), \ 202 N_("Generate code for a 68040, without any new instructions") }, \ 203 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\ 204 { "68020-60", -(MASK_5200|MASK_68040_ONLY), \ 205 N_("Generate code for a 68060, without any new instructions") }, \ 206 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \ 207 |MASK_68060), "" }, \ 208 { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ 209 N_("Generate code for a 68030") }, \ 210 { "68030", (MASK_68020|MASK_BITFIELD), "" }, \ 211 { "68040", - (MASK_5200|MASK_68060), \ 212 N_("Generate code for a 68040") }, \ 213 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \ 214 |MASK_68040_ONLY|MASK_68040), "" }, \ 215 { "68060", - (MASK_5200|MASK_68040), \ 216 N_("Generate code for a 68060") }, \ 217 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \ 218 |MASK_68040_ONLY|MASK_68060), "" }, \ 219 { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ 220 |MASK_BITFIELD|MASK_68881), \ 221 N_("Generate code for a 520X") }, \ 222 { "5200", (MASK_5200), "" }, \ 223 { "68851", 0, \ 224 N_("Generate code for a 68851") }, \ 225 { "no-68851", 0, \ 226 N_("Do no generate code for a 68851") }, \ 227 { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ 228 |MASK_68020|MASK_BITFIELD|MASK_68881), \ 229 N_("Generate code for a 68302") }, \ 230 { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ 231 |MASK_BITFIELD|MASK_68881), \ 232 N_("Generate code for a 68332") }, \ 233 { "68332", MASK_68020, "" }, \ 234 { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ 235 |MASK_BITFIELD|MASK_68881), \ 236 N_("Generate code for a cpu32") }, \ 237 { "cpu32", MASK_68020, "" }, \ 238 { "align-int", MASK_ALIGN_INT, \ 239 N_("Align variables on a 32-bit boundary") }, \ 240 { "no-align-int", -MASK_ALIGN_INT, \ 241 N_("Align variables on a 16-bit boundary") }, \ 242 { "pcrel", MASK_PCREL, \ 243 N_("Generate pc-relative code") }, \ 244 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \ 245 N_("Do not use unaligned memory references") }, \ 246 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \ 247 N_("Use unaligned memory references") }, \ 248 SUBTARGET_SWITCHES \ 249 { "", TARGET_DEFAULT, "" }} 250 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */ 251 252 /* This macro is similar to `TARGET_SWITCHES' but defines names of 253 command options that have values. Its definition is an 254 initializer with a subgrouping for each command option. 255 256 Each subgrouping contains a string constant, that defines the 257 fixed part of the option name, and the address of a variable. The 258 variable, type `char *', is set to the variable part of the given 259 option if the fixed part matches. The actual option name is made 260 by appending `-m' to the specified name. */ 261 #define TARGET_OPTIONS \ 262 { { "align-loops=", &m68k_align_loops_string, \ 263 N_("Loop code aligned to this power of 2") }, \ 264 { "align-jumps=", &m68k_align_jumps_string, \ 265 N_("Jump targets are aligned to this power of 2") }, \ 266 { "align-functions=", &m68k_align_funcs_string, \ 267 N_("Function starts are aligned to this power of 2") }, \ 268 SUBTARGET_OPTIONS \ 269 } 270 271 /* Sometimes certain combinations of command options do not make 272 sense on a particular target machine. You can define a macro 273 `OVERRIDE_OPTIONS' to take account of this. This macro, if 274 defined, is executed once just after all the command options have 275 been parsed. 276 277 Don't use this macro to turn on various extra optimizations for 278 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 279 280 #define OVERRIDE_OPTIONS override_options() 281 282 /* These are meant to be redefined in the host dependent files */ 283 #define SUBTARGET_SWITCHES 284 #define SUBTARGET_OPTIONS 285 #define SUBTARGET_OVERRIDE_OPTIONS 286 287 /* target machine storage layout */ 288 289 /* Define for XFmode extended real floating point support. */ 290 #define LONG_DOUBLE_TYPE_SIZE 96 291 292 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp 293 instructions, we get proper intermediate rounding, otherwise we 294 get extended precision results. */ 295 #define TARGET_FLT_EVAL_METHOD (TARGET_68040_ONLY ? 0 : 2) 296 297 /* Define this if most significant bit is lowest numbered 298 in instructions that operate on numbered bit-fields. 299 This is true for 68020 insns such as bfins and bfexts. 300 We make it true always by avoiding using the single-bit insns 301 except in special cases with constant bit numbers. */ 302 #define BITS_BIG_ENDIAN 1 303 304 /* Define this if most significant byte of a word is the lowest numbered. */ 305 /* That is true on the 68000. */ 306 #define BYTES_BIG_ENDIAN 1 307 308 /* Define this if most significant word of a multiword number is the lowest 309 numbered. */ 310 /* For 68000 we can decide arbitrarily 311 since there are no machine instructions for them. 312 So let's be consistent. */ 313 #define WORDS_BIG_ENDIAN 1 314 315 /* Width of a word, in units (bytes). */ 316 #define UNITS_PER_WORD 4 317 318 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 319 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) 320 321 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 322 #define STACK_BOUNDARY 16 323 324 /* Allocation boundary (in *bits*) for the code of a function. */ 325 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3)) 326 327 /* Alignment of field after `int : 0' in a structure. */ 328 #define EMPTY_FIELD_BOUNDARY 16 329 330 /* No data type wants to be aligned rounder than this. 331 Most published ABIs say that ints should be aligned on 16 bit 332 boundaries, but cpus with 32 bit busses get better performance 333 aligned on 32 bit boundaries. Coldfires without a misalignment 334 module require 32 bit alignment. */ 335 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) 336 337 /* Set this nonzero if move instructions will actually fail to work 338 when given unaligned data. */ 339 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT) 340 341 /* Maximum power of 2 that code can be aligned to. */ 342 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */ 343 344 /* Align loop starts for optimal branching. */ 345 #define LOOP_ALIGN(LABEL) (m68k_align_loops) 346 347 /* This is how to align an instruction for optimal branching. */ 348 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps) 349 350 /* Define number of bits in most basic integer type. 351 (If undefined, default is BITS_PER_WORD). */ 352 353 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 354 355 /* Define these to avoid dependence on meaning of `int'. */ 356 357 #define WCHAR_TYPE "long int" 358 #define WCHAR_TYPE_SIZE 32 359 360 /* Standard register usage. */ 361 362 /* Number of actual hardware registers. 363 The hardware registers are assigned numbers for the compiler 364 from 0 to just below FIRST_PSEUDO_REGISTER. 365 All registers that the compiler knows about must be given numbers, 366 even those that are not normally considered general registers. 367 For the 68000, we give the data registers numbers 0-7, 368 the address registers numbers 010-017, 369 and the 68881 floating point registers numbers 020-027. */ 370 #ifndef SUPPORT_SUN_FPA 371 #define FIRST_PSEUDO_REGISTER 24 372 #else 373 #define FIRST_PSEUDO_REGISTER 56 374 #endif 375 376 /* This defines the register which is used to hold the offset table for PIC. */ 377 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM) 378 379 #ifndef SUPPORT_SUN_FPA 380 381 /* 1 for registers that have pervasive standard uses 382 and are not available for the register allocator. 383 On the 68000, only the stack pointer is such. */ 384 385 #define FIXED_REGISTERS \ 386 {/* Data registers. */ \ 387 0, 0, 0, 0, 0, 0, 0, 0, \ 388 \ 389 /* Address registers. */ \ 390 0, 0, 0, 0, 0, 0, 0, 1, \ 391 \ 392 /* Floating point registers \ 393 (if available). */ \ 394 0, 0, 0, 0, 0, 0, 0, 0 } 395 396 /* 1 for registers not available across function calls. 397 These must include the FIXED_REGISTERS and also any 398 registers that can be used without being saved. 399 The latter must include the registers where values are returned 400 and the register where structure-value addresses are passed. 401 Aside from that, you can include as many other registers as you like. */ 402 #define CALL_USED_REGISTERS \ 403 {1, 1, 0, 0, 0, 0, 0, 0, \ 404 1, 1, 0, 0, 0, 0, 0, 1, \ 405 1, 1, 0, 0, 0, 0, 0, 0 } 406 407 #else /* SUPPORT_SUN_FPA */ 408 409 /* 1 for registers that have pervasive standard uses 410 and are not available for the register allocator. 411 On the 68000, only the stack pointer is such. */ 412 413 /* fpa0 is also reserved so that it can be used to move data back and 414 forth between high fpa regs and everything else. */ 415 416 #define FIXED_REGISTERS \ 417 {/* Data registers. */ \ 418 0, 0, 0, 0, 0, 0, 0, 0, \ 419 \ 420 /* Address registers. */ \ 421 0, 0, 0, 0, 0, 0, 0, 1, \ 422 \ 423 /* Floating point registers \ 424 (if available). */ \ 425 0, 0, 0, 0, 0, 0, 0, 0, \ 426 \ 427 /* Sun3 FPA registers. */ \ 428 1, 0, 0, 0, 0, 0, 0, 0, \ 429 0, 0, 0, 0, 0, 0, 0, 0, \ 430 0, 0, 0, 0, 0, 0, 0, 0, \ 431 0, 0, 0, 0, 0, 0, 0, 0 } 432 433 /* 1 for registers not available across function calls. 434 These must include the FIXED_REGISTERS and also any 435 registers that can be used without being saved. 436 The latter must include the registers where values are returned 437 and the register where structure-value addresses are passed. 438 Aside from that, you can include as many other registers as you like. */ 439 #define CALL_USED_REGISTERS \ 440 {1, 1, 0, 0, 0, 0, 0, 0, \ 441 1, 1, 0, 0, 0, 0, 0, 1, \ 442 1, 1, 0, 0, 0, 0, 0, 0, \ 443 /* FPA registers. */ \ 444 1, 1, 1, 1, 0, 0, 0, 0, \ 445 0, 0, 0, 0, 0, 0, 0, 0, \ 446 0, 0, 0, 0, 0, 0, 0, 0, \ 447 0, 0, 0, 0, 0, 0, 0, 0 } 448 449 #endif /* defined SUPPORT_SUN_FPA */ 450 451 452 /* Make sure everything's fine if we *don't* have a given processor. 453 This assumes that putting a register in fixed_regs will keep the 454 compiler's mitts completely off it. We don't bother to zero it out 455 of register classes. */ 456 457 #ifdef SUPPORT_SUN_FPA 458 459 #define CONDITIONAL_REGISTER_USAGE \ 460 { \ 461 int i; \ 462 HARD_REG_SET x; \ 463 if (! TARGET_FPA) \ 464 { \ 465 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \ 466 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ 467 if (TEST_HARD_REG_BIT (x, i)) \ 468 fixed_regs[i] = call_used_regs[i] = 1; \ 469 } \ 470 if (! TARGET_68881) \ 471 { \ 472 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ 473 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ 474 if (TEST_HARD_REG_BIT (x, i)) \ 475 fixed_regs[i] = call_used_regs[i] = 1; \ 476 } \ 477 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 478 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ 479 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 480 } 481 #else 482 #define CONDITIONAL_REGISTER_USAGE \ 483 { \ 484 int i; \ 485 HARD_REG_SET x; \ 486 if (! TARGET_68881) \ 487 { \ 488 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ 489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ 490 if (TEST_HARD_REG_BIT (x, i)) \ 491 fixed_regs[i] = call_used_regs[i] = 1; \ 492 } \ 493 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 494 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ 495 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 496 } 497 498 #endif /* defined SUPPORT_SUN_FPA */ 499 500 /* Return number of consecutive hard regs needed starting at reg REGNO 501 to hold something of mode MODE. 502 This is ordinarily the length in words of a value of mode MODE 503 but can be less for certain modes in special long registers. 504 505 On the 68000, ordinary registers hold 32 bits worth; 506 for the 68881 registers, a single register is always enough for 507 anything that can be stored in them at all. */ 508 #define HARD_REGNO_NREGS(REGNO, MODE) \ 509 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ 510 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 511 512 #ifndef SUPPORT_SUN_FPA 513 514 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 515 On the 68000, the cpu registers can hold any mode but the 68881 registers 516 can hold only SFmode or DFmode. */ 517 518 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 519 (((REGNO) < 16 \ 520 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \ 521 || ((REGNO) >= 16 && (REGNO) < 24 \ 522 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 523 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 524 && GET_MODE_UNIT_SIZE (MODE) <= 12)) 525 526 #else /* defined SUPPORT_SUN_FPA */ 527 528 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 529 On the 68000, the cpu registers can hold any mode but the 68881 registers 530 can hold only SFmode or DFmode. However, the Sun FPA register can 531 (apparently) hold whatever you feel like putting in them. 532 If using the fpa, don't put a double in d7/a0. */ 533 534 /* ??? This is confused. The check to prohibit d7/a0 overlaps should always 535 be enabled regardless of whether TARGET_FPA is specified. It isn't clear 536 what the other d/a register checks are for. Every check using REGNO 537 actually needs to use a range, e.g. 24>=X<56 not <56. There is probably 538 no one using this code anymore. 539 This code used to be used to suppress register usage for the 68881 by 540 saying that the 68881 registers couldn't hold values of any mode if there 541 was no 68881. This was wrong, because reload (etc.) will still try 542 to save and restore call-saved registers during, for instance, non-local 543 goto. */ 544 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 545 (((REGNO) < 16 \ 546 && !(TARGET_FPA \ 547 && GET_MODE_CLASS ((MODE)) != MODE_INT \ 548 && GET_MODE_UNIT_SIZE ((MODE)) > 4 \ 549 && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \ 550 && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \ 551 || ((REGNO) >= 16 && (REGNO) < 24 \ 552 ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \ 553 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 554 && GET_MODE_UNIT_SIZE (MODE) <= 12) \ 555 : ((REGNO) < 56 ? TARGET_FPA && GET_MODE_UNIT_SIZE (MODE) <= 8 : 0))) 556 557 #endif /* defined SUPPORT_SUN_FPA */ 558 559 /* Value is 1 if it is a good idea to tie two pseudo registers 560 when one has mode MODE1 and one has mode MODE2. 561 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 562 for any hard reg, then this must be 0 for correct output. */ 563 #define MODES_TIEABLE_P(MODE1, MODE2) \ 564 (! TARGET_68881 \ 565 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 566 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 567 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 568 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) 569 570 /* Specify the registers used for certain standard purposes. 571 The values of these macros are register numbers. */ 572 573 /* m68000 pc isn't overloaded on a register. */ 574 /* #define PC_REGNUM */ 575 576 /* Register to use for pushing function arguments. */ 577 #define STACK_POINTER_REGNUM 15 578 579 /* Base register for access to local variables of the function. */ 580 #define FRAME_POINTER_REGNUM 14 581 582 /* Value should be nonzero if functions must have frame pointers. 583 Zero means the frame pointer need not be set up (and parms 584 may be accessed via the stack pointer) in functions that seem suitable. 585 This is computed in `reload', in reload1.c. */ 586 #define FRAME_POINTER_REQUIRED 0 587 588 /* Base register for access to arguments of the function. */ 589 #define ARG_POINTER_REGNUM 14 590 591 /* Register in which static-chain is passed to a function. */ 592 #define STATIC_CHAIN_REGNUM 8 593 594 /* Register in which address to store a structure value 595 is passed to a function. */ 596 #define STRUCT_VALUE_REGNUM 9 597 598 /* Define the classes of registers for register constraints in the 599 machine description. Also define ranges of constants. 600 601 One of the classes must always be named ALL_REGS and include all hard regs. 602 If there is more than one class, another class must be named NO_REGS 603 and contain no registers. 604 605 The name GENERAL_REGS must be the name of a class (or an alias for 606 another name such as ALL_REGS). This is the class of registers 607 that is allowed by "g" or "r" in a register constraint. 608 Also, registers outside this class are allocated only when 609 instructions express preferences for them. 610 611 The classes must be numbered in nondecreasing order; that is, 612 a larger-numbered class must never be contained completely 613 in a smaller-numbered class. 614 615 For any two classes, it is very desirable that there be another 616 class that represents their union. */ 617 618 /* The 68000 has three kinds of registers, so eight classes would be 619 a complete set. One of them is not needed. */ 620 621 #ifndef SUPPORT_SUN_FPA 622 623 enum reg_class { 624 NO_REGS, DATA_REGS, 625 ADDR_REGS, FP_REGS, 626 GENERAL_REGS, DATA_OR_FP_REGS, 627 ADDR_OR_FP_REGS, ALL_REGS, 628 LIM_REG_CLASSES }; 629 630 #define N_REG_CLASSES (int) LIM_REG_CLASSES 631 632 /* Give names of register classes as strings for dump file. */ 633 634 #define REG_CLASS_NAMES \ 635 { "NO_REGS", "DATA_REGS", \ 636 "ADDR_REGS", "FP_REGS", \ 637 "GENERAL_REGS", "DATA_OR_FP_REGS", \ 638 "ADDR_OR_FP_REGS", "ALL_REGS" } 639 640 /* Define which registers fit in which classes. 641 This is an initializer for a vector of HARD_REG_SET 642 of length N_REG_CLASSES. */ 643 644 #define REG_CLASS_CONTENTS \ 645 { \ 646 {0x00000000}, /* NO_REGS */ \ 647 {0x000000ff}, /* DATA_REGS */ \ 648 {0x0000ff00}, /* ADDR_REGS */ \ 649 {0x00ff0000}, /* FP_REGS */ \ 650 {0x0000ffff}, /* GENERAL_REGS */ \ 651 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \ 652 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \ 653 {0x00ffffff}, /* ALL_REGS */ \ 654 } 655 656 /* The same information, inverted: 657 Return the class number of the smallest class containing 658 reg number REGNO. This could be a conditional expression 659 or could index an array. */ 660 661 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1) 662 663 #else /* defined SUPPORT_SUN_FPA */ 664 665 /* 666 * Notes on final choices: 667 * 668 * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything 669 * else. 670 * 2) Removed all unions that involve address registers with 671 * floating point registers (left in unions of address and data with 672 * floating point). 673 * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS. 674 * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS. 675 * 4) Left in everything else. 676 */ 677 enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS, 678 FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS, 679 DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS, 680 GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS, 681 LIM_REG_CLASSES }; 682 683 #define N_REG_CLASSES (int) LIM_REG_CLASSES 684 685 /* Give names of register classes as strings for dump file. */ 686 687 #define REG_CLASS_NAMES \ 688 { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \ 689 "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \ 690 "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \ 691 "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" } 692 693 /* Define which registers fit in which classes. 694 This is an initializer for a vector of HARD_REG_SET 695 of length N_REG_CLASSES. */ 696 697 #define REG_CLASS_CONTENTS \ 698 { \ 699 {0, 0}, /* NO_REGS */ \ 700 {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \ 701 {0xff000000, 0x00ffffff}, /* FPA_REGS */ \ 702 {0x00ff0000, 0x00000000}, /* FP_REGS */ \ 703 {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \ 704 {0x000000ff, 0x00000000}, /* DATA_REGS */ \ 705 {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \ 706 {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \ 707 {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\ 708 {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \ 709 {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \ 710 {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\ 711 {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\ 712 {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \ 713 } 714 715 /* The same information, inverted: 716 Return the class number of the smallest class containing 717 reg number REGNO. This could be a conditional expression 718 or could index an array. */ 719 720 extern const enum reg_class regno_reg_class[]; 721 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3]) 722 723 #endif /* SUPPORT_SUN_FPA */ 724 725 /* The class value for index registers, and the one for base regs. */ 726 727 #define INDEX_REG_CLASS GENERAL_REGS 728 #define BASE_REG_CLASS ADDR_REGS 729 730 /* Get reg_class from a letter such as appears in the machine description. 731 We do a trick here to modify the effective constraints on the 732 machine description; we zorch the constraint letters that aren't 733 appropriate for a specific target. This allows us to guarantee 734 that a specific kind of register will not be used for a given target 735 without fiddling with the register classes above. */ 736 737 #ifndef SUPPORT_SUN_FPA 738 739 #define REG_CLASS_FROM_LETTER(C) \ 740 ((C) == 'a' ? ADDR_REGS : \ 741 ((C) == 'd' ? DATA_REGS : \ 742 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ 743 NO_REGS) : \ 744 NO_REGS))) 745 746 #else /* defined SUPPORT_SUN_FPA */ 747 748 #define REG_CLASS_FROM_LETTER(C) \ 749 ((C) == 'a' ? ADDR_REGS : \ 750 ((C) == 'd' ? DATA_REGS : \ 751 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ 752 NO_REGS) : \ 753 ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \ 754 NO_REGS) : \ 755 ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \ 756 NO_REGS) : \ 757 NO_REGS))))) 758 759 #endif /* defined SUPPORT_SUN_FPA */ 760 761 /* The letters I, J, K, L and M in a register constraint string 762 can be used to stand for particular ranges of immediate operands. 763 This macro defines what the ranges are. 764 C is the letter, and VALUE is a constant value. 765 Return 1 if VALUE is in the range specified by C. 766 767 For the 68000, `I' is used for the range 1 to 8 768 allowed as immediate shift counts and in addq. 769 `J' is used for the range of signed numbers that fit in 16 bits. 770 `K' is for numbers that moveq can't handle. 771 `L' is for range -8 to -1, range of values that can be added with subq. 772 `M' is for numbers that moveq+notb can't handle. 773 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate. 774 'O' is for 16 (for rotate using swap). 775 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */ 776 777 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 778 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ 779 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ 780 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ 781 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \ 782 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \ 783 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \ 784 (C) == 'O' ? (VALUE) == 16 : \ 785 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0) 786 787 /* 788 * A small bit of explanation: 789 * "G" defines all of the floating constants that are *NOT* 68881 790 * constants. this is so 68881 constants get reloaded and the 791 * fpmovecr is used. "H" defines *only* the class of constants that 792 * the fpa can use, because these can be gotten at in any fpa 793 * instruction and there is no need to force reloads. 794 */ 795 #ifndef SUPPORT_SUN_FPA 796 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 797 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 ) 798 #else /* defined SUPPORT_SUN_FPA */ 799 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 800 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \ 801 (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0) 802 #endif /* defined SUPPORT_SUN_FPA */ 803 804 /* A C expression that defines the optional machine-dependent constraint 805 letters that can be used to segregate specific types of operands, 806 usually memory references, for the target machine. It should return 1 if 807 VALUE corresponds to the operand type represented by the constraint letter 808 C. If C is not defined as an extra constraint, the value returned should 809 be 0 regardless of VALUE. */ 810 811 /* Letters in the range `Q' through `U' may be defined in a 812 machine-dependent fashion to stand for arbitrary operand types. 813 The machine description macro `EXTRA_CONSTRAINT' is passed the 814 operand as its first argument and the constraint letter as its 815 second operand. 816 817 `Q' means address register indirect addressing mode. 818 `S' is for operands that satisfy 'm' when -mpcrel is in effect. 819 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */ 820 821 #define EXTRA_CONSTRAINT(OP,CODE) \ 822 (((CODE) == 'S') \ 823 ? (TARGET_PCREL \ 824 && GET_CODE (OP) == MEM \ 825 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ 826 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \ 827 || GET_CODE (XEXP (OP, 0)) == CONST)) \ 828 : \ 829 (((CODE) == 'T') \ 830 ? ( !TARGET_PCREL \ 831 && (GET_CODE (OP) == SYMBOL_REF \ 832 || GET_CODE (OP) == LABEL_REF \ 833 || GET_CODE (OP) == CONST)) \ 834 : \ 835 (((CODE) == 'Q') \ 836 ? (GET_CODE (OP) == MEM \ 837 && GET_CODE (XEXP (OP, 0)) == REG) \ 838 : \ 839 0))) 840 841 /* Given an rtx X being reloaded into a reg required to be 842 in class CLASS, return the class of reg to actually use. 843 In general this is just CLASS; but on some machines 844 in some cases it is preferable to use a more restrictive class. 845 On the 68000 series, use a data reg if possible when the 846 value is a constant in the range where moveq could be used 847 and we ensure that QImodes are reloaded into data regs. */ 848 849 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 850 ((GET_CODE (X) == CONST_INT \ 851 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ 852 && (CLASS) != ADDR_REGS) \ 853 ? DATA_REGS \ 854 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \ 855 ? DATA_REGS \ 856 : (GET_CODE (X) == CONST_DOUBLE \ 857 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ 858 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \ 859 ? FP_REGS : NO_REGS) \ 860 : (TARGET_PCREL \ 861 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ 862 || GET_CODE (X) == LABEL_REF)) \ 863 ? ADDR_REGS \ 864 : (CLASS)) 865 866 /* Force QImode output reloads from subregs to be allocated to data regs, 867 since QImode stores from address regs are not supported. We make the 868 assumption that if the class is not ADDR_REGS, then it must be a superset 869 of DATA_REGS. */ 870 871 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 872 (((MODE) == QImode && (CLASS) != ADDR_REGS) \ 873 ? DATA_REGS \ 874 : (CLASS)) 875 876 /* Return the maximum number of consecutive registers 877 needed to represent mode MODE in a register of class CLASS. */ 878 /* On the 68000, this is the size of MODE in words, 879 except in the FP regs, where a single reg is always enough. */ 880 #ifndef SUPPORT_SUN_FPA 881 882 #define CLASS_MAX_NREGS(CLASS, MODE) \ 883 ((CLASS) == FP_REGS ? 1 \ 884 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 885 886 /* Moves between fp regs and other regs are two insns. */ 887 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 888 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ 889 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ 890 ? 4 : 2) 891 892 #else /* defined SUPPORT_SUN_FPA */ 893 894 #define CLASS_MAX_NREGS(CLASS, MODE) \ 895 ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \ 896 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 897 898 /* Moves between fp regs and other regs are two insns. */ 899 /* Likewise for high fpa regs and other regs. */ 900 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 901 ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ 902 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ 903 || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \ 904 || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \ 905 ? 4 : 2) 906 907 #endif /* define SUPPORT_SUN_FPA */ 908 909 /* Stack layout; function entry, exit and calling. */ 910 911 /* Define this if pushing a word on the stack 912 makes the stack pointer a smaller address. */ 913 #define STACK_GROWS_DOWNWARD 914 915 /* Nonzero if we need to generate stack-probe insns. 916 On most systems they are not needed. 917 When they are needed, define this as the stack offset to probe at. */ 918 #define NEED_PROBE 0 919 920 /* Define this if the nominal address of the stack frame 921 is at the high-address end of the local variables; 922 that is, each additional local variable allocated 923 goes at a more negative offset in the frame. */ 924 #define FRAME_GROWS_DOWNWARD 925 926 /* Offset within stack frame to start allocating local variables at. 927 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 928 first local allocated. Otherwise, it is the offset to the BEGINNING 929 of the first local allocated. */ 930 #define STARTING_FRAME_OFFSET 0 931 932 /* If we generate an insn to push BYTES bytes, 933 this says how many the stack pointer really advances by. 934 On the 68000, sp@- in a byte insn really pushes a word. 935 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */ 936 #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1) 937 938 /* We want to avoid trying to push bytes. */ 939 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ 940 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \ 941 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200))) 942 943 /* Offset of first parameter from the argument pointer register value. */ 944 #define FIRST_PARM_OFFSET(FNDECL) 8 945 946 /* Value is the number of byte of arguments automatically 947 popped when returning from a subroutine call. 948 FUNDECL is the declaration node of the function (as a tree), 949 FUNTYPE is the data type of the function (as a tree), 950 or for a library call it is an identifier node for the subroutine name. 951 SIZE is the number of bytes of arguments passed on the stack. 952 953 On the 68000, the RTS insn cannot pop anything. 954 On the 68010, the RTD insn may be used to pop them if the number 955 of args is fixed, but if the number is variable then the caller 956 must pop them all. RTD can't be used for library calls now 957 because the library is compiled with the Unix compiler. 958 Use of RTD is a selectable option, since it is incompatible with 959 standard Unix calling sequences. If the option is not selected, 960 the caller must always pop the args. */ 961 962 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ 963 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \ 964 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ 965 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ 966 == void_type_node))) \ 967 ? (SIZE) : 0) 968 969 /* Define how to find the value returned by a function. 970 VALTYPE is the data type of the value (as a tree). 971 If the precise function being called is known, FUNC is its FUNCTION_DECL; 972 otherwise, FUNC is 0. */ 973 974 /* On the 68000 the return value is in D0 regardless. */ 975 976 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 977 gen_rtx_REG (TYPE_MODE (VALTYPE), 0) 978 979 /* Define how to find the value returned by a library function 980 assuming the value has mode MODE. */ 981 982 /* On the 68000 the return value is in D0 regardless. */ 983 984 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) 985 986 /* 1 if N is a possible register number for a function value. 987 On the 68000, d0 is the only register thus used. */ 988 989 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) 990 991 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for 992 more than one register. */ 993 994 #define NEEDS_UNTYPED_CALL 0 995 996 /* Define this if PCC uses the nonreentrant convention for returning 997 structure and union values. */ 998 999 #define PCC_STATIC_STRUCT_RETURN 1000 1001 /* 1 if N is a possible register number for function argument passing. 1002 On the 68000, no registers are used in this way. */ 1003 1004 #define FUNCTION_ARG_REGNO_P(N) 0 1005 1006 /* Define a data type for recording info about an argument list 1007 during the scan of that argument list. This data type should 1008 hold all necessary information about the function itself 1009 and about the args processed so far, enough to enable macros 1010 such as FUNCTION_ARG to determine where the next arg should go. 1011 1012 On the m68k, this is a single integer, which is a number of bytes 1013 of arguments scanned so far. */ 1014 1015 #define CUMULATIVE_ARGS int 1016 1017 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1018 for a call to a function whose data type is FNTYPE. 1019 For a library call, FNTYPE is 0. 1020 1021 On the m68k, the offset starts at 0. */ 1022 1023 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ 1024 ((CUM) = 0) 1025 1026 /* Update the data in CUM to advance over an argument 1027 of mode MODE and data type TYPE. 1028 (TYPE is null for libcalls where that information may not be available.) */ 1029 1030 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1031 ((CUM) += ((MODE) != BLKmode \ 1032 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ 1033 : (int_size_in_bytes (TYPE) + 3) & ~3)) 1034 1035 /* Define where to put the arguments to a function. 1036 Value is zero to push the argument on the stack, 1037 or a hard register in which to store the argument. 1038 1039 MODE is the argument's machine mode. 1040 TYPE is the data type of the argument (as a tree). 1041 This is null for libcalls where that information may 1042 not be available. 1043 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1044 the preceding args and about the function being called. 1045 NAMED is nonzero if this argument is a named parameter 1046 (otherwise it is an extra parameter matching an ellipsis). */ 1047 1048 /* On the 68000 all args are pushed, except if -mregparm is specified 1049 then the first two words of arguments are passed in d0, d1. 1050 *NOTE* -mregparm does not work. 1051 It exists only to test register calling conventions. */ 1052 1053 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1054 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0) 1055 1056 /* For an arg passed partly in registers and partly in memory, 1057 this is the number of registers used. 1058 For args passed entirely in registers or entirely in memory, zero. */ 1059 1060 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1061 ((TARGET_REGPARM && (CUM) < 8 \ 1062 && 8 < ((CUM) + ((MODE) == BLKmode \ 1063 ? int_size_in_bytes (TYPE) \ 1064 : GET_MODE_SIZE (MODE)))) \ 1065 ? 2 - (CUM) / 4 : 0) 1066 1067 /* Output assembler code to FILE to increment profiler label # LABELNO 1068 for profiling a function entry. */ 1069 1070 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1071 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) 1072 1073 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1074 the stack pointer does not matter. The value is tested only in 1075 functions that have frame pointers. 1076 No definition is equivalent to always zero. */ 1077 1078 #define EXIT_IGNORE_STACK 1 1079 1080 /* This is a hook for other tm files to change. */ 1081 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */ 1082 1083 /* Determine if the epilogue should be output as RTL. 1084 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1085 #define USE_RETURN_INSN use_return_insn () 1086 1087 /* Store in the variable DEPTH the initial difference between the 1088 frame pointer reg contents and the stack pointer reg contents, 1089 as of the start of the function body. This depends on the layout 1090 of the fixed parts of the stack frame and on how registers are saved. 1091 1092 On the 68k, if we have a frame, we must add one word to its length 1093 to allow for the place that a6 is stored when we do have a frame pointer. 1094 Otherwise, we would need to compute the offset from the frame pointer 1095 of a local variable as a function of frame_pointer_needed, which 1096 is hard. */ 1097 1098 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ 1099 { int regno; \ 1100 int offset = -4; \ 1101 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ 1102 if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 1103 offset += 12; \ 1104 for (regno = 0; regno < 16; regno++) \ 1105 if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 1106 offset += 4; \ 1107 if (flag_pic && current_function_uses_pic_offset_table) \ 1108 offset += 4; \ 1109 (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \ 1110 + (get_frame_size () == 0 ? 0 : 4)); \ 1111 } 1112 1113 /* Output assembler code for a block containing the constant parts 1114 of a trampoline, leaving space for the variable parts. */ 1115 1116 /* On the 68k, the trampoline looks like this: 1117 movl #STATIC,a0 1118 jmp FUNCTION 1119 1120 WARNING: Targets that may run on 68040+ cpus must arrange for 1121 the instruction cache to be flushed. Previous incarnations of 1122 the m68k trampoline code attempted to get around this by either 1123 using an out-of-line transfer function or pc-relative data, but 1124 the fact remains that the code to jump to the transfer function 1125 or the code to load the pc-relative data needs to be flushed 1126 just as much as the "variable" portion of the trampoline. 1127 Recognizing that a cache flush is going to be required anyway, 1128 dispense with such notions and build a smaller trampoline. */ 1129 1130 /* Since more instructions are required to move a template into 1131 place than to create it on the spot, don't use a template. */ 1132 1133 /* Length in units of the trampoline for entering a nested function. */ 1134 1135 #define TRAMPOLINE_SIZE 12 1136 1137 /* Alignment required for a trampoline in bits. */ 1138 1139 #define TRAMPOLINE_ALIGNMENT 16 1140 1141 /* Targets redefine this to invoke code to either flush the cache, 1142 or enable stack execution (or both). */ 1143 1144 #ifndef FINALIZE_TRAMPOLINE 1145 #define FINALIZE_TRAMPOLINE(TRAMP) 1146 #endif 1147 1148 /* Emit RTL insns to initialize the variable parts of a trampoline. 1149 FNADDR is an RTX for the address of the function's pure code. 1150 CXT is an RTX for the static chain value for the function. 1151 1152 We generate a two-instructions program at address TRAMP : 1153 movea.l &CXT,%a0 1154 jmp FNADDR */ 1155 1156 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1157 { \ 1158 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \ 1159 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \ 1160 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \ 1161 GEN_INT(0x4EF9)); \ 1162 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \ 1163 FINALIZE_TRAMPOLINE(TRAMP); \ 1164 } 1165 1166 /* This is the library routine that is used 1167 to transfer control from the trampoline 1168 to the actual nested function. 1169 It is defined for backward compatibility, 1170 for linking with object code that used the old 1171 trampoline definition. */ 1172 1173 /* A colon is used with no explicit operands 1174 to cause the template string to be scanned for %-constructs. */ 1175 /* The function name __transfer_from_trampoline is not actually used. 1176 The function definition just permits use of "asm with operands" 1177 (though the operand list is empty). */ 1178 #define TRANSFER_FROM_TRAMPOLINE \ 1179 void \ 1180 __transfer_from_trampoline () \ 1181 { \ 1182 register char *a0 asm ("%a0"); \ 1183 asm (GLOBAL_ASM_OP "___trampoline"); \ 1184 asm ("___trampoline:"); \ 1185 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ 1186 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ 1187 asm ("rts":); \ 1188 } 1189 1190 /* Addressing modes, and classification of registers for them. */ 1191 1192 #define HAVE_POST_INCREMENT 1 1193 /* #define HAVE_POST_DECREMENT 0 */ 1194 1195 #define HAVE_PRE_DECREMENT 1 1196 /* #define HAVE_PRE_INCREMENT 0 */ 1197 1198 /* Macros to check register numbers against specific register classes. */ 1199 1200 /* These assume that REGNO is a hard or pseudo reg number. 1201 They give nonzero only if REGNO is a hard reg of the suitable class 1202 or a pseudo reg currently allocated to a suitable hard reg. 1203 Since they use reg_renumber, they are safe only once reg_renumber 1204 has been allocated, which happens in local-alloc.c. */ 1205 1206 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1207 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) 1208 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1209 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) 1210 #define REGNO_OK_FOR_DATA_P(REGNO) \ 1211 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) 1212 #define REGNO_OK_FOR_FP_P(REGNO) \ 1213 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) 1214 #ifdef SUPPORT_SUN_FPA 1215 #define REGNO_OK_FOR_FPA_P(REGNO) \ 1216 (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56)) 1217 #endif 1218 1219 /* Now macros that check whether X is a register and also, 1220 strictly, whether it is in a specified class. 1221 1222 These macros are specific to the 68000, and may be used only 1223 in code for printing assembler insns and in conditions for 1224 define_optimization. */ 1225 1226 /* 1 if X is a data register. */ 1227 1228 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) 1229 1230 /* 1 if X is an fp register. */ 1231 1232 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 1233 1234 /* 1 if X is an address register */ 1235 1236 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) 1237 1238 #ifdef SUPPORT_SUN_FPA 1239 /* 1 if X is a register in the Sun FPA. */ 1240 #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X))) 1241 #else 1242 /* Answer must be no if we don't have an FPA. */ 1243 #define FPA_REG_P(X) 0 1244 #endif 1245 1246 /* Maximum number of registers that can appear in a valid memory address. */ 1247 1248 #define MAX_REGS_PER_ADDRESS 2 1249 1250 /* Recognize any constant value that is a valid address. */ 1251 1252 #define CONSTANT_ADDRESS_P(X) \ 1253 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1254 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1255 || GET_CODE (X) == HIGH) 1256 1257 /* Nonzero if the constant value X is a legitimate general operand. 1258 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1259 1260 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode) 1261 1262 /* Nonzero if the constant value X is a legitimate general operand 1263 when generating PIC code. It is given that flag_pic is on and 1264 that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1265 1266 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are 1267 accepted by insn predicates, but which would otherwise fail the 1268 `general_operand' test. */ 1269 1270 #ifndef REG_OK_STRICT 1271 #define PCREL_GENERAL_OPERAND_OK 0 1272 #else 1273 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL) 1274 #endif 1275 1276 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1277 (! symbolic_operand (X, VOIDmode) \ 1278 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \ 1279 || PCREL_GENERAL_OPERAND_OK) 1280 1281 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1282 and check its validity for a certain class. 1283 We have two alternate definitions for each of them. 1284 The usual definition accepts all pseudo regs; the other rejects 1285 them unless they have been allocated suitable hard regs. 1286 The symbol REG_OK_STRICT causes the latter definition to be used. 1287 1288 Most source files want to accept pseudo regs in the hope that 1289 they will get allocated to the class that the insn wants them to be in. 1290 Source files for reload pass need to be strict. 1291 After reload, it makes no difference, since pseudo regs have 1292 been eliminated by then. */ 1293 1294 #ifndef REG_OK_STRICT 1295 1296 /* Nonzero if X is a hard reg that can be used as an index 1297 or if it is a pseudo reg. */ 1298 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) 1299 /* Nonzero if X is a hard reg that can be used as a base reg 1300 or if it is a pseudo reg. */ 1301 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) 1302 1303 #else 1304 1305 /* Nonzero if X is a hard reg that can be used as an index. */ 1306 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1307 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1308 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1309 1310 #endif 1311 1312 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1313 that is a valid memory address for an instruction. 1314 The MODE argument is the machine mode for the MEM expression 1315 that wants to use this address. 1316 1317 When generating PIC, an address involving a SYMBOL_REF is legitimate 1318 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF. 1319 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses, 1320 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF. 1321 1322 Likewise for a LABEL_REF when generating PIC. 1323 1324 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 1325 1326 /* Allow SUBREG everywhere we allow REG. This results in better code. It 1327 also makes function inlining work when inline functions are called with 1328 arguments that are SUBREGs. */ 1329 1330 #define LEGITIMATE_BASE_REG_P(X) \ 1331 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1332 || (GET_CODE (X) == SUBREG \ 1333 && GET_CODE (SUBREG_REG (X)) == REG \ 1334 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 1335 1336 #define INDIRECTABLE_1_ADDRESS_P(X) \ 1337 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ 1338 || LEGITIMATE_BASE_REG_P (X) \ 1339 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ 1340 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ 1341 || (GET_CODE (X) == PLUS \ 1342 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ 1343 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1344 && (TARGET_68020 \ 1345 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \ 1346 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ 1347 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \ 1348 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ 1349 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) 1350 1351 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ 1352 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } 1353 1354 /* Only labels on dispatch tables are valid for indexing from. */ 1355 #define GO_IF_INDEXABLE_BASE(X, ADDR) \ 1356 { rtx temp; \ 1357 if (GET_CODE (X) == LABEL_REF \ 1358 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \ 1359 && GET_CODE (temp) == JUMP_INSN \ 1360 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \ 1361 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \ 1362 goto ADDR; \ 1363 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; } 1364 1365 #define GO_IF_INDEXING(X, ADDR) \ 1366 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ 1367 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ 1368 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ 1369 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } 1370 1371 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ 1372 { GO_IF_INDEXING (X, ADDR); \ 1373 if (GET_CODE (X) == PLUS) \ 1374 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 1375 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \ 1376 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ 1377 if (GET_CODE (XEXP (X, 0)) == CONST_INT \ 1378 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \ 1379 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } 1380 1381 /* coldfire/5200 does not allow HImode index registers. */ 1382 #define LEGITIMATE_INDEX_REG_P(X) \ 1383 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 1384 || (! TARGET_5200 \ 1385 && GET_CODE (X) == SIGN_EXTEND \ 1386 && GET_CODE (XEXP (X, 0)) == REG \ 1387 && GET_MODE (XEXP (X, 0)) == HImode \ 1388 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ 1389 || (GET_CODE (X) == SUBREG \ 1390 && GET_CODE (SUBREG_REG (X)) == REG \ 1391 && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 1392 1393 #define LEGITIMATE_INDEX_P(X) \ 1394 (LEGITIMATE_INDEX_REG_P (X) \ 1395 || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \ 1396 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ 1397 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1398 && (INTVAL (XEXP (X, 1)) == 2 \ 1399 || INTVAL (XEXP (X, 1)) == 4 \ 1400 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200)))) 1401 1402 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ 1403 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1404 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ 1405 GO_IF_INDEXED_ADDRESS (X, ADDR); \ 1406 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ 1407 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ 1408 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ 1409 goto ADDR; } 1410 1411 /* Don't call memory_address_noforce for the address to fetch 1412 the switch offset. This address is ok as it stands (see above), 1413 but memory_address_noforce would alter it. */ 1414 #define PIC_CASE_VECTOR_ADDRESS(index) index 1415 1416 /* Try machine-dependent ways of modifying an illegitimate address 1417 to be legitimate. If we find one, return the new, valid address. 1418 This macro is used in only one place: `memory_address' in explow.c. 1419 1420 OLDX is the address as it was before break_out_memory_refs was called. 1421 In some cases it is useful to look at this to decide what needs to be done. 1422 1423 MODE and WIN are passed so that this macro can use 1424 GO_IF_LEGITIMATE_ADDRESS. 1425 1426 It is always safe for this macro to do nothing. It exists to recognize 1427 opportunities to optimize the output. 1428 1429 For the 68000, we handle X+REG by loading X into a register R and 1430 using R+REG. R will go in an address reg and indexing will be used. 1431 However, if REG is a broken-out memory address or multiplication, 1432 nothing needs to be done because REG can certainly go in an address reg. */ 1433 1434 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } 1435 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1436 { register int ch = (X) != (OLDX); \ 1437 if (GET_CODE (X) == PLUS) \ 1438 { int copied = 0; \ 1439 if (GET_CODE (XEXP (X, 0)) == MULT) \ 1440 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \ 1441 if (GET_CODE (XEXP (X, 1)) == MULT) \ 1442 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ 1443 if (ch && GET_CODE (XEXP (X, 1)) == REG \ 1444 && GET_CODE (XEXP (X, 0)) == REG) \ 1445 goto WIN; \ 1446 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ 1447 if (GET_CODE (XEXP (X, 0)) == REG \ 1448 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ 1449 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ 1450 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ 1451 { register rtx temp = gen_reg_rtx (Pmode); \ 1452 register rtx val = force_operand (XEXP (X, 1), 0); \ 1453 emit_move_insn (temp, val); \ 1454 COPY_ONCE (X); \ 1455 XEXP (X, 1) = temp; \ 1456 goto WIN; } \ 1457 else if (GET_CODE (XEXP (X, 1)) == REG \ 1458 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ 1459 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ 1460 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ 1461 { register rtx temp = gen_reg_rtx (Pmode); \ 1462 register rtx val = force_operand (XEXP (X, 0), 0); \ 1463 emit_move_insn (temp, val); \ 1464 COPY_ONCE (X); \ 1465 XEXP (X, 0) = temp; \ 1466 goto WIN; }}} 1467 1468 /* Go to LABEL if ADDR (a legitimate address expression) 1469 has an effect that depends on the machine mode it is used for. 1470 On the 68000, only predecrement and postincrement address depend thus 1471 (the amount of decrement or increment being the length of the operand). */ 1472 1473 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1474 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL 1475 1476 /* Specify the machine mode that this machine uses 1477 for the index in the tablejump instruction. */ 1478 #define CASE_VECTOR_MODE HImode 1479 1480 /* Define as C expression which evaluates to nonzero if the tablejump 1481 instruction expects the table to contain offsets from the address of the 1482 table. 1483 Do not define this if the table should contain absolute addresses. */ 1484 #define CASE_VECTOR_PC_RELATIVE 1 1485 1486 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1487 #define DEFAULT_SIGNED_CHAR 1 1488 1489 /* Don't cse the address of the function being compiled. */ 1490 #define NO_RECURSIVE_FUNCTION_CSE 1491 1492 /* Max number of bytes we can move from memory to memory 1493 in one reasonably fast instruction. */ 1494 #define MOVE_MAX 4 1495 1496 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1497 #define SLOW_BYTE_ACCESS 0 1498 1499 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1500 is done just by pretending it is already truncated. */ 1501 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1502 1503 /* We assume that the store-condition-codes instructions store 0 for false 1504 and some other value for true. This is the value stored for true. */ 1505 1506 #define STORE_FLAG_VALUE (-1) 1507 1508 /* When a prototype says `char' or `short', really pass an `int'. */ 1509 #define PROMOTE_PROTOTYPES 1 1510 1511 /* Specify the machine mode that pointers have. 1512 After generation of rtl, the compiler makes no further distinction 1513 between pointers and any other objects of this machine mode. */ 1514 #define Pmode SImode 1515 1516 /* A function address in a call instruction 1517 is a byte address (for indexing purposes) 1518 so give the MEM rtx a byte's mode. */ 1519 #define FUNCTION_MODE QImode 1520 1521 /* Compute the cost of computing a constant rtl expression RTX 1522 whose rtx-code is CODE. The body of this macro is a portion 1523 of a switch statement. If the code is computed here, 1524 return it with a return statement. Otherwise, break from the switch. */ 1525 1526 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ 1527 case CONST_INT: \ 1528 /* Constant zero is super cheap due to clr instruction. */ \ 1529 if (RTX == const0_rtx) return 0; \ 1530 /* if ((OUTER_CODE) == SET) */ \ 1531 return const_int_cost(RTX); \ 1532 case CONST: \ 1533 case LABEL_REF: \ 1534 case SYMBOL_REF: \ 1535 return 3; \ 1536 case CONST_DOUBLE: \ 1537 /* Make 0.0 cheaper than other floating constants to \ 1538 encourage creating tstsf and tstdf insns. */ \ 1539 if ((OUTER_CODE) == COMPARE \ 1540 && ((RTX) == CONST0_RTX (SFmode) \ 1541 || (RTX) == CONST0_RTX (DFmode))) \ 1542 return 4; \ 1543 return 5; 1544 1545 /* Compute the cost of various arithmetic operations. 1546 These are vaguely right for a 68020. */ 1547 /* The costs for long multiply have been adjusted to 1548 work properly in synth_mult on the 68020, 1549 relative to an average of the time for add and the time for shift, 1550 taking away a little more because sometimes move insns are needed. */ 1551 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */ 1552 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13) 1553 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5) 1554 #define DIVW_COST (TARGET_68020 ? 27 : 12) 1555 1556 #define RTX_COSTS(X,CODE,OUTER_CODE) \ 1557 case PLUS: \ 1558 /* An lea costs about three times as much as a simple add. */ \ 1559 if (GET_MODE (X) == SImode \ 1560 && GET_CODE (XEXP (X, 1)) == REG \ 1561 && GET_CODE (XEXP (X, 0)) == MULT \ 1562 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ 1563 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ 1564 && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \ 1565 || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \ 1566 || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \ 1567 return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \ 1568 break; \ 1569 case ASHIFT: \ 1570 case ASHIFTRT: \ 1571 case LSHIFTRT: \ 1572 if (TARGET_68060) \ 1573 return COSTS_N_INSNS(1); \ 1574 if (! TARGET_68020) \ 1575 { \ 1576 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1577 { \ 1578 if (INTVAL (XEXP (X, 1)) < 16) \ 1579 return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \ 1580 else \ 1581 /* We're using clrw + swap for these cases. */ \ 1582 return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \ 1583 } \ 1584 return COSTS_N_INSNS (10); /* worst case */ \ 1585 } \ 1586 /* A shift by a big integer takes an extra instruction. */ \ 1587 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 1588 && (INTVAL (XEXP (X, 1)) == 16)) \ 1589 return COSTS_N_INSNS (2); /* clrw;swap */ \ 1590 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 1591 && !(INTVAL (XEXP (X, 1)) > 0 \ 1592 && INTVAL (XEXP (X, 1)) <= 8)) \ 1593 return COSTS_N_INSNS (3); /* lsr #i,dn */ \ 1594 break; \ 1595 case MULT: \ 1596 if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \ 1597 || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \ 1598 && GET_MODE (X) == SImode) \ 1599 return COSTS_N_INSNS (MULW_COST); \ 1600 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ 1601 return COSTS_N_INSNS (MULW_COST); \ 1602 else \ 1603 return COSTS_N_INSNS (MULL_COST); \ 1604 case DIV: \ 1605 case UDIV: \ 1606 case MOD: \ 1607 case UMOD: \ 1608 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ 1609 return COSTS_N_INSNS (DIVW_COST); /* div.w */ \ 1610 return COSTS_N_INSNS (43); /* div.l */ 1611 1612 /* Tell final.c how to eliminate redundant test instructions. */ 1613 1614 /* Here we define machine-dependent flags and fields in cc_status 1615 (see `conditions.h'). */ 1616 1617 /* Set if the cc value is actually in the 68881, so a floating point 1618 conditional branch must be output. */ 1619 #define CC_IN_68881 04000 1620 1621 /* Store in cc_status the expressions that the condition codes will 1622 describe after execution of an instruction whose pattern is EXP. 1623 Do not alter them if the instruction would not alter the cc's. */ 1624 1625 /* On the 68000, all the insns to store in an address register fail to 1626 set the cc's. However, in some cases these instructions can make it 1627 possibly invalid to use the saved cc's. In those cases we clear out 1628 some or all of the saved cc's so they won't be used. */ 1629 1630 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) 1631 1632 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ 1633 { if (cc_prev_status.flags & CC_IN_68881) \ 1634 return FLOAT; \ 1635 if (cc_prev_status.flags & CC_NO_OVERFLOW) \ 1636 return NO_OV; \ 1637 return NORMAL; } 1638 1639 /* Control the assembler format that we output. */ 1640 1641 /* Output at beginning of assembler file. */ 1642 1643 #define ASM_FILE_START(FILE) \ 1644 fprintf (FILE, "#NO_APP\n"); 1645 1646 /* Output to assembler file text saying following lines 1647 may contain character constants, extra white space, comments, etc. */ 1648 1649 #define ASM_APP_ON "#APP\n" 1650 1651 /* Output to assembler file text saying following lines 1652 no longer contain unusual constructs. */ 1653 1654 #define ASM_APP_OFF "#NO_APP\n" 1655 1656 /* Output before read-only data. */ 1657 1658 #define TEXT_SECTION_ASM_OP "\t.text" 1659 1660 /* Output before writable data. */ 1661 1662 #define DATA_SECTION_ASM_OP "\t.data" 1663 1664 #define GLOBAL_ASM_OP "\t.globl\t" 1665 1666 /* Here are four prefixes that are used by asm_fprintf to 1667 facilitate customization for alternate assembler syntaxes. 1668 Machines with no likelihood of an alternate syntax need not 1669 define these and need not use asm_fprintf. */ 1670 1671 /* The prefix for register names. Note that REGISTER_NAMES 1672 is supposed to include this prefix. */ 1673 1674 #define REGISTER_PREFIX "" 1675 1676 /* The prefix for local labels. You should be able to define this as 1677 an empty string, or any arbitrary string (such as ".", ".L%", etc) 1678 without having to make any other changes to account for the specific 1679 definition. Note it is a string literal, not interpreted by printf 1680 and friends. */ 1681 1682 #define LOCAL_LABEL_PREFIX "" 1683 1684 /* The prefix to add to user-visible assembler symbols. */ 1685 1686 #define USER_LABEL_PREFIX "_" 1687 1688 /* The prefix for immediate operands. */ 1689 1690 #define IMMEDIATE_PREFIX "#" 1691 1692 /* How to refer to registers in assembler output. 1693 This sequence is indexed by compiler's hard-register-number (see above). */ 1694 1695 #ifndef SUPPORT_SUN_FPA 1696 1697 #define REGISTER_NAMES \ 1698 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ 1699 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ 1700 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" } 1701 1702 #else /* SUPPORTED_SUN_FPA */ 1703 1704 #define REGISTER_NAMES \ 1705 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ 1706 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ 1707 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \ 1708 "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \ 1709 "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \ 1710 "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \ 1711 "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" } 1712 1713 #endif /* defined SUPPORT_SUN_FPA */ 1714 1715 /* How to renumber registers for dbx and gdb. 1716 On the Sun-3, the floating point registers have numbers 1717 18 to 25, not 16 to 23 as they do in the compiler. */ 1718 1719 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) 1720 1721 /* Before the prologue, RA is at 0(%sp). */ 1722 #define INCOMING_RETURN_ADDR_RTX \ 1723 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 1724 1725 /* We must not use the DBX register numbers for the DWARF 2 CFA column 1726 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. 1727 Instead use the identity mapping. */ 1728 #define DWARF_FRAME_REGNUM(REG) REG 1729 1730 /* Before the prologue, the top of the frame is at 4(%sp). */ 1731 #define INCOMING_FRAME_SP_OFFSET 4 1732 1733 /* Describe how we implement __builtin_eh_return. */ 1734 #define EH_RETURN_DATA_REGNO(N) \ 1735 ((N) < 2 ? (N) : INVALID_REGNUM) 1736 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8) 1737 #define EH_RETURN_HANDLER_RTX \ 1738 gen_rtx_MEM (Pmode, \ 1739 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \ 1740 plus_constant (EH_RETURN_STACKADJ_RTX, \ 1741 UNITS_PER_WORD))) 1742 1743 /* Select a format to encode pointers in exception handling data. CODE 1744 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1745 true if the symbol may be affected by dynamic relocations. */ 1746 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1747 (flag_pic \ 1748 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 1749 : DW_EH_PE_absptr) 1750 1751 /* This is how to output a reference to a user-level label named NAME. 1752 `assemble_name' uses this. */ 1753 1754 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1755 asm_fprintf (FILE, "%0U%s", NAME) 1756 1757 /* This is how to output an internal numbered label where 1758 PREFIX is the class of label and NUM is the number within the class. */ 1759 1760 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 1761 asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM) 1762 1763 /* This is how to store into the string LABEL 1764 the symbol_ref name of an internal numbered label where 1765 PREFIX is the class of label and NUM is the number within the class. 1766 This is suitable for output with `assemble_name'. */ 1767 1768 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1769 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) 1770 1771 /* This is how to output an insn to push a register on the stack. 1772 It need not be very fast code. */ 1773 1774 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 1775 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) 1776 1777 /* This is how to output an insn to pop a register from the stack. 1778 It need not be very fast code. */ 1779 1780 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 1781 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) 1782 1783 /* This is how to output an element of a case-vector that is absolute. 1784 (The 68000 does not use such vectors, 1785 but we must define this macro anyway.) */ 1786 1787 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1788 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) 1789 1790 /* This is how to output an element of a case-vector that is relative. */ 1791 1792 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1793 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) 1794 1795 /* This is how to output an assembler line 1796 that says to advance the location counter 1797 to a multiple of 2**LOG bytes. */ 1798 1799 /* We don't have a way to align to more than a two-byte boundary, so do the 1800 best we can and don't complain. */ 1801 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1802 if ((LOG) >= 1) \ 1803 fprintf (FILE, "\t.even\n"); 1804 1805 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1806 fprintf (FILE, "\t.skip %u\n", (SIZE)) 1807 1808 /* This says how to output an assembler line 1809 to define a global common symbol. */ 1810 1811 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1812 ( fputs (".comm ", (FILE)), \ 1813 assemble_name ((FILE), (NAME)), \ 1814 fprintf ((FILE), ",%u\n", (ROUNDED))) 1815 1816 /* This says how to output an assembler line 1817 to define a local common symbol. */ 1818 1819 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1820 ( fputs (".lcomm ", (FILE)), \ 1821 assemble_name ((FILE), (NAME)), \ 1822 fprintf ((FILE), ",%u\n", (ROUNDED))) 1823 1824 /* Store in OUTPUT a string (made with alloca) containing 1825 an assembler-name for a local static variable named NAME. 1826 LABELNO is an integer which is different for each call. */ 1827 1828 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 1829 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 1830 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 1831 1832 /* Output a float value (represented as a C double) as an immediate operand. 1833 This macro is a 68k-specific macro. */ 1834 1835 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ 1836 do { \ 1837 if (CODE == 'f') \ 1838 { \ 1839 char dstr[30]; \ 1840 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \ 1841 asm_fprintf ((FILE), "%I0r%s", dstr); \ 1842 } \ 1843 else \ 1844 { \ 1845 long l; \ 1846 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ 1847 asm_fprintf ((FILE), "%I0x%lx", l); \ 1848 } \ 1849 } while (0) 1850 1851 /* Output a double value (represented as a C double) as an immediate operand. 1852 This macro is a 68k-specific macro. */ 1853 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ 1854 do { char dstr[30]; \ 1855 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ 1856 asm_fprintf (FILE, "%I0r%s", dstr); \ 1857 } while (0) 1858 1859 /* Note, long double immediate operands are not actually 1860 generated by m68k.md. */ 1861 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ 1862 do { char dstr[30]; \ 1863 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ 1864 asm_fprintf (FILE, "%I0r%s", dstr); \ 1865 } while (0) 1866 1867 /* Print operand X (an rtx) in assembler syntax to file FILE. 1868 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1869 For `%' followed by punctuation, CODE is the punctuation and X is null. 1870 1871 On the 68000, we use several CODE characters: 1872 '.' for dot needed in Motorola-style opcode names. 1873 '-' for an operand pushing on the stack: 1874 sp@-, -(sp) or -(%sp) depending on the style of syntax. 1875 '+' for an operand pushing on the stack: 1876 sp@+, (sp)+ or (%sp)+ depending on the style of syntax. 1877 '@' for a reference to the top word on the stack: 1878 sp@, (sp) or (%sp) depending on the style of syntax. 1879 '#' for an immediate operand prefix (# in MIT and Motorola syntax 1880 but & in SGS syntax). 1881 '!' for the fpcr register (used in some float-to-fixed conversions). 1882 '$' for the letter `s' in an op code, but only on the 68040. 1883 '&' for the letter `d' in an op code, but only on the 68040. 1884 '/' for register prefix needed by longlong.h. 1885 1886 'b' for byte insn (no effect, on the Sun; this is for the ISI). 1887 'd' to force memory addressing to be absolute, not relative. 1888 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 1889 'o' for operands to go directly to output_operand_address (bypassing 1890 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL) 1891 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather 1892 than directly). Second part of 'y' below. 1893 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), 1894 or print pair of registers as rx:ry. 1895 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs 1896 CONST_DOUBLE's as SunFPA constant RAM registers if 1897 possible, so it should not be used except for the SunFPA. */ 1898 1899 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1900 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ 1901 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ 1902 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/') 1903 1904 /* A C compound statement to output to stdio stream STREAM the 1905 assembler syntax for an instruction operand X. X is an RTL 1906 expression. 1907 1908 CODE is a value that can be used to specify one of several ways 1909 of printing the operand. It is used when identical operands 1910 must be printed differently depending on the context. CODE 1911 comes from the `%' specification that was used to request 1912 printing of the operand. If the specification was just `%DIGIT' 1913 then CODE is 0; if the specification was `%LTR DIGIT' then CODE 1914 is the ASCII code for LTR. 1915 1916 If X is a register, this macro should print the register's name. 1917 The names can be found in an array `reg_names' whose type is 1918 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. 1919 1920 When the machine description has a specification `%PUNCT' (a `%' 1921 followed by a punctuation character), this macro is called with 1922 a null pointer for X and the punctuation character for CODE. 1923 1924 See m68k.c for the m68k specific codes. */ 1925 1926 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 1927 1928 /* A C compound statement to output to stdio stream STREAM the 1929 assembler syntax for an instruction operand that is a memory 1930 reference whose address is ADDR. ADDR is an RTL expression. */ 1931 1932 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 1933 1934 /* Variables in m68k.c */ 1935 extern const char *m68k_align_loops_string; 1936 extern const char *m68k_align_jumps_string; 1937 extern const char *m68k_align_funcs_string; 1938 extern int m68k_align_loops; 1939 extern int m68k_align_jumps; 1940 extern int m68k_align_funcs; 1941 extern int m68k_last_compare_had_fp_operands; 1942 1943 1944 /* Define the codes that are matched by predicates in m68k.c. */ 1945 1946 #define PREDICATE_CODES \ 1947 {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 1948 LABEL_REF, SUBREG, REG, MEM}}, \ 1949 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \ 1950 {"memory_src_operand", {SUBREG, MEM}}, \ 1951 {"not_sp_operand", {SUBREG, REG, MEM}}, \ 1952 {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \ 1953 {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \ 1954 {"const_sint32_operand", {CONST_INT}}, \ 1955 {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \ 1956 GT, LT, GE, LE}}, \ 1957 {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}}, 1958 1959 /* 1960 Local variables: 1961 version-control: t 1962 End: 1963 */ 1964