1 /* $OpenBSD: pci_1000a.c,v 1.14 2017/09/08 05:36:51 deraadt Exp $ */
2 /* $NetBSD: pci_1000a.c,v 1.14 2001/07/27 00:25:20 thorpej Exp $ */
3
4 /*
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at
9 * Carnegie-Mellon University. Platform support for Noritake, Pintake, and
10 * Corelle by Ross Harvey with copyright assignment by permission of Avalon
11 * Computer Systems, Inc.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 /*
36 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
37 * All rights reserved.
38 *
39 * Author: Chris G. Demetriou
40 *
41 * Permission to use, copy, modify and distribute this software and
42 * its documentation is hereby granted, provided that both the copyright
43 * notice and this permission notice appear in all copies of the
44 * software, derivative works or modified versions, and any portions
45 * thereof, and that both notices appear in supporting documentation.
46 *
47 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
48 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
49 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
50 *
51 * Carnegie Mellon requests users of this software to return to
52 *
53 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
54 * School of Computer Science
55 * Carnegie Mellon University
56 * Pittsburgh PA 15213-3890
57 *
58 * any improvements or extensions that they make and grant Carnegie the
59 * rights to redistribute these changes.
60 */
61
62 #include <sys/param.h>
63 #include <sys/time.h>
64 #include <sys/systm.h>
65 #include <sys/errno.h>
66 #include <sys/malloc.h>
67 #include <sys/device.h>
68
69 #include <uvm/uvm_extern.h>
70
71 #include <machine/autoconf.h>
72
73 #include <dev/pci/pcireg.h>
74 #include <dev/pci/pcivar.h>
75 #include <dev/pci/ppbreg.h>
76
77 #include <alpha/pci/pci_1000a.h>
78
79 #include "sio.h"
80 #if NSIO > 0 || NPCEB > 0
81 #include <alpha/pci/siovar.h>
82 #endif
83
84 #define PCI_NIRQ 32
85 #define PCI_STRAY_MAX 5
86
87 #define IMR2IRQ(bn) ((bn) - 1)
88 #define IRQ2IMR(irq) ((irq) + 1)
89
90 static bus_space_tag_t mystery_icu_iot;
91 static bus_space_handle_t mystery_icu_ioh[2];
92
93 int dec_1000a_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
94 const char *dec_1000a_intr_string(void *, pci_intr_handle_t);
95 int dec_1000a_intr_line(void *, pci_intr_handle_t);
96 void *dec_1000a_intr_establish(void *, pci_intr_handle_t,
97 int, int (*func)(void *), void *, const char *);
98 void dec_1000a_intr_disestablish(void *, void *);
99
100 struct alpha_shared_intr *dec_1000a_pci_intr;
101
102 void dec_1000a_iointr(void *arg, unsigned long vec);
103 void dec_1000a_enable_intr(int irq);
104 void dec_1000a_disable_intr(int irq);
105 void pci_1000a_imi(void);
106
107 void
pci_1000a_pickintr(core,iot,memt,pc)108 pci_1000a_pickintr(core, iot, memt, pc)
109 void *core;
110 bus_space_tag_t iot, memt;
111 pci_chipset_tag_t pc;
112 {
113 int i;
114
115 mystery_icu_iot = iot;
116
117 if (bus_space_map(iot, 0x54a, 2, 0, mystery_icu_ioh + 0)
118 || bus_space_map(iot, 0x54c, 2, 0, mystery_icu_ioh + 1))
119 panic("pci_1000a_pickintr");
120 pc->pc_intr_v = core;
121 pc->pc_intr_map = dec_1000a_intr_map;
122 pc->pc_intr_string = dec_1000a_intr_string;
123 pc->pc_intr_line = dec_1000a_intr_line;
124 pc->pc_intr_establish = dec_1000a_intr_establish;
125 pc->pc_intr_disestablish = dec_1000a_intr_disestablish;
126
127 pc->pc_pciide_compat_intr_establish = NULL;
128 pc->pc_pciide_compat_intr_disestablish = NULL;
129
130 dec_1000a_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ);
131 for (i = 0; i < PCI_NIRQ; i++) {
132 alpha_shared_intr_set_maxstrays(dec_1000a_pci_intr, i,
133 PCI_STRAY_MAX);
134 }
135
136 pci_1000a_imi();
137 #if NSIO > 0 || NPCEB > 0
138 sio_intr_setup(pc, iot);
139 #endif
140 }
141
142 int
dec_1000a_intr_map(pa,ihp)143 dec_1000a_intr_map(pa, ihp)
144 struct pci_attach_args *pa;
145 pci_intr_handle_t *ihp;
146 {
147 pcitag_t bustag = pa->pa_intrtag;
148 int buspin, line = pa->pa_intrline;
149 int imrbit = 0, bus, device;
150 /*
151 * Get bit number in mystery ICU imr
152 */
153 static const signed char imrmap[][4] = {
154 # define IRQSPLIT(o) { (o), (o)+1, (o)+16, (o)+16+1 }
155 # define IRQNONE { 0, 0, 0, 0 }
156 /* 0 */ { 1, 0, 0, 0 }, /* Noritake and Pintake */
157 /* 1 */ IRQSPLIT(8),
158 /* 2 */ IRQSPLIT(10),
159 /* 3 */ IRQSPLIT(12),
160 /* 4 */ IRQSPLIT(14),
161 /* 5 */ { 1, 0, 0, 0 }, /* Corelle */
162 /* 6 */ { 10, 0, 0, 0 }, /* Corelle */
163 /* 7 */ IRQNONE,
164 /* 8 */ IRQNONE, /* see imrmap2[] below */
165 /* 9 */ IRQNONE,
166 /* 10 */ IRQNONE,
167 /* 11 */ IRQSPLIT(2),
168 /* 12 */ IRQSPLIT(4),
169 /* 13 */ IRQSPLIT(6),
170 /* 14 */ IRQSPLIT(8) /* Corelle */
171 }, imrmap2[][4] = {
172 /* 0 */ { 1, 0, 0, 0 }, /* isp */
173 /* 1 */ IRQSPLIT(8),
174 /* 2 */ IRQSPLIT(10),
175 /* 3 */ IRQSPLIT(12),
176 /* 4 */ IRQSPLIT(14)
177 };
178
179 /*
180 * The console places the interrupt mapping in the "line" value.
181 * We trust it whenever possible.
182 */
183 if (line >= 0 && line < PCI_NIRQ) {
184 imrbit = line + 1;
185 } else {
186 if (pa->pa_bridgetag) {
187 buspin = pa->pa_rawintrpin;
188 bus = pa->pa_bus;
189 device = pa->pa_device;
190
191 if (bus == 2) {
192 /*
193 * Devices behind ppb1 (pci bus #2).
194 * Those use fixed per-slot assignments.
195 */
196 if (0 <= device && device <
197 sizeof imrmap2 / sizeof imrmap2[0]) {
198 imrbit = imrmap2[device][buspin - 1];
199 }
200 } else {
201 /*
202 * Devices behind further ppb.
203 * Those reuse ppb configured interrupts.
204 */
205 buspin = PPB_INTERRUPT_SWIZZLE(buspin, device);
206 if (pa->pa_bridgeih[buspin - 1] != 0) {
207 imrbit =
208 IRQ2IMR(pa->pa_bridgeih[buspin - 1]);
209 }
210 }
211 } else {
212 pci_decompose_tag(pa->pa_pc, bustag, &bus, &device,
213 NULL);
214 buspin = pa->pa_intrpin;
215 if (0 <= device &&
216 device < sizeof imrmap / sizeof imrmap[0])
217 imrbit = imrmap[device][buspin - 1];
218 }
219 }
220
221 if (imrbit) {
222 *ihp = IMR2IRQ(imrbit);
223 return 0;
224 }
225
226 return 1;
227 }
228
229 const char *
dec_1000a_intr_string(ccv,ih)230 dec_1000a_intr_string(ccv, ih)
231 void *ccv;
232 pci_intr_handle_t ih;
233 {
234 static const char irqmsg_fmt[] = "dec_1000a irq %ld";
235 static char irqstr[sizeof irqmsg_fmt];
236
237
238 if (ih >= PCI_NIRQ)
239 panic("dec_1000a_intr_string: bogus dec_1000a IRQ 0x%lx", ih);
240
241 snprintf(irqstr, sizeof irqstr, irqmsg_fmt, ih);
242 return (irqstr);
243 }
244
245 int
dec_1000a_intr_line(ccv,ih)246 dec_1000a_intr_line(ccv, ih)
247 void *ccv;
248 pci_intr_handle_t ih;
249 {
250 #if NSIO > 0
251 return sio_intr_line(NULL /*XXX*/, ih);
252 #else
253 return (ih);
254 #endif
255 }
256
257 void *
dec_1000a_intr_establish(ccv,ih,level,func,arg,name)258 dec_1000a_intr_establish(ccv, ih, level, func, arg, name)
259 void *ccv;
260 pci_intr_handle_t ih;
261 int level;
262 int (*func)(void *);
263 void *arg;
264 const char *name;
265 {
266 void *cookie;
267
268 if (ih >= PCI_NIRQ)
269 panic("dec_1000a_intr_establish: IRQ too high, 0x%lx", ih);
270
271 cookie = alpha_shared_intr_establish(dec_1000a_pci_intr, ih, IST_LEVEL,
272 level, func, arg, name);
273
274 if (cookie != NULL &&
275 alpha_shared_intr_firstactive(dec_1000a_pci_intr, ih)) {
276 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_1000a_iointr, NULL);
277 dec_1000a_enable_intr(ih);
278
279 }
280 return (cookie);
281 }
282
283 void
dec_1000a_intr_disestablish(ccv,cookie)284 dec_1000a_intr_disestablish(ccv, cookie)
285 void *ccv, *cookie;
286 {
287 struct alpha_shared_intrhand *ih = cookie;
288 unsigned int irq = ih->ih_num;
289 int s;
290
291 s = splhigh();
292
293 alpha_shared_intr_disestablish(dec_1000a_pci_intr, cookie);
294 if (alpha_shared_intr_isactive(dec_1000a_pci_intr, irq) == 0) {
295 dec_1000a_disable_intr(irq);
296 alpha_shared_intr_set_dfltsharetype(dec_1000a_pci_intr, irq,
297 IST_NONE);
298 scb_free(0x900 + SCB_IDXTOVEC(irq));
299 }
300
301 splx(s);
302 }
303
304 void
dec_1000a_iointr(framep,vec)305 dec_1000a_iointr(framep, vec)
306 void *framep;
307 unsigned long vec;
308 {
309 int irq;
310
311 irq = SCB_VECTOIDX(vec - 0x900);
312
313 if (!alpha_shared_intr_dispatch(dec_1000a_pci_intr, irq)) {
314 alpha_shared_intr_stray(dec_1000a_pci_intr, irq,
315 "dec_1000a irq");
316 if (ALPHA_SHARED_INTR_DISABLE(dec_1000a_pci_intr, irq))
317 dec_1000a_disable_intr(irq);
318 } else
319 alpha_shared_intr_reset_strays(dec_1000a_pci_intr, irq);
320 }
321
322 /*
323 * Read and write the mystery ICU IMR registers
324 */
325
326 #define IR(h) bus_space_read_2(mystery_icu_iot, mystery_icu_ioh[h], 0)
327 #define IW(h, v) bus_space_write_2(mystery_icu_iot, mystery_icu_ioh[h], 0, (v))
328
329 /*
330 * Enable and disable interrupts at the ICU level
331 */
332
333 void
dec_1000a_enable_intr(irq)334 dec_1000a_enable_intr(irq)
335 int irq;
336 {
337 int imrval = IRQ2IMR(irq);
338 int i = imrval >= 16;
339
340 IW(i, IR(i) | 1 << (imrval & 0xf));
341 }
342
343 void
dec_1000a_disable_intr(irq)344 dec_1000a_disable_intr(irq)
345 int irq;
346 {
347 int imrval = IRQ2IMR(irq);
348 int i = imrval >= 16;
349
350 IW(i, IR(i) & ~(1 << (imrval & 0xf)));
351 }
352 /*
353 * Initialize mystery ICU
354 */
355 void
pci_1000a_imi()356 pci_1000a_imi()
357 {
358 IW(0, IR(0) & 1);
359 IW(1, IR(0) & 3);
360 }
361