1/*	$OpenBSD: bus_space_asm_generic.S,v 1.5 2017/01/06 00:06:02 jsg Exp $	*/
2/*	$NetBSD: bus_space_asm_generic.S,v 1.3 2003/03/27 19:46:14 mycroft Exp $	*/
3
4/*
5 * Copyright (c) 1997 Causality Limited.
6 * Copyright (c) 1997 Mark Brinicombe.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *	This product includes software developed by Mark Brinicombe
20 *	for the NetBSD Project.
21 * 4. The name of the company nor the name of the author may be used to
22 *    endorse or promote products derived from this software without specific
23 *    prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 */
37
38#include <arm/asm.h>
39#include <arm/cpuconf.h>
40
41/*
42 * Generic bus_space functions.
43 */
44
45/*
46 * read single
47 */
48
49ENTRY(generic_bs_r_1)
50	ldrb	r0, [r1, r2]
51	mov	pc, lr
52
53ENTRY(generic_armv4_bs_r_2)
54	ldrh	r0, [r1, r2]
55	mov	pc, lr
56
57ENTRY(generic_bs_r_4)
58	ldr	r0, [r1, r2]
59	mov	pc, lr
60
61/*
62 * write single
63 */
64
65ENTRY(generic_bs_w_1)
66	strb	r3, [r1, r2]
67	mov	pc, lr
68
69ENTRY(generic_armv4_bs_w_2)
70	strh	r3, [r1, r2]
71	mov	pc, lr
72
73ENTRY(generic_bs_w_4)
74	str	r3, [r1, r2]
75	mov	pc, lr
76
77/*
78 * read multiple
79 */
80
81ENTRY(generic_bs_rm_1)
82	add	r0, r1, r2
83	mov	r1, r3
84	ldr	r2, [sp, #0]
85	teq	r2, #0
86	moveq	pc, lr
87
881:	ldrb	r3, [r0]
89	strb	r3, [r1], #1
90	subs	r2, r2, #1
91	bne	1b
92
93	mov	pc, lr
94
95ENTRY(generic_armv4_bs_rm_2)
96	add	r0, r1, r2
97	mov	r1, r3
98	ldr	r2, [sp, #0]
99	teq	r2, #0
100	moveq	pc, lr
101
1021:	ldrh	r3, [r0]
103	strh	r3, [r1], #2
104	subs	r2, r2, #1
105	bne	1b
106
107	mov	pc, lr
108
109ENTRY(generic_bs_rm_4)
110	add	r0, r1, r2
111	mov	r1, r3
112	ldr	r2, [sp, #0]
113	teq	r2, #0
114	moveq	pc, lr
115
1161:	ldr	r3, [r0]
117	str	r3, [r1], #4
118	subs	r2, r2, #1
119	bne	1b
120
121	mov	pc, lr
122
123/*
124 * write multiple
125 */
126
127ENTRY(generic_bs_wm_1)
128	add	r0, r1, r2
129	mov	r1, r3
130	ldr	r2, [sp, #0]
131	teq	r2, #0
132	moveq	pc, lr
133
1341:	ldrb	r3, [r1], #1
135	strb	r3, [r0]
136	subs	r2, r2, #1
137	bne	1b
138
139	mov	pc, lr
140
141ENTRY(generic_armv4_bs_wm_2)
142	add	r0, r1, r2
143	mov	r1, r3
144	ldr	r2, [sp, #0]
145	teq	r2, #0
146	moveq	pc, lr
147
1481:	ldrh	r3, [r1], #2
149	strh	r3, [r0]
150	subs	r2, r2, #1
151	bne	1b
152
153	mov	pc, lr
154
155ENTRY(generic_bs_wm_4)
156	add	r0, r1, r2
157	mov	r1, r3
158	ldr	r2, [sp, #0]
159	teq	r2, #0
160	moveq	pc, lr
161
1621:	ldr	r3, [r1], #4
163	str	r3, [r0]
164	subs	r2, r2, #1
165	bne	1b
166
167	mov	pc, lr
168
169/*
170 * read region
171 */
172
173ENTRY(generic_bs_rr_1)
174	add	r0, r1, r2
175	mov	r1, r3
176	ldr	r2, [sp, #0]
177	teq	r2, #0
178	moveq	pc, lr
179
1801:	ldrb	r3, [r0], #1
181	strb	r3, [r1], #1
182	subs	r2, r2, #1
183	bne	1b
184
185	mov	pc, lr
186
187ENTRY(generic_armv4_bs_rr_2)
188	add	r0, r1, r2
189	mov	r1, r3
190	ldr	r2, [sp, #0]
191	teq	r2, #0
192	moveq	pc, lr
193
1941:	ldrh	r3, [r0], #2
195	strh	r3, [r1], #2
196	subs	r2, r2, #1
197	bne	1b
198
199	mov	pc, lr
200
201ENTRY(generic_bs_rr_4)
202	add	r0, r1, r2
203	mov	r1, r3
204	ldr	r2, [sp, #0]
205	teq	r2, #0
206	moveq	pc, lr
207
2081:	ldr	r3, [r0], #4
209	str	r3, [r1], #4
210	subs	r2, r2, #1
211	bne	1b
212
213	mov	pc, lr
214
215/*
216 * write region.
217 */
218
219ENTRY(generic_bs_wr_1)
220	add	r0, r1, r2
221	mov	r1, r3
222	ldr	r2, [sp, #0]
223	teq	r2, #0
224	moveq	pc, lr
225
2261:	ldrb	r3, [r1], #1
227	strb	r3, [r0], #1
228	subs	r2, r2, #1
229	bne	1b
230
231	mov	pc, lr
232
233ENTRY(generic_armv4_bs_wr_2)
234	add	r0, r1, r2
235	mov	r1, r3
236	ldr	r2, [sp, #0]
237	teq	r2, #0
238	moveq	pc, lr
239
2401:	ldrh	r3, [r1], #2
241	strh	r3, [r0], #2
242	subs	r2, r2, #1
243	bne	1b
244
245	mov	pc, lr
246
247ENTRY(generic_bs_wr_4)
248	add	r0, r1, r2
249	mov	r1, r3
250	ldr	r2, [sp, #0]
251	teq	r2, #0
252	moveq	pc, lr
253
2541:	ldr	r3, [r1], #4
255	str	r3, [r0], #4
256	subs	r2, r2, #1
257	bne	1b
258
259	mov	pc, lr
260
261/*
262 * set region
263 */
264
265ENTRY(generic_bs_sr_1)
266	add	r0, r1, r2
267	mov	r1, r3
268	ldr	r2, [sp, #0]
269	teq	r2, #0
270	moveq	pc, lr
271
2721:	strb	r1, [r0], #1
273	subs	r2, r2, #1
274	bne	1b
275
276	mov	pc, lr
277
278ENTRY(generic_armv4_bs_sr_2)
279	add	r0, r1, r2
280	mov	r1, r3
281	ldr	r2, [sp, #0]
282	teq	r2, #0
283	moveq	pc, lr
284
2851:	strh	r1, [r0], #2
286	subs	r2, r2, #1
287	bne	1b
288
289	mov	pc, lr
290
291ENTRY(generic_bs_sr_4)
292	add	r0, r1, r2
293	mov	r1, r3
294	ldr	r2, [sp, #0]
295	teq	r2, #0
296	moveq	pc, lr
297
2981:	str	r1, [r0], #4
299	subs	r2, r2, #1
300	bne	1b
301
302	mov	pc, lr
303
304/*
305 * copy region
306 */
307
308ENTRY(generic_armv4_bs_c_2)
309	add	r0, r1, r2
310	ldr	r2, [sp, #0]
311	add	r1, r2, r3
312	ldr	r2, [sp, #4]
313	teq	r2, #0
314	moveq	pc, lr
315
316	cmp	r0, r1
317	blt	2f
318
3191:	ldrh	r3, [r0], #2
320	strh	r3, [r1], #2
321	subs	r2, r2, #1
322	bne	1b
323
324	mov	pc, lr
325
3262:	add	r0, r0, r2, lsl #1
327	add	r1, r1, r2, lsl #1
328	sub	r0, r0, #2
329	sub	r1, r1, #2
330
3313:	ldrh	r3, [r0], #-2
332	strh	r3, [r1], #-2
333	subs	r2, r2, #1
334	bne	3b
335
336	mov	pc, lr
337