1 /* $OpenBSD: shpcicvar.h,v 1.7 2024/05/22 14:25:47 jsg Exp $ */ 2 /* $NetBSD: shpcicvar.h,v 1.6 2005/12/11 12:18:58 christos Exp $ */ 3 4 /*- 5 * Copyright (c) 2005 NONAKA Kimihiro 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef SH_DEV_PCICVAR_H 31 #define SH_DEV_PCICVAR_H 32 33 #include <machine/bus.h> 34 35 bus_space_tag_t shpcic_get_bus_io_tag(void); 36 bus_space_tag_t shpcic_get_bus_mem_tag(void); 37 bus_dma_tag_t shpcic_get_bus_dma_tag(void); 38 39 int shpcic_bus_maxdevs(void *v, int busno); 40 pcitag_t shpcic_make_tag(void *v, int bus, int device, int function); 41 void shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp); 42 int shpcic_conf_size(void *, pcitag_t); 43 pcireg_t shpcic_conf_read(void *v, pcitag_t tag, int reg); 44 void shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data); 45 46 struct config_bus_space { 47 u_int32_t bus_base; 48 u_int32_t bus_size; 49 int bus_io; 50 }; 51 52 struct shpcic_softc { 53 struct device s_dev; 54 55 pci_chipset_tag_t sc_pci_chipset; 56 57 /* Structures to do bus fixup */ 58 int nbogus; 59 struct extent *extent_mem; 60 struct extent *extent_port; 61 struct config_bus_space sc_membus_space; 62 struct config_bus_space sc_iobus_space; 63 }; 64 65 /* 66 * shpcic io/mem bus space 67 */ 68 int shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size, int flags, 69 bus_space_handle_t *bshp); 70 void shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size); 71 int shpcic_iomem_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, 72 bus_size_t size, bus_space_handle_t *nbshp); 73 int shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend, 74 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, 75 bus_addr_t *bpap, bus_space_handle_t *bshp); 76 void shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size); 77 void *shpcic_iomem_vaddr(void *v, bus_space_handle_t bsh); 78 79 /* read single */ 80 uint8_t shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset); 81 uint16_t shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset); 82 uint32_t shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset); 83 uint8_t shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset); 84 uint16_t shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset); 85 uint32_t shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset); 86 87 /* read multi */ 88 void shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh, 89 bus_size_t offset, uint8_t *addr, bus_size_t count); 90 void shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh, 91 bus_size_t offset, uint16_t *addr, bus_size_t count); 92 void shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh, 93 bus_size_t offset, uint32_t *addr, bus_size_t count); 94 void shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh, 95 bus_size_t offset, uint8_t *addr, bus_size_t count); 96 void shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh, 97 bus_size_t offset, uint16_t *addr, bus_size_t count); 98 void shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh, 99 bus_size_t offset, uint32_t *addr, bus_size_t count); 100 101 /* read raw multi */ 102 void shpcic_io_read_raw_multi_2(void *v, bus_space_handle_t bsh, 103 bus_size_t offset, uint8_t *addr, bus_size_t count); 104 void shpcic_io_read_raw_multi_4(void *v, bus_space_handle_t bsh, 105 bus_size_t offset, uint8_t *addr, bus_size_t count); 106 void shpcic_mem_read_raw_multi_2(void *v, bus_space_handle_t bsh, 107 bus_size_t offset, uint8_t *addr, bus_size_t count); 108 void shpcic_mem_read_raw_multi_4(void *v, bus_space_handle_t bsh, 109 bus_size_t offset, uint8_t *addr, bus_size_t count); 110 111 /* read region */ 112 void shpcic_io_read_region_1(void *v, bus_space_handle_t bsh, 113 bus_size_t offset, uint8_t *addr, bus_size_t count); 114 void shpcic_io_read_region_2(void *v, bus_space_handle_t bsh, 115 bus_size_t offset, uint16_t *addr, bus_size_t count); 116 void shpcic_io_read_region_4(void *v, bus_space_handle_t bsh, 117 bus_size_t offset, uint32_t *addr, bus_size_t count); 118 void shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh, 119 bus_size_t offset, uint8_t *addr, bus_size_t count); 120 void shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh, 121 bus_size_t offset, uint16_t *addr, bus_size_t count); 122 void shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh, 123 bus_size_t offset, uint32_t *addr, bus_size_t count); 124 125 /* read raw region */ 126 void shpcic_io_read_raw_region_2(void *v, bus_space_handle_t bsh, 127 bus_size_t offset, uint8_t *addr, bus_size_t count); 128 void shpcic_io_read_raw_region_4(void *v, bus_space_handle_t bsh, 129 bus_size_t offset, uint8_t *addr, bus_size_t count); 130 void shpcic_mem_read_raw_region_2(void *v, bus_space_handle_t bsh, 131 bus_size_t offset, uint8_t *addr, bus_size_t count); 132 void shpcic_mem_read_raw_region_4(void *v, bus_space_handle_t bsh, 133 bus_size_t offset, uint8_t *addr, bus_size_t count); 134 135 /* write single */ 136 void shpcic_io_write_1(void *v, bus_space_handle_t bsh, 137 bus_size_t offset, uint8_t data); 138 void shpcic_io_write_2(void *v, bus_space_handle_t bsh, 139 bus_size_t offset, uint16_t data); 140 void shpcic_io_write_4(void *v, bus_space_handle_t bsh, 141 bus_size_t offset, uint32_t data); 142 void shpcic_mem_write_1(void *v, bus_space_handle_t bsh, 143 bus_size_t offset, uint8_t data); 144 void shpcic_mem_write_2(void *v, bus_space_handle_t bsh, 145 bus_size_t offset, uint16_t data); 146 void shpcic_mem_write_4(void *v, bus_space_handle_t bsh, 147 bus_size_t offset, uint32_t data); 148 149 /* write multi */ 150 void shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh, 151 bus_size_t offset, const uint8_t *addr, bus_size_t count); 152 void shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh, 153 bus_size_t offset, const uint16_t *addr, bus_size_t count); 154 void shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh, 155 bus_size_t offset, const uint32_t *addr, bus_size_t count); 156 void shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh, 157 bus_size_t offset, const uint8_t *addr, bus_size_t count); 158 void shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh, 159 bus_size_t offset, const uint16_t *addr, bus_size_t count); 160 void shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh, 161 bus_size_t offset, const uint32_t *addr, bus_size_t count); 162 163 /* write raw multi */ 164 void shpcic_io_write_raw_multi_2(void *v, bus_space_handle_t bsh, 165 bus_size_t offset, const uint8_t *addr, bus_size_t count); 166 void shpcic_io_write_raw_multi_4(void *v, bus_space_handle_t bsh, 167 bus_size_t offset, const uint8_t *addr, bus_size_t count); 168 void shpcic_mem_write_raw_multi_2(void *v, bus_space_handle_t bsh, 169 bus_size_t offset, const uint8_t *addr, bus_size_t count); 170 void shpcic_mem_write_raw_multi_4(void *v, bus_space_handle_t bsh, 171 bus_size_t offset, const uint8_t *addr, bus_size_t count); 172 173 /* write region */ 174 void shpcic_io_write_region_1(void *v, bus_space_handle_t bsh, 175 bus_size_t offset, const uint8_t *addr, bus_size_t count); 176 void shpcic_io_write_region_2(void *v, bus_space_handle_t bsh, 177 bus_size_t offset, const uint16_t *addr, bus_size_t count); 178 void shpcic_io_write_region_4(void *v, bus_space_handle_t bsh, 179 bus_size_t offset, const uint32_t *addr, bus_size_t count); 180 void shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh, 181 bus_size_t offset, const uint8_t *addr, bus_size_t count); 182 void shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh, 183 bus_size_t offset, const uint16_t *addr, bus_size_t count); 184 void shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh, 185 bus_size_t offset, const uint32_t *addr, bus_size_t count); 186 187 /* write raw region */ 188 void shpcic_io_write_raw_region_2(void *v, bus_space_handle_t bsh, 189 bus_size_t offset, const uint8_t *addr, bus_size_t count); 190 void shpcic_io_write_raw_region_4(void *v, bus_space_handle_t bsh, 191 bus_size_t offset, const uint8_t *addr, bus_size_t count); 192 void shpcic_mem_write_raw_region_2(void *v, bus_space_handle_t bsh, 193 bus_size_t offset, const uint8_t *addr, bus_size_t count); 194 void shpcic_mem_write_raw_region_4(void *v, bus_space_handle_t bsh, 195 bus_size_t offset, const uint8_t *addr, bus_size_t count); 196 197 /* set multi */ 198 void shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh, 199 bus_size_t offset, uint8_t val, bus_size_t count); 200 void shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh, 201 bus_size_t offset, uint16_t val, bus_size_t count); 202 void shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh, 203 bus_size_t offset, uint32_t val, bus_size_t count); 204 void shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh, 205 bus_size_t offset, uint8_t val, bus_size_t count); 206 void shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh, 207 bus_size_t offset, uint16_t val, bus_size_t count); 208 void shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh, 209 bus_size_t offset, uint32_t val, bus_size_t count); 210 211 /* set region */ 212 void shpcic_io_set_region_1(void *v, bus_space_handle_t bsh, 213 bus_size_t offset, uint8_t val, bus_size_t count); 214 void shpcic_io_set_region_2(void *v, bus_space_handle_t bsh, 215 bus_size_t offset, uint16_t val, bus_size_t count); 216 void shpcic_io_set_region_4(void *v, bus_space_handle_t bsh, 217 bus_size_t offset, uint32_t val, bus_size_t count); 218 void shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh, 219 bus_size_t offset, uint8_t val, bus_size_t count); 220 void shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh, 221 bus_size_t offset, uint16_t val, bus_size_t count); 222 void shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh, 223 bus_size_t offset, uint32_t val, bus_size_t count); 224 225 /* copy region */ 226 void shpcic_io_copy_1(void *v, bus_space_handle_t bsh1, 227 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 228 bus_size_t count); 229 void shpcic_io_copy_2(void *v, bus_space_handle_t bsh1, 230 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 231 bus_size_t count); 232 void shpcic_io_copy_4(void *v, bus_space_handle_t bsh1, 233 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 234 bus_size_t count); 235 void shpcic_mem_copy_1(void *v, bus_space_handle_t bsh1, 236 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 237 bus_size_t count); 238 void shpcic_mem_copy_2(void *v, bus_space_handle_t bsh1, 239 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 240 bus_size_t count); 241 void shpcic_mem_copy_4(void *v, bus_space_handle_t bsh1, 242 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 243 bus_size_t count); 244 #endif /* SH_DEV_PCICVAR_H */ 245