1 /* $OpenBSD: shpcicvar.h,v 1.6 2010/12/04 17:06:32 miod Exp $ */ 2 /* $NetBSD: shpcicvar.h,v 1.6 2005/12/11 12:18:58 christos Exp $ */ 3 4 /*- 5 * Copyright (c) 2005 NONAKA Kimihiro 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef SH_DEV_PCICVAR_H 31 #define SH_DEV_PCICVAR_H 32 33 #include <machine/bus.h> 34 35 bus_space_tag_t shpcic_get_bus_io_tag(void); 36 bus_space_tag_t shpcic_get_bus_mem_tag(void); 37 bus_dma_tag_t shpcic_get_bus_dma_tag(void); 38 39 int shpcic_bus_maxdevs(void *v, int busno); 40 pcitag_t shpcic_make_tag(void *v, int bus, int device, int function); 41 void shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp); 42 int shpcic_conf_size(void *, pcitag_t); 43 pcireg_t shpcic_conf_read(void *v, pcitag_t tag, int reg); 44 void shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data); 45 46 int shpcic_set_intr_priority(int intr, int level); 47 void *shpcic_intr_establish(int evtcode, int (*ih_func)(void *), void *ih_arg, 48 const char *ih_name); 49 void shpcic_intr_disestablish(void *ih); 50 51 struct config_bus_space { 52 u_int32_t bus_base; 53 u_int32_t bus_size; 54 int bus_io; 55 }; 56 57 struct shpcic_softc { 58 struct device s_dev; 59 60 pci_chipset_tag_t sc_pci_chipset; 61 62 /* Structures to do bus fixup */ 63 int nbogus; 64 struct extent *extent_mem; 65 struct extent *extent_port; 66 struct config_bus_space sc_membus_space; 67 struct config_bus_space sc_iobus_space; 68 }; 69 70 void pci_addr_fixup(void *v, int maxbus); 71 72 /* 73 * shpcic io/mem bus space 74 */ 75 int shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size, int flags, 76 bus_space_handle_t *bshp); 77 void shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size); 78 int shpcic_iomem_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, 79 bus_size_t size, bus_space_handle_t *nbshp); 80 int shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend, 81 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, 82 bus_addr_t *bpap, bus_space_handle_t *bshp); 83 void shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size); 84 void *shpcic_iomem_vaddr(void *v, bus_space_handle_t bsh); 85 86 /* read single */ 87 uint8_t shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset); 88 uint16_t shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset); 89 uint32_t shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset); 90 uint8_t shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset); 91 uint16_t shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset); 92 uint32_t shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset); 93 94 /* read multi */ 95 void shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh, 96 bus_size_t offset, uint8_t *addr, bus_size_t count); 97 void shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh, 98 bus_size_t offset, uint16_t *addr, bus_size_t count); 99 void shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh, 100 bus_size_t offset, uint32_t *addr, bus_size_t count); 101 void shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh, 102 bus_size_t offset, uint8_t *addr, bus_size_t count); 103 void shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh, 104 bus_size_t offset, uint16_t *addr, bus_size_t count); 105 void shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh, 106 bus_size_t offset, uint32_t *addr, bus_size_t count); 107 108 /* read raw multi */ 109 void shpcic_io_read_raw_multi_2(void *v, bus_space_handle_t bsh, 110 bus_size_t offset, uint8_t *addr, bus_size_t count); 111 void shpcic_io_read_raw_multi_4(void *v, bus_space_handle_t bsh, 112 bus_size_t offset, uint8_t *addr, bus_size_t count); 113 void shpcic_mem_read_raw_multi_2(void *v, bus_space_handle_t bsh, 114 bus_size_t offset, uint8_t *addr, bus_size_t count); 115 void shpcic_mem_read_raw_multi_4(void *v, bus_space_handle_t bsh, 116 bus_size_t offset, uint8_t *addr, bus_size_t count); 117 118 /* read region */ 119 void shpcic_io_read_region_1(void *v, bus_space_handle_t bsh, 120 bus_size_t offset, uint8_t *addr, bus_size_t count); 121 void shpcic_io_read_region_2(void *v, bus_space_handle_t bsh, 122 bus_size_t offset, uint16_t *addr, bus_size_t count); 123 void shpcic_io_read_region_4(void *v, bus_space_handle_t bsh, 124 bus_size_t offset, uint32_t *addr, bus_size_t count); 125 void shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh, 126 bus_size_t offset, uint8_t *addr, bus_size_t count); 127 void shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh, 128 bus_size_t offset, uint16_t *addr, bus_size_t count); 129 void shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh, 130 bus_size_t offset, uint32_t *addr, bus_size_t count); 131 132 /* read raw region */ 133 void shpcic_io_read_raw_region_2(void *v, bus_space_handle_t bsh, 134 bus_size_t offset, uint8_t *addr, bus_size_t count); 135 void shpcic_io_read_raw_region_4(void *v, bus_space_handle_t bsh, 136 bus_size_t offset, uint8_t *addr, bus_size_t count); 137 void shpcic_mem_read_raw_region_2(void *v, bus_space_handle_t bsh, 138 bus_size_t offset, uint8_t *addr, bus_size_t count); 139 void shpcic_mem_read_raw_region_4(void *v, bus_space_handle_t bsh, 140 bus_size_t offset, uint8_t *addr, bus_size_t count); 141 142 /* write single */ 143 void shpcic_io_write_1(void *v, bus_space_handle_t bsh, 144 bus_size_t offset, uint8_t data); 145 void shpcic_io_write_2(void *v, bus_space_handle_t bsh, 146 bus_size_t offset, uint16_t data); 147 void shpcic_io_write_4(void *v, bus_space_handle_t bsh, 148 bus_size_t offset, uint32_t data); 149 void shpcic_mem_write_1(void *v, bus_space_handle_t bsh, 150 bus_size_t offset, uint8_t data); 151 void shpcic_mem_write_2(void *v, bus_space_handle_t bsh, 152 bus_size_t offset, uint16_t data); 153 void shpcic_mem_write_4(void *v, bus_space_handle_t bsh, 154 bus_size_t offset, uint32_t data); 155 156 /* write multi */ 157 void shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh, 158 bus_size_t offset, const uint8_t *addr, bus_size_t count); 159 void shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh, 160 bus_size_t offset, const uint16_t *addr, bus_size_t count); 161 void shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh, 162 bus_size_t offset, const uint32_t *addr, bus_size_t count); 163 void shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh, 164 bus_size_t offset, const uint8_t *addr, bus_size_t count); 165 void shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh, 166 bus_size_t offset, const uint16_t *addr, bus_size_t count); 167 void shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh, 168 bus_size_t offset, const uint32_t *addr, bus_size_t count); 169 170 /* write raw multi */ 171 void shpcic_io_write_raw_multi_2(void *v, bus_space_handle_t bsh, 172 bus_size_t offset, const uint8_t *addr, bus_size_t count); 173 void shpcic_io_write_raw_multi_4(void *v, bus_space_handle_t bsh, 174 bus_size_t offset, const uint8_t *addr, bus_size_t count); 175 void shpcic_mem_write_raw_multi_2(void *v, bus_space_handle_t bsh, 176 bus_size_t offset, const uint8_t *addr, bus_size_t count); 177 void shpcic_mem_write_raw_multi_4(void *v, bus_space_handle_t bsh, 178 bus_size_t offset, const uint8_t *addr, bus_size_t count); 179 180 /* write region */ 181 void shpcic_io_write_region_1(void *v, bus_space_handle_t bsh, 182 bus_size_t offset, const uint8_t *addr, bus_size_t count); 183 void shpcic_io_write_region_2(void *v, bus_space_handle_t bsh, 184 bus_size_t offset, const uint16_t *addr, bus_size_t count); 185 void shpcic_io_write_region_4(void *v, bus_space_handle_t bsh, 186 bus_size_t offset, const uint32_t *addr, bus_size_t count); 187 void shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh, 188 bus_size_t offset, const uint8_t *addr, bus_size_t count); 189 void shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh, 190 bus_size_t offset, const uint16_t *addr, bus_size_t count); 191 void shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh, 192 bus_size_t offset, const uint32_t *addr, bus_size_t count); 193 194 /* write raw region */ 195 void shpcic_io_write_raw_region_2(void *v, bus_space_handle_t bsh, 196 bus_size_t offset, const uint8_t *addr, bus_size_t count); 197 void shpcic_io_write_raw_region_4(void *v, bus_space_handle_t bsh, 198 bus_size_t offset, const uint8_t *addr, bus_size_t count); 199 void shpcic_mem_write_raw_region_2(void *v, bus_space_handle_t bsh, 200 bus_size_t offset, const uint8_t *addr, bus_size_t count); 201 void shpcic_mem_write_raw_region_4(void *v, bus_space_handle_t bsh, 202 bus_size_t offset, const uint8_t *addr, bus_size_t count); 203 204 /* set multi */ 205 void shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh, 206 bus_size_t offset, uint8_t val, bus_size_t count); 207 void shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh, 208 bus_size_t offset, uint16_t val, bus_size_t count); 209 void shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh, 210 bus_size_t offset, uint32_t val, bus_size_t count); 211 void shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh, 212 bus_size_t offset, uint8_t val, bus_size_t count); 213 void shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh, 214 bus_size_t offset, uint16_t val, bus_size_t count); 215 void shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh, 216 bus_size_t offset, uint32_t val, bus_size_t count); 217 218 /* set region */ 219 void shpcic_io_set_region_1(void *v, bus_space_handle_t bsh, 220 bus_size_t offset, uint8_t val, bus_size_t count); 221 void shpcic_io_set_region_2(void *v, bus_space_handle_t bsh, 222 bus_size_t offset, uint16_t val, bus_size_t count); 223 void shpcic_io_set_region_4(void *v, bus_space_handle_t bsh, 224 bus_size_t offset, uint32_t val, bus_size_t count); 225 void shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh, 226 bus_size_t offset, uint8_t val, bus_size_t count); 227 void shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh, 228 bus_size_t offset, uint16_t val, bus_size_t count); 229 void shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh, 230 bus_size_t offset, uint32_t val, bus_size_t count); 231 232 /* copy region */ 233 void shpcic_io_copy_1(void *v, bus_space_handle_t bsh1, 234 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 235 bus_size_t count); 236 void shpcic_io_copy_2(void *v, bus_space_handle_t bsh1, 237 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 238 bus_size_t count); 239 void shpcic_io_copy_4(void *v, bus_space_handle_t bsh1, 240 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 241 bus_size_t count); 242 void shpcic_mem_copy_1(void *v, bus_space_handle_t bsh1, 243 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 244 bus_size_t count); 245 void shpcic_mem_copy_2(void *v, bus_space_handle_t bsh1, 246 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 247 bus_size_t count); 248 void shpcic_mem_copy_4(void *v, bus_space_handle_t bsh1, 249 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 250 bus_size_t count); 251 #endif /* SH_DEV_PCICVAR_H */ 252